Analysis of clocked sequential networks keywords: Mealy, Moore Consider : a sequential parity checker an 8th bit is added to each group of 7 bits such that the total # of 1 bits is odd for odd parity if any odd # of bits in the 8 bit block changes value then the presence of this error can be detected we'll design a parity checker for serial data: first generate a state graph S0: even number of 1's received so far S1: odd number of 1's received so far generate the state table State Table X : input Present State Next State 0 S0 S0 1 S0 S1 0 S1 S1 1 S1 S0 Since we only have two states, one bit will be used (or a single flipflop) We set up a table showing the next state as a function of the present state and the value of the current input signal X. We will use a T flip flop X Q Q+ T
0 0 0 0 1 0 1 1 0 1 1 0 1 1 0 1 from this table note that T is 1 whenever X is 1. so we do not need to do any further simplification, our circuit solution is:. If the output of a sequential circuit is a function of the present state only the network is referred to as a MOORE machine. (has output associated with the state in the state graph) output can change only when the state changes. If the output is a function of both the present state and the input, the newtork is a MEALY machine ( has output associated with arrows). output can change when the input changes as well as when the state changes. Stages of Sequential network design 1. construct state graph 2. identify how many states are required, allocate bits to represent these states (State Assignment) 3. from state tables, implement karnaugh maps
4. complete design of meally or moore machine Designing with MSI components note: state graphs that have a loop of states, with few additional state transitions can be realized with a counter (synchronous counter with load and clear) Example, design a sequential network using 74S163 counter Function of 74S163 counter 1. clear = 0 all flipflops set to 0 following rising edge of clock. 2. clea = 1, load = 0, D inputs transferred in parallel to flipflops after rising edge of clock. 3. clear = load = 1 and P = T =1, count is enabled counter state incremented by 1 after each rising edge of clock. State Table (note: P = T enables count) clear load P = T Qd+ Qc+ Qb+ Qa+ function 0 X X 0 0 0 0 clear 1 0 X Dd Dc Db Da parallel load 1 1 0 Qd Qc Qb Qa no change 1 1 1 Present state + 1 increment counter Now consider designing with this counter to implement a state machine defined below, where the input signal is X. (note arcs shown with both "0,1" on them, indicate a mandatory transition to the next state for either case X=0 or X=1).
Note only 3 bits of state are used, ie. S1 = 001 = CBA. Create state table, derive counter inputs from state table X State C B A C+ B+ A+ clear load Dc Db Da P = T 0 S0 000 001 1 1 x x x 1 0 S1 001 010 1 1 x x x 1 0 S2 010 000 0 X x x x x 0 S3 011 110 1 0 1 1 0 x 0 S4 100 100 1 1 x x x 0 0 S5 101 011 1 0 0 1 1 x 0 S6 110 000 0 X x x x x 1 S0 000 001 1 1 x x x 1 1 S1 001 010 1 1 x x x 1 1 S2 010 011 1 1 x x x 1 1 S3 011 100 1 1 x x x 1 1 S4 100 101 1 1 x x x 1 1 S5 101 110 1 1 x x x 1 1 S6 110 000 0 X x x x x 0 or 1 Sx 111 XXX X X x x x x Then derive Kmaps for clear, load, PT, Da, Db, Dc Click here for kmaps ie. Kmap for PT X A \ B C 00 01 11 10 00 1 0 x x 01 1 x x x 11 1 1 x 1
10 1 1 x 1 therefore PT = (c' + x ) Circuit is given below, with Db=1 Three State Logic and Register Transfers 3 state logic facilitates transfer of data among a group of registers note: if outputs of 2 or more gates are connected together the circuit will not operate properly in general ie if one gate outputs 0 and the other gate outputs 1 then when the outputs are connected together the output may be 0 or 1 or some intermediate value. so we use tristate buffers (or 3-state buffers) A: data input, B: gate or control, C: output signal. When B=0, the buffer acts as an open circuit (output C is effectively disconnnected from the buffer output, so that no current can flow. This is called high-impedance state (Hi-Z) of the output. Ie. the circuit offers very high resistance or impedance to the flow of current). A B C 0 0 Z 1 0 Z 0 1 0 1 1 1 Z represents high impedance state. below, 74LS374 is an octal register with 3-state outputs.
Below is an example of a bus, where several outputs are connected to the same wire. Design of Sequential Networks Using ROMs Example of mealy network designed with ROM (similar to PLA, except in PLA design, assignment of states plays important role in reducing costs). For example ROM design may require 16 words by 4 bit ROM, or alternatively in PLA design 9 product terms. Design Using PLDs
Design with FPGA, involves mapping our design into a number of combinational logic blocks where each logic block may be ie. XC2000 series, 1 function of 4 variables 2 functions of 3 variables ie. XC3000 series 5-input look up table, 1 function of 5 variables 2 4-input look up tables, 2 functions of 4 variables Example: realize the following expression in XC2000 FPGA Qa+= (Sh Si) + Sh' L Da + Sh' L' Qa, a function of 5 variables, requiring two logic blocks in XC2000 technology. Factoring yields the expression Qa+= (Sh Si) + Sh' F1, where F1 =( L Da + L' Qa) In fact this equation is a part of the 74178 shift register defined by SH(shift) L(load) 0 0 0 1 1 X Qa+ Qb+ Qc+ Qd+ Qa Qb Qc Qd (no change) Da Db Dc Dd (parallel load) SI Qa Qb Qc (right shift) where the next state equation is Qa+ = (Sh Si) + Sh' L Da + Sh' L' Qa, realizing this as a sequential element using two logic blocks with the D flipflops(included in block in FPGA), we get:
Implementing a 5 variable logic function with XC2000 series requires the following arrangement in general: Iterative Design with multiple outputs Design with mealy state diagrams extract truth table design logic of cell (or block) Example: Design the following circuit: Zi is 1 iff input to cell i (Xi) is 0 and inputs to cells immediately to left of celli consists of group of an even # of consecutive 1's. X= 01100111011110000100 Z= 00010000000001000000 we need 3 states: reset S0, odd # 1's S1, S2 even # of 1's.
state diagram is: Si ai bi ai+1 bi+1 for ai+1 bi+1 for Zi : xi=0 xi=0 xi=1 xi=1 S0 00 00 01 0 0 S1 01 00 10 0 0 S2 10 00 01 1 0 so cell is Note: similarly with iterative binary adder network one can obtain sequential "serial adder", see below:
Other Sequential Designs Now we can make a parallel adder with accumulator parity checker (with input X) revisited as sequential circuit: magnitude comparator (with inputs X,Z) as sequential circuit: