Clock Strategy Clocked Systems Latch and Flip-flops System timing Clock skew High speed latch design Phase locked loop ynamic logic Multiple phase Clock distribution
Clocked Systems Most VLSI systems are a combination of pipelines and finite state machines(fsm) Pipelined systems Input Logic Logic... output CLK CLK Finite state machine Comb. Logic CLK or CLKS
Single-phase timing waveforms Clock Cycle Time (T c ) Tc: cycle time (period) data Setup Time (T s ) Hold Time (T h ) Clock-to- elay (T q ) CLK Ts: setup time -- the time before the edge during which the data input () has to be stable Th: hold time -- the time after the edge during which the data input () has to remain stable Tq: -to- delay -- The delay from the edge to the output
Latches and flip-flops 0 1 s CLK (a) Negative Latch (Level sensitive) 0 1 s CLK (b) Positive Latch (Level sensitive)
Latches and flip-flops 0 1 s CLK master M 0 1 s CLK slave M (c) Positive edge-triggered register(single-phase ) =0 =1 master slave (d) Pass transistor/inverter implementation
System timing (A) Positive-edge triggered Register A Tq Combinational Logic Td Ts Register B Tc Tq Td Ts Tc >Tq + Td + Ts (B) Alternatively, one may use latches as storage elements to save area. Latch A Tq Combinational Logic Td Ts Latch B
System timing (con t) (C) A B Latch A Tq Combinational Ts Combinational Latch Latch Logic Logic B c Tda Tdb Tc1 Tco Tqa Tda Tsb Tqb Tdb Tsc Tc1>Tqa+Tda+Tsb Tco>Tqb+Tdb+Tsc If Tc=Tc1+Tco and Tc1=Tco, Tqa=Tqb, Tsb=Tsc => The limit is Tc = Tda + Tdb + 2(Tq+Ts)
Racing due to skew Td REG 2 1 0 1-bit Logic d q REG 1-bit d q M 1 M 2 1. If T c2 > T c1 + t q1 + t d2 M 2 may sample a wrong data (current data) Transparency problem delay Tc 1 Tc 2 delay Tc 1 2. If T c1 + t q1 + t d2 >T c (cycle time) M 2 cannot sample the previous data Td 2 Old ata New ata Tc 2
Single-phase using -FF C1 L1 C2 L2 1) C2=C1 C2 C1 C1 = C2 or C2 = C1 C2 C1 C1 C2 C1 C2 2) C1=C2 Wrong data in L2 Correct data L1 L2 Comb C1 C2 CLK Wrong only if FSM --> "feedback" or Pipeline --> "feedthrough" Comb. Logic
To eliminate (reduce) time skew ( skew) 1.Balanced delay driver 2.Use buffers where necessary -in Large Load -in usually slightly smaller than the inverter 3.Very careful simulation(hspice) 4.Very small rise and fall time on the -- large buffer for large load 5.Multiple ing strategies
Some Implementations of ed latches Use a weak trickle inverter -ck ck eliminate a metal connection smaller area small inverter (low-gain, smaller W or large L) or Transmission-gate latch buffered input compared with a tri-state buffer
Typical symbolic layouts for latches (a) (b) (c) V V V - V SS - V SS - V SS - - - -
logic gate based latches (a) Level sensitive - (b) Edge triggered -
(a) Asynchronously settable and resettable F/Fs - -reset - (b) - - -reset - - - -set -
ynamic single latches The feedback inverter and transmission gate are eliminated. The latched value is stored on the capacitance of the input to the inverter (mainly gate capacitance) Clock-to- (T q ) is very small need to be very careful to prevent transparency problem. Internal inversion of the is often necessary. ynamic nodes should be always refreshed or clamped to a known state when in stand-by or low-power mode. - (a) - (b) -
ynamic single latches (con t) - - - - - (c)tristate inverter (d)master-slave F/F (e)
Refreshing for ynamic latches ynamic storage nodes are usually a gate capacitance. Assume the leakage current= 1 na C and the storage capacitance = 0.02PF ΔV Δi 12 5 = 0.02 10 9 10 = 100μs Even if the storage of the correct state is unimportant, the leakage may cause the storage node to assume a level that causes the inverter to draw significant current. 5V -> 2.5V large current must refresh every 100μs
(1) Phase locked loop (PLL) techniques (1) To synchronize internal and external s. (2) To synchronize data transfers between chips. (3) To operate the internal at a higher rate. pad route d data out chip PLL pad route d data out d d output pad (a) Without PLL d +d pad output pad (a) With PLL d +d pad
PLL techniques (2) (3) bus high speed tristate bus chip PLL pad PLL PLL / 4 route d d system To ensure the output of chips are synchronized with each other. output pad d +d pad Clock rate at d 4 = d = 4
Block diagram of a PLL circuit n F fb reference (F in ) Phase etector U Charge pump Filter VCO n*f in Phase detector: detect the difference between Ffb and Fin. If Ffb > Fin => pulse If Ffb > Fin =>U pulse Charge pump: charge or ischarge a capacitor according to and U. Filter: filter the capacitor output (smoother). VCO: Change the oscillation frequency depending on the control voltage. (Voltage Control Oscillator)
Phase etector F1 F2 F1 16/8 16/8 16/8 16/8 16/8 16/8 UP 16/8 If F1 falls before F2 => UP=1 If F2 falls before F1 => N=1 F2 16/8 16/8 16/8 16/8 16/8 16/8 16/8 N
Charge Pump N1 2/5 N2 2/5 N3 10/2 40/2 P1 P-REF CHGUP 40/2 N4 CHGN N-REF P-REF P-SWITCHSW0 SW1 CAP P-SWITCH SW0 SW1 N-REF P1 40/2 N5 40/2 IN 8/1 16/1 SW0 10/2 10/2 SW1 Bias circuit CAP charges when CHGUP=1 discharge when CHGN=1
Filter VCO in 2/6 4/6 2400/6 out 2400/6 32/1 control voltage 32/1 32/1 32/1 13stages 16/1 16/1 32/1 32/1 16xFsc 16/1 in out 16/1 16/1 VCO 16/1
Metastability Problem If the setup or hold time is not satisfied, I.e., changes at the activation edge of the, then the output will have a state depending on the timing relation between and CLK 4ns delay 2ns delay=2.2ns delay=2.3ns delay=2.4ns data - metastable point - metastable point - No Problem Long delay Output error
Metastable state in a pair of inverters A Inv1 B To Solve the metastability problem: Setup time is shorter than the -to- delays in a synchronization system. VB Inv1 Inv2 For asynchronous input : need a special circuit called synchronizer. metastable point Inv2 VA 0V 2.5V 5V
to p-logic blocks Single-phase N-P CMOS dynamic logic Combine N-P section of domino logic with ed CMOS (C 2 MOS) latch as the output stage. to n-logic blocks to p-logic blocks to n-logic blocks - - to - section Inputs from - stages (a) n-logic block - - to - section p-logic C 2 MOS latch block From n or buffered p-logic n-p CMOS logic stage (c) (b) - logic evaluation Precharge p-logic C 2 MOS n-logic block latch block n-p CMOS - logic stage logic Precharge evaluation - logic evaluation Precharge - 0 1 1 0
esign rules for N-P CMOS dynamic logic Two problems to be solved 1.Each section must be internally race free. 2.When different section are cascaded to from pipelined system, skew should not cause a problem. R1: uring precharge, logicblocks must be switched off. R2: uring evaluation, internal inputs can make only one transition. When a static logic is used in a N-P CMOS dynamic logic, it should be placed after dynamic logic (I.e., one should keep the static logic up to the C 2 MOS latch. Reason: static logic after creates a glitch at its output.
- R3: There exists in each logic block at least one dynamic gate that is separated from the previous C 2 MOS output stage by an even number of inventions. or R4: The total number of inversions between two consecutive C 2 MOS stage is even. - Reason: 1 1 C 2 MOS or C 2 MOS or omino 0 0 The same evaluation phase in a section at least one even number of dynamic stage inversions C 2 MOS latch output stage OR (- section) even umber of inversions C 2 MOS latch ( section)
Two phase ing -phi 1 phi 1 phi 2 -phi 2 phi 1 phi 2 (c) phi logic 1 phi logic 2 small dealy overlap skewed clokcs (a) phi 1 phi 2 FF 1 (b) phi 1 =1 phi 2 =0 phi 1 =0 phi 2 =1 C 1 C 1 C 2 C 2 (d) phi 1 =1 phi 2 =0 C 1 overlap slow rise time C 2
Two phase generation 1. Globally distribute two s with or without their complements. 3. A single global and locally generated two-phase s Two-phase generator φ 1 φ 2 elay for non-overlap period
Two phase registers -phi 1 -phi 2 high level =V -V tn phi 1 phi 2 EF1 (a) phi 1 p leakers phi 2 EF 1A -phi 1 -phi 2 -phi 1 -phi 2 n 1 n 2 (b) phi 1 phi 2 phi 1 phi 2 phi 1 phi 2 EF 1B EF2 Both of these dynamic registers have to drive a local storage gate. EF3 (c)
Two phase logic 1. Static logic with two phase registers 2. ynamic logic -phi 1 -phi 2 Logic Logic φ 1 φ 2 from phi 2 stage -phi 1 phi 1 phi 1 phi 1 n-logic -phi 2 phi 2 phi 2 phi 1 n-logic to phi 1 stage phi evaluate phi logic 1 1 precharge phi precharge phi 1 logic 1 logic latch phi latch phi 2 data 2 data evaluate phi 2 evaluate phi 2 phi 2 logic logic precharge phi 2 logic latch phi 1 data
Four-Phase φ 1 φ 1 Four-Phase logic ing method φ 1 φ 2 φ 2 φ 3 nonoverlapping φ 2 φ 4 Slave Latch Logic Master Latch Logic 1 3 2 n1 4 1 2 3 1 2 3 4 1 (a) 3 inv1 inv2 4 1 3 12 34 1 2 3 1 3 4 (b)
Clock distribution 1. A single large buffer 2. A distributed--tree approach n-bit datapath n-bit datapath n-bit datapath n-bit datapath n-bit datapath delays have to match between stages n-bit datapath n-bit datapath n-bit datapath n-bit datapath n-bit datapath n-bit datapath n-bit datapath
Trends in strategy For first-time designer, use static logic, single-phase static registers. For standard cell and gate-array design, single-phase may be the only choice. Two phase ing make timing design of RAMs, ROMs and PLAs easier. In modern process and circuits, cycle time is the main concern => single phased Processes are extremely dense => single phase