UM9 UMA SYSTEM DIAGRAM - PDF Free Download

+V/+V +.V PG. PG. PU ore PG. +.0_PH PG. +.V/+0.V PG. +.0VTT PG. UM VGORE harger PG. PG. LN LNE theros/r 0/00 board P K PG. PG. PG. R hannel PORT FI UM UM SYSTEM IGRM SOIMM Max. G SOIMM Max. G K TP M ROM PG. ITE 0 PG. WWN LNE WLN est ombo port PG.0 R hannel 0MHz US.0 PORT US.0 LP SUWOOFER MX INTEL rrandale.mm X.mm pin PG TP W INTEL PH Ibex Peak-m mm X mm 0pin FG TP W PG. PG.~ MI PG.~ zalia UIO OE LQ-GR PG. ST0 ST PIVPLSZE PG. H O oard US.0 Ports X US.0 RTS Speaker HP/MI PG. PORT0, PORT ard Reader PG. nalog MI oard PG. PG. PG. PG. HMI RT LVS Webcam PG. T T PG. PORT PORT PG..MHz LOK GEN SLGSPVTR PG. Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev LOK IGRM ate: Wednesday, January, 00 Sheet of HMI RT board LVS PG. PG. PG. FN & THERML GMT G0/ EM--IZL-TR PG. RT oard US.0 Ports X PG. PORT, Stackup TOP GN IN IN V OT

m 00m +.0V_PH +VIO_LK +.V_RUN +VSE_LK L0 L 0.U/ 0V 0U/.V_ H0KF-T_ 0.U/ 0V H0KF-T_ 0.U/ 0V 0U/.V_ 0.U/ 0V 0.U/ 0V 0.U/ 0V 0.U/ 0V Place each 0.uF cap close to pin P (Power ap quantities follow UM) 0 Place each 0.uF cap close to pin U0 +.V_RUN () LK_PH_M +VSE_LK +VIO_LK R LK_PH_M R *0P/0V N 0K/J_ K_PWRG_R /J_ PU_SEL 0 V_US V_L V_SR V_PU V_REF V_SR_IO V_PU_IO VSS_ST VSS_US VSS_L VSS_SR VSS_PU VSS_REF PU_STOP# K_PWRG/P#_. REF_0/PU_SEL K0 QFN PU-0 PU-0# PU- 0 PU-# OTT_LPR OT_LPR SR- SR-# ST 0 ST# MHz_nonSS MHz_SS LK_UF_LKP () LK_UF_LKN () LK_UF_REFLKP () LK_UF_REFLKN () LK_UF_PIE_GPLLP () LK_UF_PIE_GPLLN () LK_UF_REFSSLKP () LK_UF_REFSSLKN () Place R0 within 0." of /G XTL_OUT XTL_IN XOUT XIN (,) (,) SMT SMLK ST SLK GN SLGSPVTR +.V_RUN +.V_RUN XTL_IN Y XTL_OUT R *0K/J N R K/J_.MHZ P/0V_ P/0V_ PU_SEL K_PWRG_R R 0K/J_ () VR_PWRG_LKEN# N00W--F Q R *00K/J N PU_SEL PU0/=MHz (default) 0 PU0/=00MHz 0 *00P_N Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev lock Gen(ISLRSKLFT) ate: Monday, February 0, 00 Sheet of

() MI_TXN0 () MI_TXN () MI_TXN () MI_TXN () MI_TXP0 () MI_TXP () MI_TXP () MI_TXP () MI_RXN0 () MI_RXN () MI_RXN () MI_RXN () MI_RXP0 () MI_RXP () MI_RXP () MI_RXP () FI_TXN0 () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXP0 () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_FSYN0 () FI_FSYN () FI_INT () FI_LSYN0 () FI_LSYN U MI_RX#[0] MI_RX#[] MI_RX#[] MI_RX#[] MI_RX[0] MI_RX[] MI_RX[] MI_RX[] MI_TX#[0] G MI_TX#[] F MI_TX#[] H MI_TX#[] MI_TX[0] F MI_TX[] E MI_TX[] G MI_TX[] E FI_TX#[0] FI_TX#[] FI_TX#[] FI_TX#[] G FI_TX#[] E FI_TX#[] F FI_TX#[] G FI_TX#[] FI_TX[0] FI_TX[] 0 FI_TX[] FI_TX[] G FI_TX[] E0 FI_TX[] F0 FI_TX[] G FI_TX[] F FI_FSYN[0] E FI_FSYN[] MI Intel(R) FI FI_INT F FI_LSYN[0] FI_LSYN[] I,U_F_rPG,RP0 PI EXPRESS -- GRPHIS PEG_IOMPI PEG_IOMPO PEG_ROMPO PEG_RIS PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_OMP R PEG_RIS R K J J G G F F E 0 J H H F G E F F 0 0 L M M M0 L K M J K H0 H F E L M M L0 M K M H K G0 G F E./F_ 0/F_ H_PEI *P/0V N PM_SYN (0) (0) () H_PUET# () H_PEI H_THERM PM_SYN (0) H_PWRGOO () PM_RM_PWRG *00P_N (0) H_VTTPWRG (,,) PLTRST# TP0 R R R R TP R R TP TP TP TP TP TP0 TP TP TP 0/F_ 0/F_./F_./F_ 0/F_ H_OMP H_OMP H_OMP H_OMP0 H_PURST# H_TERR# R H_PROHOT# R0 PU_PLTRST# R0 H_PURST# R H_PWRGOO +.0V_VTT PM_RM_PWRG PLL_REF_SSLK:Embedded isplay Port PLL ifferential lock In. If no ep, do we need implement these R? U T OMP T OMP G OMP T OMP0 H SKTO# H_TERR# K TERR# T H_PROHOT# PEI N PROHOT# K THERMTRIP# MIS P RESET_OS# L PM_SYN N VPWRGOO_ N VPWRGOO_0 K SM_RMPWROK M TPPWRGOO M PU_PLTRST# VTTPWRGOO L.K_ RSTIN# THERML PWR MNGEMENT J PM#[0] K PM#[] K PM#[] J PM#[] J PM#[] H PM#[] K PM#[] H PM#[] I,U_F_rPG,RP0./F_./F_ */J N */J N LOKS R MIS JTG & PM H_VTTPWRG LK LK# LK_ITP R0 T0 LK_ITP# PEG_LK E PEG_LK# PLL_REF_SSLK PLL_REF_SSLK# SM_RMRST# F For ITP Lk LK_REFSSLKP_R LK_REFSSLKN_R Rb XP_TMS XP_TRST# XP_TI XP_TO XP_TI_M XP_TO_M Ra L SM_ROMP_0 R SM_ROMP[0] SM_ROMP_ SM_ROMP[] M R SM_ROMP_ R SM_ROMP[] N R0 PM_EXT_TS#[0] N PM_EXT_TS#[] P R R T PRY# PREQ# P XP_TLK TK N TMS TRST# P T TI T TO R TI_M R TO_M P R# N R XP_TO_M XP_TI_M XP_TRST# IS SG Ra Rb N 0 ohm 0 ohm N Rc 0 ohm N Rc R R R R0 SJ_00 XP_RESET# () 0 LK_PU_LKP (0) LK_PU_LKN (0) LK_PIE_GPLLP () LK_PIE_GPLLN () R_RMRST# (,) 00/F_./F_ 0/F_ 0K/J_ +.0V_VTT PM_EXTTS#0 () PM_EXTTS# () 0K/J_ +.0V_VTT *.K/F_N TP TP TP close Pin P TP0 JTG MPPING R 0 TP0 TP *0_N SJ_00 SJ_00 *0_N TP TP TP TP TP TP LK_REFSSLKP () LK_REFSSLKN () Intel Suggest to reserve 0 ohm below for PU P and R pins. *00P_N 00P *00P_N R /J_ PU THERMTRIP (,) IMVP_PWRG PM_THRMTRIP# () +.V_SUS Scan hain (efault) STUFF -> Ra, Rc, Re NO STUFF -> Rb, Rd H_THERM R *.K/J N Q *MMST0--F_N Q *N00W--F_N R.K/F PM_RM_PWRG PU Only GMH Only STUFF -> Ra, Rb NO STUFF -> Rc, Rd, Re STUFF -> Rd, Re NO STUFF -> Ra, Rb, Rc R K/F Use a voltage divider with VQ (. V) rail ON in S) and resistor combination of.k ±% (to VQ)/0±% (to GN) to convert to processor VTT level. Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PROESSER /(HOST&PEX) ate: Monday, February 0, 00 Sheet of

UURNLE/LRKSFIEL PROESSOR (R) 0 () M Q[0..] U M Q0 0 M Q S_Q[0] 0 M Q S_Q[] M Q S_Q[] M Q S_Q[] 0 M Q S_Q[] 0 M Q S_Q[] E0 M Q S_Q[] M Q S_Q[] M Q S_Q[] F0 M Q0 S_Q[] E M Q S_Q[0] F M Q S_Q[] E M Q S_Q[] M Q S_Q[] E M Q S_Q[] M Q S_Q[] H0 M Q S_Q[] G M Q S_Q[] K M Q S_Q[] J M Q0 S_Q[] G M Q S_Q[0] G0 M Q S_Q[] J M Q S_Q[] J0 M Q S_Q[] L M Q S_Q[] M M Q S_Q[] M M Q S_Q[] L M Q S_Q[] L M Q S_Q[] K M Q0 S_Q[] N M Q S_Q[0] P M Q S_Q[] H M Q S_Q[] F M Q S_Q[] K M Q S_Q[] K M Q S_Q[] F M Q S_Q[] G M Q S_Q[] J M Q S_Q[] J M Q0 S_Q[] J0 M Q S_Q[0] J M Q S_Q[] L0 M Q S_Q[] K M Q S_Q[] K M Q S_Q[] L M Q S_Q[] K M Q S_Q[] L M Q S_Q[] N M Q S_Q[] M0 M Q0 S_Q[] R M Q S_Q[0] L M Q S_Q[] M M Q S_Q[] N M Q S_Q[] T M Q S_Q[] P M Q S_Q[] M M Q S_Q[] N M Q S_Q[] M M Q S_Q[] T M Q0 S_Q[] T M Q S_Q[0] L M Q S_Q[] R M Q S_Q[] P S_Q[] R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] P Y Y P E E F M M0 M M H M M M M M G M M M M M N0 M M N M M M QSN0 F M QSN J M QSN N M QSN H M QSN K M QSN P M QSN T M QSN M QSP0 F M QSP H M QSP M M QSP H M QSP K0 M QSP N M QSP R M QSP Y M 0 W M M M V M M V T M M Y M U M M 0 T M U M G M T M V M M LKP0 () M LKN0 () M KE0 () M LKP () M LKN () M KE () M S#0 () M S# () M OT0 () M OT () M M[0..] () M QSN[0..] () M QSP[0..] () M [0..] () () M Q[0..] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U S_Q[0] S_Q[] S_Q[] S_Q[] E S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] F S_Q[0] F S_Q[] S_Q[] F S_Q[] F S_Q[] G S_Q[] H S_Q[] G S_Q[] J S_Q[] J S_Q[] G S_Q[0] G S_Q[] J S_Q[] J S_Q[] J S_Q[] K S_Q[] L S_Q[] M S_Q[] K S_Q[] K S_Q[] M S_Q[0] N S_Q[] F S_Q[] G S_Q[] J S_Q[] K S_Q[] G S_Q[] G S_Q[] J S_Q[] H S_Q[] K S_Q[0] K S_Q[] M S_Q[] N S_Q[] K S_Q[] K S_Q[] M S_Q[] M S_Q[] P S_Q[] N S_Q[] T S_Q[0] N S_Q[] N S_Q[] N S_Q[] T S_Q[] T S_Q[] N S_Q[] P S_Q[] P S_Q[] T S_Q[] T S_Q[0] P S_Q[] R0 S_Q[] T0 S_Q[] R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] W W M V V M M M0 E M M H M M K M M H M M L M M R M M T M M M QSN0 F M QSN J M QSN L M QSN H M QSN L M QSN R M QSN R M QSN M QSP0 E M QSP H M QSP M M QSP G M QSP L M QSP P M QSP R M QSP U V T V M 0 M M M R M T R M M R M R M R M M 0 P M R M F M P M N M M LKP0 () M LKN0 () M KE0 () M LKP () M LKN () M KE () M S#0 () M S# () M OT0 () M OT () M M[0..] () M signals are not present on larkfield processor. ll M signal can be left as N on larkfield and connect directly to GN on So-IMM side for larkfield design only M QSN[0..] () M QSP[0..] () M [0..] () () () () M S#0 M S# M S# U S_S[0] S_S[] S_S[] () () () M S#0 M S# M S# W R S_S[0] S_S[] S_S[] () () () M S# M RS# M WE# E S_S# S_RS# E S_WE# I,U_F_rPG,RP0 () () () M S# M RS# M WE# S_S# Y S_RS# S_WE# I,U_F_rPG,RP0 hannel Q[,,,], M[] Requires minimum mils spacing with all other signals, including data signals. hannel Q[,,,,,,0,,] Requires minimum mils spacing with all other signals, including data signals. Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PROESSER /(R) ate: Monday, February 0, 00 Sheet of

Name different with power +V_ORE *U/.V N *U/.V N 0 *U/.V N *U/.V N *U/.V N 0 U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ *0U/.V N *0U/.V N *0U/.V N *0U/.V N 0U/.V_ 0U/.V_ 0U/.V_ 0 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ *0U_N + *0U_N + Follow UM UF G V G V G V G V G V G0 V G V G V G V G V0 F V F V F V F V F V F0 V F V F V F V F V0 V V V V V 0 V V V V V0 V V V V V 0 V V V V V0 V V V V V 0 V V V V V0 Y V Y V Y V Y V Y V Y0 V Y V Y V Y V Y V0 V V V V V V V V V V V0 V V V V V V V V V0 U V U V U V U V U V U0 V U V U V U V U V0 R V R V R V R V R V R0 V R V R V R V R V0 P V P V P V P V P V P0 V P V P V P V P V00 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ PU ORE SUPPLY I,U_F_rPG,RP0 POWER.V RIL POWER SENSE LINES PU VIS VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ PSI# VI[0] VI[] VI[] VI[] VI[] VI[] VI[] PRO_PRSLPVR VTT_SELET ISENSE VTT_SENSE VSS_SENSE_VTT V_SENSE VSS_SENSE H H H H0 J J H H G G G G F F F F E E F0 E0 0 0 Y0 W0 U0 T0 J J J J N K K K L L M M M G +.0V_VTT 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ *0U/.V_00_N *0U/.V_00_N *0U/.V_00_N *0U/.V_00_N *0U/.V_00_N U/.V_ U/.V_ *U/.V N +.0V_VTT U/.V_ U/.V_ VTT Rail Values are uburndal VTT=.0V larksfield VTT=.V H_PSI# () VI0 () VI () VI () VI () VI () VI () VI () PRSLPVR () H_VTTVI=Low,.V H_VTTVI=High,.0V N R J J R0 0 0 TP I_MON () VTT_SENSE () TP 00/F_ 00/F_ +V_ORE VSENSE () VSSSENSE () Please note that +V_GFX_ORE should be.0v in uburndale + 0U/V_ +.0V_VTT +.0V_VTT +V_GFX_ORE 0U/.V_ U/.V_ 0 0 0 0 0U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ *U/.V N UG T VXG T VXG T VXG T VXG R VXG R VXG R VXG R VXG P VXG P VXG0 P VXG P VXG N VXG N VXG N VXG N VXG M VXG M VXG M VXG M VXG0 L VXG L VXG L VXG L VXG K VXG K VXG K VXG K VXG J VXG J VXG0 J VXG J VXG H VXG H VXG H VXG H VXG J VTT_ J VTT_ H VTT_ K VTT_ J VTT_ J VTT_0 J VTT_ H VTT_ G VTT_ G VTT_ G VTT_ F VTT_ E VTT_ E VTT_ GRPHIS POWER FI PEG & MI I,U_F_rPG,RP0 SENSE LINES GRPHIS VIs R -.V RILS.V.V VXG_SENSE VSSXG_SENSE GFX_VI[0] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VR_EN GFX_PRSLPVR GFX_IMON VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VTT0_ VTT0_0 VTT0_ VTT0_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VPLL VPLL VPLL R T M P N P M P N VI0 VI VI VI VI VI VI R GFXVR_EN T M J F E E Y W W U T T P N N L H P0 N0 L0 K0 J J0 J H H0 H L L M PRSLPVR H_PSI# 0 0 0 0 U/.V U/.V U/.V U/.V U/.V U/.V_ U/.V_ + R R R R R R R R R R R R R R R R R0 R V_XG_SENSE () VSS_XG_SENSE () GFXVR_VI_0 () GFXVR_VI_ () GFXVR_VI_ () GFXVR_VI_ () GFXVR_VI_ () GFXVR_VI_ () GFXVR_VI_ () R R0 0U/V_ 0U/.V_ *0U/.V_00_N U/.V_ *U/.V N U/.V_.U/.V.U/.V U/.V U/.V.K/F_ K/J_ *K/J N K/J_ *K/J N K/J_ *K/J N *K/J N K/J_ *K/J N K/J_ K/J_ *K/J N *K/J N K/J_ K/J_ *K/J N *K/J N K/J_ HFM_VI : Max.V LFM_VI : Min 0.V *K/F N +.0V_VTT +.V_RUN 0 GFXVR_EN () GFXVR_IMON () +.V_SUS +.0V_VTT *00P_N 0 close to R Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PROESSER /(POWER) ate: Monday, February 0, 00 Sheet of

UURNLE/LRKSFIEL PROESSOR (GN) UURNLE/LRKSFIEL PROESSOR( RESERVE, FG) 0 UH T0 VSS T VSS R VSS R VSS R VSS R VSS R VSS R0 VSS R VSS R VSS0 R VSS R VSS R VSS R VSS P0 VSS P VSS P VSS P0 VSS P VSS P VSS0 P VSS N VSS N VSS N VSS N0 VSS N VSS M VSS M VSS M VSS M0 VSS0 M VSS M VSS M VSS M VSS M VSS M VSS L VSS L VSS L VSS L0 VSS0 L VSS L VSS L VSS L VSS L VSS K VSS K VSS K VSS K0 VSS K VSS0 J VSS J VSS J0 VSS J VSS J VSS J VSS J VSS J VSS J VSS H VSS0 H VSS H VSS H VSS H VSS H0 VSS H VSS H VSS H VSS H VSS H0 VSS0 H VSS H VSS H VSS H VSS H VSS G0 VSS F VSS F VSS F VSS E VSS0 VSS I,U_F_rPG,RP0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS00 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 E E E E E0 E E E E E 0 0 0 Y Y Y W W W W W W0 W W W W W V0 U U U T T T T T T0 T T T T T R0 P P P N N N N N N0 N N N N N M0 L L L L L L K K K0 UI K VSS K VSS K VSS K VSS J VSS J0 VSS J VSS J VSS H VSS H VSS0 H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS0 H VSS G VSS G VSS G0 VSS G VSS G VSS G VSS F0 VSS F VSS F VSS0 F VSS F VSS F VSS E VSS E VSS E VSS E VSS E VSS E VSS E VSS00 E VSS0 E VSS0 E VSS0 E VSS0 VSS0 0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS T VSS_NTF T VSS_NTF R VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF I,U_F_rPG,RP0 NTF R R +M_VREF_Q_IMM0 +M_VREF_Q_IMM *0_N *0_N TP TP TP TP FG0 FG FG FG TP_RSV_R TP_RSV_R UE J S_IMM_VREF H S_IMM_VREF M0 FG[0] M FG[] P FG[] L FG[] L0 FG[] M FG[] N FG[] M FG[] K FG[] K FG[] K FG[0] J FG[] N0 FG[] N FG[] J FG[] J FG[] J0 FG[] K0 FG[] H RSV_TP_ P RSV L RSV L RSV L RSV J RSV G RSV M RSV L RSV G RSV G RSV E RSV E0 RSV RSV RSV 0 RSV 0 RSV U RSV T RSV0 RSV RSV RSV_NTF_ RSV_NTF_ J RSV J RSV RSV_NTF_ RSV_NTF_ RSV_NTF_0 RESERVE RSV_NTF_ J RSV J RSV H RSV K RSV L RSV R RSV_NTF_ J RSV J RSV P RSV_NTF_0 I,U_F_rPG,RP0 RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV RSV_TP_ RSV_TP_0 KEY RSV RSV RSV RSV RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_0 RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_0 RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ VSS T T R L L P0 P L T T P R T T P R R E F J H R R G E V V N W W N E P RSV_R RSV_R R R R TP SJ_00 *0_N *0_N For iscrete only The larkfield processor's PI Express interface may not meet PI Express.0 jitter specifications. Intel recommends placing a.0k +/- % pull down resistor to VSS on FG[] pin for both rpg and G components. This pull down resistor should be removed when this issue is fixed. FG0 FG FG FG R R R R *.0K/F N *.0K/F N *.0K/F N *.0K/F N FG (isplay Port Presence) FG0 (PI-Epress onfiguration Select) FG (PI-Epress Static Lane Reversal) 0 isabled; No Physical isplay Port attached to Embedded iplay Port Single PEG Normal Operation Enabled; n external isplay port device is connected to the Embedded isplay port ifurcation enabled Lane Numbers Reversed -> 0, -> FG[ :0 ] - PI_Epress onfiguration Select * = x PEG * 0= x PEG Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PROESSER / (GN) ate: Wednesday, January, 00 Sheet of

+.V_RUN INTVRMEN - Integrated SUS.V VRM Enable High - Enable Internal VRs PH_JTG_TO RT_RST# SRT_RST# Z_ITLK Z_SYN Z_RST# PH_JTG_RST# TP must add test point. RT_X RT_X Z_SOUT PH_JTG_TK_UF PH_JTG_TMS PH_JTG_TI SPI_S# ST_LE# ST_ET0# ST_ET# SPI_SI ST_TXN0_ ST_TXP0_ ST_TXN_ ST_TXP_ ST_OMP ST_LE# ST_ET0# ST_ET# INT_RT_LU INT_RT_GRE R0 0 INT_RT_RE R PNEL_KEN R ENV L_T P/0V_ L_TRL_LK R 0K/J_ *00P_N *00P_N L_TRL_T R 0K/J_ IEX PEK-M (H,JTG,ST) Y R 0 0.KHZ 0M/J_ U +RT_ELL () Z_SPKR () Z_SIN0 (0,) PH_MELOK TP TP TP TP R (0) (0) (0) (0) P/0V_ SPI_LK TP SPI_S0# TP TP SPI_SI TP SPI_SO TP SPI_LK SPI_S0# SPI_SI SPI_SO 0 The STLE# signal is open-collector and requires a weak external pull-up (. k to 0 k ) to +V.. R0 R R0 TP TP TP RTX RTX RTRST# SRTRST# SM_INTRUER# INTRUER# 0K/J_ PH_INVRMEN INTVRMEN 0K/J_ 0K/J_ 0K/J_ IbexPeak-M_Rev_0 RT JTG SPI +.V_RUN Ibex-M OF 0 0 H_LK H_SYN P SPKR 0 H_RST# G0 H_SIN0 F0 H_SIN E IH H_SIN F H_SIN H_SO H H_OK_EN# / GPIO (+V) J0 H_OK_RST# / GPIO (+V_S) M K K J J V Y Y V JTG_TK JTG_TMS JTG_TI JTG_TO TRST# SPI_LK SPI_S0# SPI_S# SPI_MOSI SPI_MISO R itpm ENLE/ISLE From UM TPM Function Enable isable FWH0 / L0 FWH / L LP FWH / L FWH / L FWH / LFRME# LRQ0# (+V) LRQ# / GPIO F SERIRQ ST ST0RXN K ST0RXP K ST0TXN K ST0TXP K STRXN H STRXP H STTXN H STTXP H STRXN F STRXP F STTXN F STTXP F STRXN H STRXP H STTXN F STTXP F STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STIOMPO STIOMPI STLE# T Mount N (efault) F F (+V) ST0GP / GPIO Y (+V_S) STGP / GPIO V *K_N +.V_RUN L0 (,) L (,) L (,) L (,) LFRME# (,) SERIRQ () L_LK G: Place TX cap close to connector ST port / are not support in HM. They are only in PM ST_RXN0 () ST_RXP0 () ST_TXN0 () ST_TXP0 () ST_RXN () ST_RXP () ST_TXN () ST_TXP () ST_RXN () ST_RXP () ST_TXN_ 0.0U/V_ ST_TXP_ ST_TXN () 0.0U/V_ ST_TXP () istance between the PH and cap on the "P" signal should be identical distace between the PH and cap on the "N" signal for the same pair. R0 0 ST_LE# () 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_./F_ lose to VG side R0 R UM:RT ohm, UM RT display ripple issue. +.0V_PH P/0V_ 0/F_ P/0V_ 0/F_ P/0V_ 00K/J_ 00K/J_ R R 0/F_.K/J_.K/J_ H O EST (,) PNEL_KEN () ENV () () L_LK () L_T +.V_RUN UM RT,LVS&HMI signals T P I_PWM T () L_0+ () L_+ () L_+ T P INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP PNEL_KEN ENV L_LK L_T L_TRL_LK L_TRL_T R0.K LVS_VG P T P INT_TXLOUTN INT_TXLOUTP () L_LK- () L_LK+ () L_0- () L_- () L_- T P () L_LK- P LVS_LK# () L_LK+ P LVS_LK () L_0- Y LVS_T#0 () L_- T LVS_T# () L_- U INT_TXUOUTN LVS_T# T T P LVS_T# () L_0+ Y LVS_T0 () L_+ T LVS_T () L_+ U0 INT_TXUOUTP LVS_T T T P LVS_T INT_RT_LU () INT_RT_LU INT_RT_GRE RT_LUE () INT_RT_GRE INT_RT_RE RT_GREEN () INT_RT_RE RT_RE V () LK RT LK V () T RT T R0 /J_ () INT_RT_HSYN Y R0 /J_ RT_HSYN () INT_RT_VSYN Y RT_VSYN R0 K/0.% _IREF _IREF RT_IRTN R (IREF), UM:0.%,IS:% Sch check list.0 use % R IbexPeak-M_Rev_0 Leon /0 R.K/J_ R0.K/J_ INT_HMI_TXN0 0 INT_HMI_TXP0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ HMI_SL HMI_S IEX PEK-M (LVS,I) Y U T L_KLTEN T L_V_EN L_KLTTL L LK Y L T L_TRL_LK V L_TRL_T P LV_IG P LV_VG T LV_VREFH T LV_VREFL V LVS_LK# V LVS_LK LVS-- LVS_T#0 LVS_T# Y LVS_T# V LVS_T# LVS_T0 0 LVS_T Y LVS_T V LVS_T LVS-- RT INT_HMI_TXN_ () INT_HMI_TXP_ () INT_HMI_TXN_ () INT_HMI_TXP_ () INT_HMI_TXN0_ () INT_HMI_TXP0_ () INT_HMI_TXN_ () INT_HMI_TXP_ () SVO igital isplay Interface ISPLY PORT ISPLY PORT ISPLY PORT For UM HMI Function Ibex-M SVO_TVLKINN OF 0 J SVO_TVLKINP G SVO_STLLN J SVO_STLLP G INT_HMI_HP SVO_INTN F SVO_INTP H SVO_TRLLK T SVO_TRLT T P_UXN G P_UXP J P_HP U R0 00K/J_ P_0N P_0P P_N J P_P G P_N 0 P_P 0 P_N W P_P P_TRLLK Y P_TRLT P_UXN E P_UXP P_HP V0 P_0N E0 P_0P 0 P_N F P_P H P_N P_P P_N P_P P_TRLLK U0 P_TRLT U P_UXN P_UXP P_HP T P_0N J0 P_0P G0 P_N J P_P G P_N F P_P H P_N E P_P R0 HMI_SL HMI_S R R INT_HMI_HP INT_HMI_TXN0 INT_HMI_TXP0 INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP +V_RUN Q N00K-T-E *0/J N 0 *K/J N *K/J N HMI_SL () HMI_S () *00P_N +.0V_PH HMI_ET () For UIO (,) Z_RST#_UIO () Z_SOUT_UIO () Z_SYN_UIO R0 R R /J_ Z_RST# /J_ Z_SOUT *0P/0V N /J_ Z_SYN *0P/0V N RT +RT_ELL m +.V_SUS Res. of TI near PH R R R R JTG_TI, JTG_TMS, TRST# Internal 0K PU. JTG_TK Internal 0K P R /J_ PH_JTG_TK_UF () Z_ITLK_UIO +.V_RUN R *K/J N Z_SPKR R /J_ Z_ITLK 0P/0V_ No Reboot strap. Low = efault. SPKR High = No Reboot. R 0K/F_ 0 R 0K/F_ R M/J_ FM, UM use % RT_RST# U/.V SRT_RST# U/.V SM_INTRUER# *00_N R *00_N *00_N *00_N R0 R *00_N *00_N *0K_N R *0K_N PH_JTG_TMS PH_JTG_TI PH_JTG_TO PH_JTG_RST# N all Res. when PH is production stage. Res. of TO PH ES stage : N PH ES stage : pop From UM Res. of RST# PH ES stage : pop PH ES stage : N Note : Only pop when PH is production stage & need "JTG boundary Scan". Remember to depop XP side Res. Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PH / (ST,H,LP) ate: Monday, February 0, 00 Sheet of

IEX PEK-M (GN) UI Y VSS[] VSS[] H VSS[0] VSS[0] H VSS[] VSS[] J VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] L VSS[] VSS[] L VSS[] VSS[] L VSS[] VSS[] L G VSS[0] VSS[0] L VSS[] VSS[] L VSS[] VSS[] L0 0 VSS[] VSS[] L VSS[] VSS[] M 0 VSS[] VSS[] M VSS[] VSS[] M0 VSS[] VSS[] N VSS[] VSS[] M VSS[] VSS[] M VSS[0] VSS[0] M 0 VSS[] VSS[] M VSS[] VSS[] M VSS[] VSS[] M VSS[] VSS[] M VSS[] VSS[] N VSS[] VSS[] P VSS[] VSS[] 0 VSS[] VSS[] P VSS[] VSS[] P0 VSS[0] VSS[0] P H VSS[] VSS[] P VSS[] VSS[] P VSS[] VSS[] P VSS[] VSS[] P E VSS[] VSS[] R E VSS[] VSS[] R E0 VSS[] VSS[] T E VSS[] VSS[] T E0 VSS[] VSS[] T E VSS[00] VSS[00] T E VSS[0] VSS[0] T E VSS[0] VSS[0] T E VSS[0] VSS[0] U0 E VSS[0] VSS[0] U E0 VSS[0] VSS[0] U E VSS[0] VSS[0] U E VSS[0] VSS[0] P F VSS[0] VSS[0] V F VSS[0] VSS[0] P F VSS[0] VSS[0] V G VSS[] VSS[] V0 G VSS[] VSS[] V G VSS[] VSS[] V0 G0 VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[0] VSS[0] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V VSS[] VSS[] V 0 VSS[] VSS[] V VSS[] VSS[] W E VSS[] VSS[] W E VSS[] VSS[] Y E0 VSS[0] VSS[0] Y E VSS[] VSS[] Y E0 VSS[] VSS[] Y E VSS[] VSS[] Y E VSS[] VSS[] Y E VSS[] VSS[] Y0 E VSS[] VSS[] Y E VSS[] VSS[] Y E VSS[] VSS[] Y E VSS[] VSS[] Y F VSS[0] VSS[0] Y F VSS[] VSS[] P G0 VSS[] VSS[] Y G VSS[] VSS[] Y G VSS[] VSS[] Y G VSS[] VSS[] P G VSS[] VSS[] T G VSS[] VSS[] G VSS[] VSS[] T G0 VSS[] VSS[] G VSS[0] VSS[0] Y G VSS[] VSS[] T F VSS[] VSS[] M H VSS[] VSS[] T H0 VSS[] VSS[] M H0 VSS[] VSS[] K H VSS[] VSS[] K H VSS[] VSS[] V H VSS[] IbexPeak-M_Rev_0 SM_LK_ME PIE_LK_REQ# PIE_LK_REQ# PIE_LK_REQ0# R PIE_LK_REQ# R PIE_LK_REQ# R PIE_LK_REQ#_R R SM_T_ME PIE_LK_REQ# PEG_LKREQ# +.V_SUS (,,) WLN_SMLK (,,) WLN_SMT R0 R R N00W--F Q R0 Q N00W--F RP.KX 0K 0K 0K 0K 0K 0K 0K 0K +.V_RUN +.V_SUS SMLK () SMT () +.V_RUN +.V_RUN Q N00W--F IH_SMLK Q N00W--F [WWN] [WLN] [LN] MiniWWN IH_SMT () PIE_RXN () PIE_RXP () PIE_TXN () PIE_TXP () PIE_RXN_LN () PIE_RXP_LN () PIE_TXN_LN () PIE_TXP_LN PIELKRQ0#/GPIO Internal 0K PU () LK_PIE_WLNN () LK_PIE_WLNP MiniWLN () PIE_LK_REQ# () LK_PIE_LNN () LK_PIE_LNP LN () PIE_LK_REQ#_R 0 0.U/ 0V 0.U/ 0V PIE_LK_REQ0# P M M PIE_LK_REQ# IEX PEK-M (PI-E,SMUS,LK) 0 U G0 PERN J0 PERP F PETN H PETP PIE_RXN W0 PIE_RXP PERN 0 PIE_TXN_ PERP 0 PIE_TXP_ PETN 0 PETP U0 PERN T0 PERP U PETN V PETP PERN PERP PETN E PETP F PERN H PERP G PETN J PETP PIE_RXN_LN PIE_RXP_LN PERN W 0.U/ 0V PIE_TXN_LN_ PERP 0.U/ 0V PIE_TXP_LN_ PETN PETP T PERN U PERP U PETN V PETP G PERN J PERP G PETN J PETP K LKOUT_PIE0N K LKOUT_PIE0P Ibex-M OF 0 PI-E* PIELKRQ0# / GPIO (+V_S) LKOUT_PIEN LKOUT_PIEP U PIELKRQ# / GPIO (+V) M LKOUT_PIEN M LKOUT_PIEP N PIELKRQ# / GPIO0 (+V) IbexPeak-M_Rev_0 SMus (+V_S) SMLERT# / GPIO SMLK SMT (+V_S) SML0LERT# / GPIO0 SML0LK SML0T (+V_S) SMLLERT# / GPIO (+V_S) SMLLK / GPIO (+V_S) SMLT / GPIO ontroller Link PEG From LK UFFER L_LK L_T L_RST# SMLERT# 0K/J_ H IH_SMLK.K/J_ IH_SMT.K/J_ J SML0LERT# 0K/J_ SM_LK_ME0.K/J_ G SM_T_ME0.K/J_ M SMLLERT# 0K/J_ E0 SM_LK_ME.K/J_ G SM_T_ME.K/J_ PEG_LKREQ# XTL_IN ate: Monday, February 0, 00 Sheet of XTL_OUT +.V_SUS LK_PIE_GPLLN () LK_PIE_GPLLP () LK_REFSSLKN () LK_REFSSLKP () LK_UF_PIE_GPLLN () LK_UF_PIE_GPLLP () LK_UF_LKN () LK_UF_LKP () LK_UF_REFLKN () LK_UF_REFLKP () LK_UF_REFSSLKN () LK_UF_REFSSLKP () H LKOUT_PIEN REFLKIN P LK_PH_M () H LKOUT_PIEP *.P/0V N PIE_LK_REQ# LK_PI_F PIELKRQ# / GPIO (+V_S) LKIN_PILOOPK J LK_PI_F () T M Intel recommendation LKOUT_PIEN M XTL_IN LKOUT_PIEP XTL_IN H R *0_N XTL_OUT PIE_LK_REQ# XTL_OUT H R00 M PIELKRQ# / GPIO (+V_S) XLK_ROMP XLK_ROMP F +.0V_PH R0 0./F_ J0 LKOUT_PIEN J LK_FLEX0 T LKOUT_PIEP (+V) LKOUTFLEX0 / GPIO T LK_FLEX PIE_LK_REQ# H (+V_S) (+V) LKOUTFLEX / GPIO P T0 LK_FLEX T PIELKRQ# / GPIO (+V) LKOUTFLEX / GPIO T LK_FLEX (+V) LKOUTFLEX / GPIO N0 LK_M_R () R /J_ K LKOUT_PEG N K LKOUT_PEG P lock Flex PIE_LK_REQ#_R P PEG LKRQ# / GPIO 0P/0V_ (+V_S) T T T (+V_S) PEG LKRQ# / GPIO H LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N N LKOUT_MI_P N LKOUT_P_N / LKOUT_LK_N T LKOUT_P_P / LKOUT_LK_P T LKIN_MI_N W LKIN_MI_P LKIN_LK_N P LKIN_LK_P P LKIN_OT_N F LKIN_OT_P E LKIN_ST_N / KSS_N H LKIN_ST_P / KSS_P H P 0 NPO R0 M/F_ Y MHz For UM R R0 R R R R R R R Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PH / (PIE, SMUS, K) 0 P 0 NPO

+.V_RUN REQ# PIRQE# PIRQF# T_ET# PI_IRY# PI_STOP# PI_PIRQ# PI_PIRQ# +.V_SUS () US_O# US_O# US_O0# US_O# () LK_M_LP () LK_M_K () LK_PI_F () US_MR_ET# T_ET# LK_M_K RP.KX RP.KX +.V_RUN RP PI_PLOK# PI_TRY# INTH# PI_EVSEL#.KX R R R R 0 00P T_ET# PI_PIRQ# PI_SERR# REQ# PI_FRME# US_O# US_O# US_O# US_O# PI_PERR# US_MR_ET# REQ0# PI_PIRQ# LK_M_LP +.V_RUN +.V_SUS +.V_RUN +.V_RUN PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# REQ0# REQ# REQ# US_MR_ET# GNT0# GNT# GNT# PIRQE# PIRQF# INTH# PI_SERR# PI_PERR# PI_IRY# PI_EVSEL# PI_FRME# PI_PLOK# PI_STOP# PI_TRY# PLT_RST-R# LK_M_LP_R LKOUT_PI[0..]: ohm series resistor is recommend (single & double load) on PG v. R R R Reserve capacitor pads for improving WWN. 0P/0V_ 0 0 0.K/J_.K/J_.K/J_.K/J_ TP TP /J_ /J_ /J_ 0P/0V_ LK_M_K_R LK_PI_F_R IEX PEK-M (PI,US,NVRM) oot IOS Strap PI_GNT0# GNT# 0 0 UE H0 0 N J 0 E H E0 0 0 M M F M0 M J K F0 0 K M J K L F J0 G F M 0 H J0 /E0# G /E# H /E# G /E# G PIRQ# H PIRQ# PIRQ# PIRQ# 0 0 Ibex-M OF 0 PI F REQ0# REQ# / GPIO0 (+V) REQ# / GPIO (+V) M REQ# / GPIO (+V) F GNT0# K GNT# / GPIO (+V) F GNT# / GPIO (+V) H GNT# / GPIO (+V) PIRQE# / GPIO K (+V) PIRQF# / GPIO (+V) PIRQG# / GPIO (+V) PIRQH# / GPIO (+V) K PIRST# E SERR# E0 PERR# IRY# H PR F EVSEL# FRME# M PLOK# STOP# TRY# PME# PLTRST# N LKOUT_PI0 P LKOUT_PI P LKOUT_PI P LKOUT_PI P LKOUT_PI IbexPeak-M_Rev_0 NVRM US (+V_S) O0# / GPIO (+V_S) O# / GPIO0 (+V_S) O# / GPIO (+V_S) O# / GPIO (+V_S) O# / GPIO (+V_S) O# / GPIO (+V_S) O# / GPIO0 (+V_S) O# / GPIO GNT0# GNT# GNT# oot IOS Location LP Reserved (NN) PI SPI NV_E#0 Y NV_E# NV_E# P NV_E# NV_QS0 V NV_QS G NV_Q0 / NV_IO0 P NV_Q / NV_IO P NV_Q / NV_IO T NV_Q / NV_IO T NV_Q / NV_IO NV_Q / NV_IO V NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO E NV_Q / NV_IO NV_Q0 / NV_IO0 NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO J NV_Q / NV_IO J NV_Q / NV_IO G NV_LE NV_LE Y NV_ROMP NV_R# U V NV_WR#0_RE# Y NV_WR#_RE# Y NV_WE#_K0 V NV_WE#_K F USP0N H USP0P J USPN USPP USPN N0 USPP P0 USPN J0 USPP L0 USPN F0 USPP G0 USPN 0 USPP 0 USPN M USPP N USPN USPP USPN H USPP J USPN E USPP F USP0N USP0P USPN G USPP H USPN L USPP M USPN USPP NV_LE NV_LE US_IS USRIS# R USRIS R R R N US_O0# J F US_O# US_O# L US_O# E US_O# G US_O# F US_O# T US_O# *K/J N *K/J N *K/J N PH_PWROK () () () () () () () () () () () () () () () () +.0V_PH 0 () XP_RESET# T SYS_RESET# SLP_S# P SIO_SLP_S# () M TP0 SYS_PWROK SLP_S# H TP PH_PWROK PWROK () EPWROK R K SJ_00 MEPWROK SLP_M# K TP TP RSV_IH_LN_RST# TP N 0 LN_RST# () PM_RM_PWRG RMPWROK (+V_S) SUS_PWR_N_K / GPIO0 M SUS_PWR_K () () RSMRST# _PRESENT () TP RSMRST# (+V_S) PRESENT / GPIO P (+V) LKRUN# / GPIO Y LKRUN# () () PM_PWRTN#_R P PWRTN# (+V_S) SUS_STT# / GPIO P USP0- () (+V_S) SUSLK / GPIO F TP SIO_SLP_S# USP0+ () US #0 (est) (+V_S) SIO_SLP_S# () PM_RI# SLP_S# / GPIO E PM_TLOW# USP- () F RI# (+V_S) TLOW# / GPIO USP+ () Right US # () PIE_WKE# J WKE# USP- () () PM_SYN J0 PMSYNH USP+ () Left US # (+V_S) SLP_LN# / GPIO F USP- () USP+ () Left US # IbexPeak-M_Rev_0 USP- () USP+ () WLN TLOW#/GPIO Internal 0K PU USP- () USP+ () WWN +.V_RUN USP- () USP+ () T USP- () USP+ () Webcam USP- () USP+ () ard Reader US_O0# () US_O# () swap override Strap/Top-lock Swap Override jumper GNT#./F_ 00P For Port0, For Port, Low = swap override/top-lock Swap Override enabled High = efault LKRUN# XP_RESET# RSMRST# RSV_IH_LN_RST# PH_PWROK PM_RI# PM_TLOW# PIE_WKE# R R R 0K/J_ 0K/J_ K/J_ Sch check list R.0 :WKE# use 0K heck PLT_RST-R# MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP R H MI_OMP F./F_ SUS_PWR_K _PRESENT U *MVHG0FTG_N R 00K_ +.V_SUS R IEX PEK-M (MI,FI,GPIO) R R R R U MI0RXN J MIRXN W0 MIRXN J0 MIRXN MI0RXP G MIRXP 0 MIRXP G0 MIRXP E MI0TXN F MITXN 0 MITXN E MITXN MI0TXP H MITXP 0 MITXP MITXP R R R MI_ZOMP MI_IROMP.K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ *0.U/0V_N SJ_00 MI +.V_SUS PLTRST# (,,) Ibex-M OF 0 FI System Power Management R *00K N MI Termination Voltage NV_LE NV_LE NV_LE anbury Technology Enabled NV_LE FI_RXN0 FI_RXN H FI_RXN FI_RXN J FI_RXN FI_RXN E FI_RXN FI_RXN FI_RXP0 FI_RXP F FI_RXP FI_RXP G FI_RXP W FI_RXP FI_RXP FI_RXP FI_INT J FI_FSYN0 F FI_FSYN H FI_LSYN0 J FI_LSYN G Set to Vcc when LOW Set to Vcc/ when HIGH R R00 High = Enable Low = isable *K_N *K_N FI_TXN0 () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXP0 () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_INT () FI_FSYN0 () FI_FSYN () FI_LSYN0 () FI_LSYN () +.V_RUN Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PH / (PI,ONFI,US,MI) ate: Monday, February 0, 00 Sheet of

VG Strap Madison Park +.V_SUS R *0K N heck... VG_TYPE IEX PEK-M (GPIO,VSS_NTF,RSV) UF PH_GPIO0 Ibex-M Y MUSY# / GPIO0 (+V) OF 0 LKOUT_PIEN H LKOUT_PIEP H () SIO_EXT_SMI# TH / GPIO (+V) () SIO_EXT_SI# TH / GPIO (+V) LKOUT_PIEN () SIO_EXT_WKE# GPIO J TH / GPIO(+V) LKOUT_PIEP F TP PH_GPIO F0 GPIO (+V_S) MIS LN_PHY_PWR_TRL K LN_PHY_PWR_TRL / GPIO (+V_S) 0GTE U () TEST_WOOFER_EN TEST_WOOFER_EN T GPIO (+V_S) STGP STGP / GPIO (+V) LKOUT_LK0_N/LKOUT_PIEN M () PIE_MR_ET# PIE_MR_ET#_R R0 SJ_00 F TH0 / GPIO (+V) LKOUT_LK0_P/LKOUT_PIEP M PIE_MR_ET#, If PIE_MR_ET# Y SLOK / GPIO (+V) PEI G0 WWN have issue check this R *0K N GPIO GPIO GPIO reserve for (+V_S) RIN# T internal VR. TP_PH_GPIO V PU GPIO (+V_S) PROPWRG E0 STGP PH_THRMTRIP#_R STGP / GPIO (+V) THRMTRIP# 0 R STGP STGP / GPIO (+V) TP +.0V_VTT R T_RIO_IS# TP W () T_RIO_IS# P STOUT0 / GPIO (+V) TP TP Y GPIO TP Y F PIELKRQ# / GPIO (+V_S) TP V WWN_RIO_IS# TP V () WWN_RIO_IS# STOUT / GPIO (+V) TP F RIT_TEMP_REP# TP M () RIT_TEMP_REP# STGP / GPIO (+V) TP0 N RSV TP J TP K GPIO register not cleared TP K by Fh reset event. TP M H0 GPIO GPIO H (+V_S) TP N VG_TYPE PIELKRQ# / GPIO F (+V_S) TP M0 US_MR_ET# GPIO (+V_S) TP N0 () US_MR_ET# M GPIO STP_PI# / GPIO (+V) TP H V WLN_RIO_IS# STLKREQ# / GPIO (+V) TP () WLN_RIO_IS# V SLO / GPIO (+V) N_ N_ N_ N_ N_ T INIT_V# P TP 0 R *0K N VSS_NTF_ VSS_NTF_ VSS_NTF_ 0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 E VSS_NTF_ E VSS_NTF_ F VSS_NTF_ F VSS_NTF_ H VSS_NTF_ IbexPeak-M_Rev_0 NTF VSS_NTF_ H VSS_NTF_ H VSS_NTF_ H VSS_NTF_ J VSS_NTF_0 J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J0 VSS_NTF_ J VSS_NTF_ J VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 E VSS_NTF_ E /J_ /J_ RIN# GTE0 R0 R0 T_RIO_IS# R00 STGP R0 STGP R0 STGP R PIE_MR_ET#_R R PIE_MR_ET# R SIO_EXT_SMI# SIO_EXT_SI# SIO_EXT_WKE# R R R0 WLN_RIO_IS# R0 RIT_TEMP_REP# R US_MR_ET# R0 TEST_WOOFER_EN R PH_GPIO R TP_PH_GPIO GPIO GPIO R R R LN_PHY_PWR_TRL R GTE0 () LK_PU_LKN () LK_PU_LKP () H_PEI () RIN# () H_PWRGOO () *00P_N H_THERM () 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ *0K N 0K_ 0K_ 0K_ 0K_ +.V_RUN +.V_SUS IEX PEK-M (GN) UH VSS[0] VSS[0] K0 VSS[] VSS[] K 0 VSS[] VSS[] K VSS[] VSS[] K M VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] K 0 VSS[] VSS[] K VSS[] VSS[] K VSS[0] VSS[0] K VSS[] VSS[] L VSS[] VSS[] L VSS[] VSS[] M 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] M0 VSS[] VSS[] M VSS[] VSS[] M VSS[] VSS[] M VSS[0] VSS[00] M VSS[] VSS[0] VSS[] VSS[0] M0 VSS[] VSS[0] M VSS[] VSS[0] M VSS[] VSS[0] M VSS[] VSS[0] M VSS[] VSS[0] M 0 VSS[] VSS[0] M VSS[] VSS[0] M VSS[0] VSS[0] U0 VSS[] VSS[] M U VSS[] VSS[] V VSS[] VSS[] M VSS[] VSS[] M VSS[] VSS[] 0 VSS[] VSS[] 0 E VSS[] VSS[] N E VSS[] VSS[] N0 F VSS[] VSS[] N Y VSS[0] VSS[0] P H VSS[] VSS[] P U VSS[] VSS[] P F VSS[] VSS[] P P VSS[] VSS[] P N VSS[] VSS[] P F VSS[] VSS[] R F VSS[] VSS[] R F VSS[] VSS[] T F VSS[] VSS[] F VSS[0] VSS[0] H G VSS[] VSS[] T G VSS[] VSS[] T H VSS[] VSS[] T H VSS[] VSS[] T H VSS[] VSS[] T H VSS[] VSS[] V H VSS[] VSS[] V V VSS[] VSS[] V0 H VSS[] VSS[] V H VSS[0] VSS[0] V0 H VSS[] VSS[] V J VSS[] VSS[] V J VSS[] VSS[] V J0 VSS[] VSS[] V J VSS[] VSS[] V J VSS[] VSS[] V J VSS[] VSS[] V J VSS[] VSS[] W J VSS[] VSS[] W J VSS[0] VSS[0] W T VSS[] VSS[] F J VSS[] VSS[] W K VSS[] VSS[] W M VSS[] VSS[] W0 N VSS[] VSS[] W K VSS[] VSS[] Y K VSS[] VSS[] Y K VSS[] VSS[] Y K VSS[] IbexPeak-M_Rev_0 (,) PH_MELOK 0 Flash escriptor Security Override GPIO Low = Enabled High = isabled R *K/J N R 0K_ GPIO GPIO[,,,], PIELKRQ#/GPIO, GPIO Internal 0K PU PH_GPIO0 WWN_RIO_IS# R R 0K_ 0K_ +.V_RUN MUSY#:(Intel feedback) Follow R checklist, K is for intel IOS validation purpose. MUSY#: If not used, require a weak pull-up (.- K to 0 k ) to Vcc_. R(V.0)P: it has K PU and 00 ohm on this net for validation purpose. (Internal 0K/F pull high to +.V_RUN) Note : GPIO is a signal used for Flash escriptor Security Override/ME ebug Mode.This signal should be only asserted lowthrough an external pull-down in manufacturing or debug environments ONLY. WWN_RIO_IS# -X High = Strong (efault) Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PH / (GPIO & Strap) ate: Monday, February 0, 00 Sheet 0 of

+.0V_PH +.0V_PH L +.0V_PH +.V_RUN +.0V_PH. U/.V 0U/0V_.0 0. 0.0 +.0V_VFIPLL *0U/.V N.0 POWER UG VORE[] VORE[] Ibex-M VORE[] OF 0 VORE[] VORE[] F VORE[] F VORE[] F0 VORE[] F VORE[] H VORE[0] H VORE[] H0 VORE[] H VORE[] J0 VORE[] J VORE[] V ORE *uh_n +.0V_LN_VPLL_EXP J *0U/.V N VPLLEXP N0.0 VIO[] +.0V_PH N 0U/0V_ VIO[] N 0 U/.V VIO[] N U/.V VIO[] N U/.V VIO[] N U/.V VIO[0] J VIO[] J VIO[] T VIO[] T VIO[] U VIO[] U VIO[] V VIO[] V VIO[] W VIO[] W VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] E VIO[] E VIO[0] G VIO[] G VIO[] H VIO[] N0 VIO[] N VIO[] +.V_RUN L *uh_n +.0V_PH 0.U/V K N T J M VIO[] V_[] VVRM[] VFIPLL VIO[] PI E* FI IbexPeak-M_Rev_0 RT LVS HVMOS MI NN / SPI +.0V_PH V000MN R MX:. ohm VPNN[] M VPNN[] K VPNN[] K0 VPNN[] K VPNN[] K VPNN[] K VPNN[] M VPNN[] M VPNN[] M 0. 0.0 0.0 0. 0.0 +.V_RUN +VTX_LVS L 0.0U/V_ 0.0U/V_ U/.V_ +.V_RUN +.V_RUN +.0V_VTT +.V_RUN +.V_RUN hange R from 0uH (R = 0.? which may cause high IR drop) to 0 uh (R = 0.?) +.V_VPLL +.V_VPLL ap quantities follow UM UM:u, IS:0u, solve UM RT display ripple issue. L +V H0KF-T V[] E0 0 U/.V_ 0 0.U/V V[] E 0.0U/V_ VSS_[] VSS_[] VLVS H VSS_LVS H VTX_LVS[] P VTX_LVS[] P VTX_LVS[] T VTX_LVS[] T V_[] V_[] V_[] VVRM[] VMI[] VMI[] F F T T U VME_[] M VME_[] M VME_[] P VME_[] P L L U/.V 0.U/V 0uH 0uH 0.U/V 0.U/V +.0V_PH Ensure F and F, H are not shorted to the H and J pins The above recommendations will create an inductance affect on the F and F, H pins and help to filter out the noise 0 U/.V_ +.V_SUS +.0V_VTT +VSST +V.LN_INT_VSUSY 0 0.U/V PSUS PI/GPIO/LP P VSUS_[] +.V_SUS 0. U VSUS_[0] U0 0 0.U/V VSUS_[] U VSUS_[] +.V_RUN +RT_ELL 0.0 0.0 +.V_VPLL 0.0 +.V_VPLL.0 0.U/V 0. 0 >m m.u/.v 0.U/V 0.U/V m 0..0 0.0. >m +.V_RUN +.V_RUN +.0V_PH +.0V_PH +.V_RUN UJ POWER VLK = 00m max Ibex-M +.0V_PH L *0uH_N +.V_LN_V_LK P.0 +.0V_PH *U/.V_N VLK[] 0 OF 0VIO[] V VIO[] V *0U/.V N P VLK[] VIO[] Y U/.V Y0 PSUSYP VIO[] Y US PSUSYP 0. +.V_SUS 00 0.U/V VSUS_[] V VSUS_[] U 0 0.U/ 0V +.0V_PH R0 *0_N +VLN VSUS_[] U F 0.U/ 0V VLN[] VSUS_[] U *U/.V_N VSUS_[] P F 0.uH VLN[] VSUS_[] P +.V_RUN VSUS_[] N +.0V_PH R0 SJ_00 VSUS_[] N VME[] VSUS_[] M VSUS_[0] M 0 U/._ VME[] VSUS_[] L U/._ VSUS_[] L VME[] VSUS_[] J 0 U/.V VSUS_[] J F VME[] VSUS_[] H VSUS_[] H F VME[] VSUS_[] G VSUS_[] G F VME[] VSUS_[] F VSUS_[0] F V VME[] VSUS_[] E VSUS_[] E VREF must be powered up V VME[] VSUS_[] before Vcc_, or after Vcc_ VSUS_[] V within 0. V. lso, VREF must VME[] VSUS_[] VSUS_[] power down after Vcc_, or Y VME[0] VSUS_[] before Vcc_ within 0. V Y VME[] VSUS_[] U Y.0 VME[] VIO[] V +.0V_PH +VRTEXT V +VREF_SUS R 00_ PRT VREF_SUS F +V_SUS 0.U/V >m +.V_SUS +.V_RUN U 0 SM0K--F VVRM[] U/.V U/.V 0 R U/.V U/.V U/.V 0 0.U/V 0.U/V 0.U/V U/.V SJ_00 U/.V VPLL[] VPLL[] VPLL[] VPLL[] H VIO[] J VIO[] H VIO[] F VIO[] H VIO[] F VIO[] V PSST V V_[] V V_[] Y V_[] T V_PU_IO[] U V_PU_IO[] VRT lock and Miscellaneous PU RT L0 VSUSH H IbexPeak-M_Rev_0 PI/GPIO/LP ST +VREF VREF K V_[] J V_[] L V_[0] M V_[] N V_[] P V_[] U V_[] VVRM[] T0 VIO[] H VIO[0] H VIO[] 0 VIO[] F VIO[] VIO[] F0 VIO[] F VIO[] H0 VIO[] VIO[] 0 VIO[] VIO[0] 0 0.U/V 0.U/V +.0V_VSTPLL VSTPLL[] K L VSTPLL[] K *U/.V_N *0U/.V N VME[] VME[] Y VME[] Y VME[] R 00_ U/.V SM0K--F U/.V *0uH_N +V_RUN +.V_RUN +.0V_PH U/.V_ U/.V Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PH / (POWER) ate: Monday, February 0, 00 Sheet of

() M [0..] SO-IMM SP ddress is 0X0 SO-IMM TS ddress is 0X0 () M S#0 () M S# () M S# () M S#0 () M S# () M LKP0 () M LKN0 () M LKP () M LKN () M KE0 () M KE () M S# () M RS# () M WE# R R (,,) WLN_SMLK (,,) WLN_SMT () M OT0 () M OT () M M[0..] () M QSP[0..] () M QSN[0..] 0K/F_ 0K/F_ M 0 M M M M M M M M M M 0 M M M M M IMM0_S0 IMM0_S M M0 M M M M M M M M M M M M M M M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 JIM 0 0/P /# 0 S0# S# K0 K0# K K# KE0 KE S# RS# WE# S0 S SL S OT0 OT M0 M M M M M M M QS0 QS QS QS QS QS QS QS QS#0 QS# QS# QS# QS# QS# QS# QS# P00 R SRM SO-IMM (0P) Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q 0 0 0 0 0 0 0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q[0..] () (,) R_RMRST# +.V_SUS +SMR_VREF_Q0 +SMR_VREF_IMM0 R_RMRST# +.V_SUS +VTT_R_REF +.V_RUN () PM_EXTTS#0 R +SMR_VREF_IMM0 *0_N +.V_SUS for S power reduction, P reserved R K R 0 *00P_N 0 PM_EXTTS#0 *K/F N JIM V V V V V V V V V 00 V0 0 V 0 V V V V V V V VSP N N NTEST EVENT# 0 RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS0 VSS VSS VSS VSS VSS R-IMM P00 R SRM SO-IMM (0P) VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VTT VTT 0 GN 0 GN 0 0 0 0 0 +0.V_R_VTT Place these aps near So-imm0. +.V_SUS Some Projects replace 0UF 00 by.uf 00 It can cost down 0% 0 0 0 0 + 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0.U/ 0V 0.U/ 0V 0.U/ 0V 0.U/ 0V 0.U/ 0V *0U/V N +0.V_R_VTT 00 0 U/.V U/.V U/.V U/.V 0U/.V_ 0U/.V_ 0U/.V_ R-IMM +.V_SUS R K R K +VTT_R_REF R *0_N 0.U/V_ Wait Victor check M VREF M VREF +SMR_VREF_Q0 +SMR_VREF_Q0 +M_VREF_Q_IMM0 Quantities and M/M follow UM Locations follow P +SMR_VREF_IMM0 R0 SJ_00 R *0_N +.V_RUN 0.U/.V 0 0.U/ 0V 0.U/ 0V.U/.V.U/.V 0 0.U/ 0V R K 0 0.U/V_ Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev R IMM-0 ate: Monday, February 0, 00 Sheet of

() M [0..] () M S#0 () M S# () M S# () M S#0 () M S# () M LKP0 () M LKN0 () M LKP () M LKN () M KE0 () M KE () M S# () M RS# () M WE# R +.V_RUN R0 (,,) WLN_SMLK (,,) WLN_SMT () M OT0 () M OT () M M[0..] SO-IMM SP ddress is 0X SO-IMM TS ddress is 0X () M QSP[0..] () M QSN[0..] Place these aps near So-imm. Some Projects replace 0UF 00 by.uf 00 It can cost down 0% M 0 M M M M M M M M M M 0 M M M M M M M0 M M M M M M M M M M M M M M JIM 0 0 0 0/P /# 0 0 0 0 S0# S# 0 K0 0 K0# 0 K 0 K# KE0 KE S# 0 RS# 0K/F_ IMM_S0 WE# 0K/F_ IMM_S S0 0 S 0 SL 00 S OT0 0 OT M0 M M M M M 0 M M M QSP0 M QSP QS0 M QSP QS M QSP QS M QSP QS M QSP QS M QSP QS M QSP QS M QSN0 QS 0 M QSN QS#0 M QSN QS# M QSN QS# M QSN QS# M QSN QS# M QSN QS# M QSN QS# QS# R-IMM0 P00 R SRM SO-IMM (0P) Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q 0 0 0 0 0 0 0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q[0..] () +.V_SUS +VTT_R_REF R K R K () PM_EXTTS# (,) R_RMRST# +SMR_VREF_Q +SMR_VREF_IMM +.V_RUN R +SMR_VREF_IMM *0_N 0.U/V_ +.V_SUS JIM V V V V V V V V V 00 V0 0 V 0 V V V V V V V VSP N N NTEST EVENT# 0 RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS0 VSS VSS VSS VSS VSS R-IMM0 P00 R SRM SO-IMM (0P) VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VTT VTT 0 GN 0 GN 0 0 0 0 0 +0.V_R_VTT +.V_SUS 0U/.V_ 0U/.V_ 0U/.V_ 0 0U/.V_ 0U/.V_ 0 0U/.V_ 0.U/ 0V 0.U/ 0V 0 0.U/ 0V 0.U/ 0V 0.U/ 0V + 0U/V_ +.V_RUN.U/.V 0.U/ 0V +0.V_R_VTT U/.V U/.V U/.V U/.V 0U/.V_ 0U/.V_ 0U/.V_ +SMR_VREF_IMM 0 0.U/ 0V 0.U/ 0V.U/.V 0.U/.V +.V_SUS R K R K +VTT_R_REF R *0_N R 0.U/V_ M VREF M VREF +SMR_VREF_Q +SMR_VREF_Q +M_VREF_Q_IMM R *0_N SJ_00 Quantities and M/M follow UM Locations follow P Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev R IMM- ate: Monday, February 0, 00 Sheet of

Size ocument Number Rev lank Quanta omputer Inc. PROJET : UM UM ate: Wednesday, January, 00 Sheet of

Size ocument Number Rev lank Quanta omputer Inc. PROJET : UM UM ate: Wednesday, January, 00 Sheet 0 of

/ el H&H H H-cdn H-cdn H H-N H-N H H-N H-N H H-oxdxn H-oxdxn H H-cdn H-cdn H0 H-oxdxn H-oxdxn H H-TP H-TP H H-TP H-TP H H-P H-P Nut H H-P H-P H H-P H-P H H-TP H-TP H H-N H-N H H-tcbcdp H-tcbcdp H H-TP H-TP / H H-oxdxn H-oxdxn H H-P H-P H0 H-P H-P H H-TP H-TP H H-O0X0XN H-O0X0XN H H-tcbcdp H-tcbcdp H H-TP H-TP H H-TP H-TP H H-TP H-TP H H-c0d0n H-c0d0n H H-UM- H-UM- H H-TP H-TP Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev SREW P ate: Wednesday, January, 00 Sheet of

() UM Support the new imbeded diagnostics. ENV () LV_TST_EN () I_PWM T T/R EN_LV +.V_SUS LT_PWM +V_LW +.V_RUN Q FN R 0K/J_ LV_ON Q TEU--F R *00K_N +LV 0mil Q N00W--F 0 0U/0V_ +LV +.V_RUN L_- L_+ L_0- L_0+ L_KLIGHT LT_PWM L_LK- L_LK+ L_- L_+ L_LK- L_LK+ L_- L_+ L_- L_+ L_0- L_0+ L_LK L_T USP_- USP_+ L_- () L_+ () L_- () L_+ () L_0- () L_0+ () L_- () L_+ () L_- () L_+ () L_0- () L_0+ () L_LK () L_T () L_TST () +LV +.V_RUN *0_N +GFX_PWR_SR MI_LK () MI_T () () PWM_VJ T T/R () L_K L_KLIGHT (,) PNEL_KEN R00 0K R R 0K/J_ 00 *0.0U/V N T T/R +PWR_SR 0mil R *00K_N *0.U_N 0 Shunt capacitors on LVS for improving WWN. L_LK- L_LK- L_LK+ L_0- L_- L_- L_0- L_- L_- *.P_N 0 L_0+ 0 *.P_N 0 L_+ *.P_N 0 L_+ *.P_N 0 L_0+ *.P_N 0 L_+ *.P_N 0 L_+ 0 *.P_N L_LK- () L_LK+ () L_LK- () USP_- USP_+ USP- () USP+ () (0,,,,) RUN_ON R K Q N00W--F 0 0.0U/V_ R 0 0.U/V_ J 0 0 0 0 0 0 0 0 0-00-00 R *0_N *0.0U/0V N 0 0 0.U/V_ heck R size R 0 0 +GFX_PWR_SR 0mil Q *FP_N *0.U_N *0.U_N 0 0 R0 *00K_N R *0/J N R R SJ_00 SJ_00 Q0 *N00W--F_N L_LK+ R *0/J N 0 *.P_N L_LK+ () RUN_ON *00P_N lose to PQ Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev L ONN / HMI ONN ate: Monday, February 0, 00 Sheet of

UM This page to RT board E Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev RT ONN ate: Wednesday, January, 00 Sheet of E

E To RT OR Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev ONN/Left US ate: Wednesday, January, 00 Sheet of E

R_V S_ S_ S_ S_M S_ *0P/0V_N 0 0 R close to U Pin MS_LK MS_ R SJ_00 MS_INS# MS_ MS_0 MS_ MS_S R close to U Pin S_LK S_ R SJ_00 S_ S_0 S_ *0P_N *P_N 0.U/V 0 NPO 0.U/V R_V_R ON S-() S-() MM-0() S-(S_M) MM-() S-(VSS) S-(V) MS-0(VSS) MS-(V) 0 MS-(SLK) MS-() MS-(INS) MS-() MS-(0) MS-() MS-(S) MS-(VSS) S-(LK) MM-() 0 S-(GN) MM-() S-(0) S-() LPS IN-SF000-P-V 0~0mil S(SW.OM) S(SW.) X-(SW) X-0(GN) X-(R/-) X-(RE) X-(E) X-(LE) X-(LE) X-(WE) X-(-WP) X-(GN) X-0(0) X-() X-() X-() X-() X-() X-() X-() X-(V) S(SW.WP) symbol from RM 0 0 R 0~0mil R, R for pin, check R R SJ_00 S_# SJ_00 X_# SJ_00 X_RY X_RE# X_E# X_LE X_LE X_WE# X_WP X_0 X_ X_ X_ X_ X_ X_ X_ S_WP lose to ON Pin 0.U/V +.V_RUN 0.U/.V. XR 0 () LK_M_R *00P_N 0 R.K/F_ RREF USP_- USP_+ R_V 0.U/V_ R_V VREG U/.V I ottom Ground RTS-QFN U RREF M P V_IN R_V V GN RTS X_ SP SP SP SP LK_IN X_ SP SP SP 0 SP X_# SP SP SP SP SP X_# SP SP SP 0 SP SP SP0 GPIO0 SP SP SP SP SP0 SP SP SP SP SP X_RY S_WP MS_LK SP X_RE# MS_INS# SP X_E# S_ SP X_LE S_0 MS_ SP X_LE S_ MS_ SP X_WE# S_# SP X_WP S_ MS_ SP X_0 S_LK MS_ SP X_ S_ MS_0 SP0 X_ S_M SP X_ S_ MS_ SP X_ S_ MS_ SP X_ S_ MS_ SP X_ MS_S Share Pin LPSN00HLL () () USP_+ USP_- USP+ USP- L Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev ard Reader(RST) ate: Monday, February 0, 00 Sheet of

+V_RUN *0U/0V/00_N +V_RUN +V_V +V_RUN R0 L +PV U_SPK_L+ U_SPK_R+ +PV HP_OUT_R HP_OUT_L MI_VREFO_R MI_VREFO () EP EP L +.V_RUN V & V-IO TYP=0m +.V_RUN *0U/ 0V N 0 0 V, V TYP=m SJ_00 *0U/.V N LMPG00SN R R *0U/.V N 0. 0U/.V_ 0. SJ_00 *0U/.V N SJ_00 *0U/.V N 0.U/ 0V 0 *0.U/ 0V_N 0 U R *0_N SHN VO GN VIN SET *G-_N *0.U/0V_N 0 0 0 ZM_M_FOR_IT_0-.SN R 0. SJ_00 0.U/ 0V 0 +V_V F:.V +V +V_IO Z_OE_SIN0 U_P_EEP MI_VREFO_L MI_R MI_L MI_R MI_L 0 EP *0.U/ 0V_N SPIFO/EP LINE-L R0 0.K/F SPIFO Sense R 0K/F_ 0. 0. R *K_N 0 U VSS V PV SPK-L+ PVSS PVSS U_SPK_R+ R U_SPK_R- R U_SPK_L+ R U_SPK_L- R U_SPK_R- U_SPK_L- SPK-L- SPK-R- 0.U/ 0V 0 () MI_T 0 0.U/ 0V 0 R *K_N () MI_LK SPK-R+ PV P.U/.V P V N GPIO0/MI-T.U/.V PVEE GPIO/MI-LK HP-OUT-R P# UM, symbol from P HP-OUT-L ST-OUT R0 *0_N PVREF IT-LK MI-VREFO-R 0 VSS MI-VREFO ST-IN MI-VREFO-L V-IO P/0V_ R *0_N VREF SYN 0 0.U/ 0V VSS RESET# V MONO-OUT PEEP 0U/.V_ R 0 *0U/.V_00_N LINE-R LINE-L MI-R MI-L JREF Sense- MI-R MI-L 0 LINE-R V, V TYP=m +V_V 0 0.U/ 0V R K/F 00 U_P_EEP EEP 0U/.V_ 0.U/ 0V 0 0 0 0 0 0.U/ 0V R K/F. 0 0 MONO-OUT R *NOTE: L_V type add the LO circuit in I PIN NME R0 R R OE I V type: PIN MI MI_VREF0-L POP N L PIN -GN PVREF POP N V LINE_R () LINE_L () nalog Plane igital Plane Z_RST#_UIO (,) Z_SYN_UIO () R /J_ Z_SIN0 () PIN NME R0 R R OE I MI_VREF0-L N POP L PVREF N POP V 0K/F_ Z_ITLK_UIO () Z_SOUT_UIO () MONO-OUT () HP_J# () MI_J# () Int. Stereo Speakers V / Ohm / W HP_OUT_R HP_OUT_L MI_VREFO_R MI_VREFO_L R /F R R SJ_00 SJ_00 SJ_00 SJ_00 R /F.K/J_.K/J_ V type: PIN MI PIN P LO output R *0K_N U_SPK_R+_R U_SPK_R-_R U_SPK_L+_R U_SPK_L-_R *00P_N 0 L LMG0SN 0 L LMG0SN 0 0 *00P_N 0 *00P_N 0 _GN _GN E *00P_N 0 0 *00P_N 0 E_EEP () Z_SPKR () J TY_- *00P_N 0 U_HP_R () U_HP_L () () N_MUTE# (,) Z_RST#_UIO N_MUTE# Z_RST#_UIO SM0K--F *SM0K--F_N P# P#=0V : Power down lass SPK amplifer P#=.V : Power up lass SPK amplifer Internal pulled high. R *K_N MI_R MI_L 0.U R 0 0 R 0.U 0 0 UM_IS_000_000_SSI_STEPHEN.SN K K L LMG0SN 0 L LMG0SN 0 0 *00P_N 0 _GN _GN 0 *00P_N 0 U_MI_R () U_MI_L () MI_VREFO R.K/J_ Z_ITLK_UIO R Reserve R for EMI *_N *P_N R0 R R R R R igital GN SJ_00 SJ_00 SJ_00 SJ_00 SJ_00 SJ_00 nalog GN Tied at one point only under the L or near the L MI_L MI_R 0.U 0 0 0.U 0 0 R R K K MI L *00P_N 0 heck the GN of MI onn. in the need add 0 ohm P to -GN L LMG0SN 0 MI_ () Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev zelia OE(L) ate: Monday, February 0, 00 Sheet of E

FM +V_SPK_MP INTERNL SUWOOFER MP SYN R *00K_N +V_SPK_MP R0 00K R 00K R 00K SYN V GN FLOT locked UFFER_VIS.U 00 () MONO-OUT () () ondition LINE_R LINE_L +V_SPK_MP U_MONO_OUT Only for '' Spread-spectrum mode with fs = 00kHz ±0kHz. Fixed-frequency mode with fs = 00kHz. Fixed-frequency mode with fs = 00kHz. Fixed-frequency mode with fs = external clock frequency. V VSS *0.U/.V_N U MXU+ 0.U/.V 0.U/.V +V_SPK_MP V VSS R 0K/F_ 0.0U/V U MXU+ R0 UFFER_VIS R 0K/F_ K R0 K/F_ +V_SPK_MP 0 +.V_RUN () EP (0) TEST_WOOFER_EN 0.0U R U MXU+ V VSS.K/F *00P_N 0 NPO R R SJ_00 +V_SPK_MP R *00K_N S 0K/F_ 0 SU_MUTE# *00P_N 0 0.0U/V S UFFER_VIS 0.0U/V R 0K/F_ R K SYN SU_MUTE# U_SU_GIN U_SU_GIN +V_SPK_MP R V VSS R 00K U MXU+ U_MONO_OUT R 00K/F_ K/F_ SHN# MUTE# SYN SYN_OUT MXETE+ W U/ 0V 00 U_SU_IN+ SU_IN+ 0ohm, SU_IN- L *LMPGSN_N U/ 0V 00 U IN+ OUT+ IN- MX OUT- 0 TQFN PIN G G Exposed Paddle +V_SPK_MP V GN PV PGN PV PGN R *00K_N R 00K Jack Sense SU_OUT+ R0 SU_OUT- R R 00K 0 0.U/V_ 0.U/V_ 0.U/V_ U_SU_GIN U_SU_GIN R *00K_N SJ_00 SU_OUT+_R SJ_00 SU_OUT-_R +V_SPK_MP 0U/.V_ 00 0.0U/V_ GIN GIN GIN 0 0 d 0 d 0 d d MI_J# () HP_J# () N MLX_-0 0.0U/V_ +V_SPK_MP +V_RUN U/ 0V 0 0 L 0U/ 0V_ 0 0 LMPG00SN F_0ohm+-%_00MHz 0.0ohm Layout Note: Place close to pin. N_MUTE# TEST_WOOFER_EN U_SPK P# SU_MUTE# 0 0 L (isable SPK) L (isable Woofer) 0 L (isable SPK) H (Test Woofer) 0 H (Test SPK) L (isable Woofer) H (Test SPK) H (Test Woofer) MI_J Q N00W--F _GN _GN Q N00W--F HP_J UM-IO-00.SN udio Jacks () U_HP_L U_HP_L () U_HP_R U_HP_R 00P 0 _GN 00P 0 _GN HP_J 0- N HP JKN R 00K +.V_RUN heck PIn efinition UM-IO-00.SN () U_MI_L U_MI_L () U_MI_R U_MI_R 00P 0 _GN 00P 0 _GN R 00K MI_J 0- N MI JK +.V_RUN heck PIn efinition igital GN nalog GN _GN Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev UIO ONN R R SJ_00 SJ_00 R SJ_00 lose N, N R *0_00_N nalog GN ate: Monday, February 0, 00 Sheet of

HMI_TX+_L HMI_TX-_L L EXG00U HMI_TX+ HMI_TX- HMI_TX0-_L HMI_TX0+_L L EXG00U HMI_TX0- HMI_TX0+ UM_UM_000_00_Ray.pdf HMI +.V_RUN HMI_TX+_L HMI_TX-_L L0 EXG00U HMI_TX+ HMI_TX- HMI_LK+_L HMI_LK-_L L EXG00U HMI_LK+ HMI_LK- +V_RUN R *SM0K--F_N SJ_00 +V_HMI_R 0mil HMIF For safty +V_HMI R.K/J_ 0L0WR R.K/J_ +V_HMI 0mil 0.U/0V_ HMI_TX+ HMI_TX- HMI_TX0+ HMI_TX0- HMI_LK+ HMI_SL_S HMI_S_S HMI_ET_R 0.U/0V_ 0 HMI_TX- HMI_TX+ HMI_LK- N SHELL 0 + GN Shield - + Shield - 0+ 0 Shield 0-0 K+ K Shield K- E Remote N LK T GN +V HP ETGN SHELL LL_--L *00P_N 0 *00P_N 0 +.V_RUN L LMPGSN U PIN I_EN PIN HPINV EQULIZTION SETTING P:P0=0:0 d P:P0=0: d Recommanded P:P0=:0 d P:P0=: 0d SLZ/SZ Low-level input/output Voltage FG0:FG00=0:0 VIL:<0.V VOL:0.V (efault) GF0:GF00=0: VIL:<0.V VOL:0.V GF0:GF00=:0 VIL:<0.V VOL:0.V GF0:GF00=: VIL:<0.V VOL:0.V HMI_PWR_TRL 0 is Enable is isable TI SNP H L H L 0 0.U/0V_ HMI VI 0.U/0V_ 0.U/0V_ HP Inversion VOH =0.V HP non-inversion VOH =.V 0.U/0V_ +.V_RUN +.V_RUN 0.U/0V_ R0 00K/J_ HMI_ET PQ N00W--F +V_HMI 0.U/0V_ () INT_HMI_TXP_ () INT_HMI_TXN_ () INT_HMI_TXP0_ () INT_HMI_TXN0_ () INT_HMI_TXP_ () INT_HMI_TXN_ () INT_HMI_TXP_ () INT_HMI_TXN_ () () () HMI_SL HMI_S HMI_ET R0 R0 R R0 R0 0.U/0V_.K/J EN *.K/J N P0.K/J_ P *.K/J N FG00 *.K/J N FG0 R0 0.U/0V_ R.K SJ_00 V V V V V V 0 V V SL S HP _EN P0 P UF_EN FG 0 RT_EN# OE# REXT ONTROL POWER GN IN_+ IN_- IN_+ IN_- IN_+ IN_- IN_+ IN_- OUT_+ OUT_- OUT_+ OUT_- 0 OUT_+ OUT_- OUT_+ OUT_- SL_SINK S_SINK HP_SINK 0 GN GN GN GN GN GN GN GN GN GN EP SNPRGZR(QFN) R value check HMI_LK+_L HMI_LK-_L HMI_TX0+_L HMI_TX0-_L HMI_TX+_L HMI_TX-_L HMI_TX+_L HMI_TX-_L HMI_SL_S HMI_S_S HMI_ET_L R K/J_ HMI_ET_R R0 *0/J N R0 *0/J N R00 *0_N R0 0/J_ R0 *0/J N For EMI HMI_LK+_L HMI_TX0+_L HMI_TX+_L HMI_TX+_L _EN P0 P FG00 FG0 *00_N *00_N *00_N *00_N R R R R HMI_LK_ HMI_TX0_ HMI_TX_ HMI_TX_ *0.U/0V N HMI_LK-_L *0.U/0V N HMI_TX0-_L *0.U/0V N HMI_TX-_L *0.U/0V N HMI_TX-_L Size ocument Number Rev lank Quanta omputer Inc. PROJET : UM UM ate: Monday, February 0, 00 Sheet of