Synchronous Sequential Logic Part I Mantıksal Tasarım BBM23 section instructor: Ufuk Çelikcan
Sequential Logic Digital circuits we have learned, so far, have been combinational no memory, outputs are entirely defined by the current inputs However, many digital systems encountered in everyday life are sequential (i.e. they have memory) the memory elements remember past inputs outputs of sequential circuits are not only dependent on the current input but also the state of the memory elements. 2
Sequential Circuits Model inputs Combinational Circuit outputs current state next state Memory Elements 3 current state is a function of past inputs + initial state
Classification There are 2 types of sequential circuits. Synchronous Signals affect the memory elements at discrete instants of time. Discrete instants of time requires synchronization. Synchronization is usually achieved through the use of a common clock. A clock generator is a device that generates a periodic train of pulses. 4
Classification. Synchronous The state of the memory elements are updated with the arrival of each pulse This type of logical circuit is also known as clocked sequential circuits. 2. Asynchronous No clock Behavior of an asynchronous sequential circuit depends upon the input signals at any instant of time and the order in which the inputs change. Memory elements in asynchronous circuits are regarded as time-delay elements 5
Clocked Sequential Circuits Memory elements are flip-flops which are logic devices, each of which is capable of storing one bit of information. inputs Combinational Circuit outputs current state next state clock Flip-Flops 6
Clocked Sequential Circuits The outputs of a clocked sequential circuit can come from the combinational circuit, the outputs of the flip-flops or both. The state of the flip-flops can change only during a clock pulse transition i.e. low-to-high and high-to-low clock edge When the clock maintains its value, the flip-flop output does not change The transition from one state to the next occurs at the clock edge. 7
Machine Machine ( Inputs {X}, States {D}, Outputs {Z}, Output Function {F : X D Z}, Next State Function {G : X D D} ) 8
Representation with State Diagram d d 2 x x 2 x i x l d i d j,z d r- d r 9
Assign a Node to Each State x k /z k x p /z p d i d j Machine is at state d i, input x k comes, the next state will be again d i and the output is z k Machine is at state d i, input x p comes, the next state will be d j and the output is z p
Assign a Node to Each State?/??/??? Machine is at state d m, input x t comes, the next state will be again d m and the output is z t Machine is at state d m, input x u comes, the next state will be d n and the output is z u
Notation Let Ik be an input sequence with length equal to k, i.e. Ik = xx2 xk f(ik,di) = zz2 zk g(ik,di) = didi2 dik is an output sequence is a state sequence di Ik dik : Follower of di after the input sequence Ik 2
Example - Fill out the rest A E, D, B F, D, C E, B, D F, B, E C, F, F B, C, A D B E C F 3
Example A E, D, B F, D, C E, B, D F, B, E C, F, F B, C, Let I5=, find g(i5,c) and f(i5,c) I5 g(i5,c) f(i5,c) I5 follower of C :? 4
Example A E, D, B F, D, C E, B, D F, B, E C, F, F B, C, Let I5=, find g(i5,c) and f(i5,c) I5 g(i5,c) C B F C B F f(i5,c) I5 follower of C is F 5
D Flip-Flop clk D C D FF Q Positive edge-triggered D Flip-Flop Characteristic equation Q(t+) = D D Q(t+) Characteristic Table 6
Timing Diagram of D Flip-Flop
8 Other Flip-Flops D flip-flop is the most common since it requires the fewest number of gates to construct. Two other widely used flip-flops JK flip-flops T flip-flops JK flip-flops Three FF operations. Set 2. Reset 3. Complement
JK Flip-Flops J K C Q J K Q(t+) next state Q(t) no change Reset Set Q (t) Complement Characteristic Table Characteristic Equation of JK flip-flop? 9
JK Flip-Flops 2 J Q C K J K Q(t) Q(t+) J K Q(t+) next state Q(t) no change Reset Set Q (t) Complement Characteristic Table
JK Flip-Flops J Q C K J K Q(t) Q(t+) J K Q(t+) next state Q(t) no change Reset Set Q (t) Complement Characteristic Table K,Q(t) J 2 Q(t+) =?
JK Flip-Flops J Q C K J K Q(t) Q(t+) J K Q(t+) next state Q(t) no change Reset Set Q (t) Complement Characteristic Table K,Q(t) J 22 Q(t+) =?
JK Flip-Flops J K C Q J K Q(t+) next state Q(t) no change Reset Set Q (t) Complement Characteristic Table Characteristic equation Q(t+) = JQ (t) + K Q(t) 23
T (Toggle) Flip-Flop Complementing flip-flop T C Q T Q(t+) next state Q(t) no change Q (t) Complement Characteristic Table Characteristic equation Q(t+) =? T J Q T D Q C C K 24
T (Toggle) Flip-Flop Complementing flip-flop T C Q T Q(t+) next state Q(t) no change Q (t) Complement Characteristic Table Characteristic equation Q(t+) = Q(t) T T J Q T D Q C C K 25
Characteristic Equations The logical properties of a flip-flop can be expressed algebraically using characteristic equations : D flip-flop Q(t+) = D JK flip-flop Q(t+) = JQ (t) + K Q(t) T flip-flop Q(t+) = Q(t) T 26
What if we have Q(t+) and Q(t), and looking for J and K values? Q(t)Q(t+) J,K,X,X X, X, J= K= Q(t+) X Q(t+) X Q(t)= Q(t)= Q(t)= Q(t)= 27
What if we have Q(t+) and Q(t), and looking for D value? Q(t)Q(t+) D D= Q(t+) 28
What if we have Q(t+) and Q(t), and looking for T value? Q(t)Q(t+) T T= Q(t) Q(t+) 29
Asynchronous Inputs of Flip-Flops They are used to force the flip-flop to a particular state independent of clock Preset (direct set) set FF state to Clear (direct reset) set FF state to They are especially useful at startup. In digital circuits when the power is turned on, the state of flip-flops are unknown. Asynchronous inputs are used to bring all flip-flops to a known starting state prior to clock operation. 3
Asynchronous Inputs data D Q clk C R D reset Q reset reset C D Q Q X X Starting State 3
Analysis of Clocked Sequential Circuits Goal: to determine the behavior of clocked sequential circuits Behavior is determined from Inputs Outputs State of the flip-flops We have to obtain Boolean expressions for output and next state output & state equations (state) table (state) diagram 32
Analyze the circuit
Run it and check the timing diagram
State Equations Also known as transition equations specify the next state as a function of the present state and inputs Example A(t+) D Q A x C A B(t+) D Q B C B y 36 clk
Output and State Equations A(t+) = B(t+) = y = input of a flip-flop determines the value of the next state (i.e., the state reached after the clock transition) A(t+) D Q A x C A B(t+) D Q B C B 37 clk y
Output and State Equations A(t+) = ( A(t) B(t) ) x B(t+) = (B(t)) x y = A(t)B(t) x A(t+) D Q A x C A B(t+) D Q B C B 38 clk y
Flip Flop Input Equations Flip-Flop input (excitation) equations Same as the state equations in D flip-flops 39
Example: State (Transition) Table A(t+) = B(t+) = y = ( AB + A B ) x B x ABx Present state input Next state output A B x A B y A sequential circuit with m FFs and n inputs needs 2 m+n rows in the transition table 4
4 Example: State (Transition) Table y B A x B A output Next state input Present state A sequential circuit with m FFs and n inputs needs 2 m+n rows in the transition table A(t+) = B(t+) = y = ( AB + A B ) x B x ABx
Example: State Diagram Present state input Next state output A B x A B y What is this circuit doing? State diagram provides the same information as state table 42
Example: State Diagram / / / / / / / / Present state What is this circuit doing? input Next state output A B x A B y State diagram provides the same information as state table 43
44 Analysis with JK Flip-Flops For a D flip-flop, the state equation is the same as the flip-flop input equation Q(t+) = D For JK flip-flops, situation is different Goal is to find state equations Method. determine flip-flop input equations 2. List the binary values of each input equation 3. Use the corresponding flip-flop characteristic table to determine the next state values in the state table
Example: Analysis with JK FFs x J A J Q A K A K C clk J B JD C K Q B K B y Flip-flop input equations J A = and K A = 45 J B = and K B =
Example: Analysis with JK FFs J A = Bx and K A = x +B J B = x and K B = present State input next state FF inputs A B x A B J A K A J B K B 46
47 Example: Analysis with JK FFs J A = Bx and K A = x +B J B = x and K B = K B J B K A J A B A x B A FF inputs next state input present State Characteristic equations A(t+) =? B(t+) =? y =?
Example: Analysis with JK FFs Characteristic equations A(t+) = J A A + K A A B(t+) = J B B + K B B y = ABx Input equations J A = Bx and K A = x +B J B = x and K B = State equations A(t+) = = B(t+) = 48
Example: Analysis with JK FFs Characteristic equations A(t+) = J A A + K A A B(t+) = J B B + K B B y = ABx Input equations J A = Bx and K A = x +B J B = x and K B = State equations A(t+) B(t+) = A Bx + (x +B) A = A Bx + AB x = (A B) x = B x 49
State Diagram Present state input Next state output A B x A B y 5 What is the circuit doing?
State Diagram / / / / / / / / Present state input Next state output A B x A B y 5 What is the circuit doing?
Analysis with T Flip-Flops Method is the same Example T A = T B = x T A T Q A y C A(t+) = B(t+) = clk T B TD C Q B y reset y = A y = B 52
Example: Analysis with T Flip-Flops Characteristic equation A(t+) = T A A B(t+) = T B B Input equations T A = Bx T B = x Output equations y = A y = B State equations A(t+) = B(t+) = 53
A(t+) = xb A B(t+) = x B y = A; y = B State Table & Diagram Present state input Next state output A B x A B y y 54
A(t+) = xb A B(t+) = x B y = A; y = B State Table & Diagram Present state input Next state output A B x A B y y 55
State Table & Diagram A(t+) = xb A B(t+) = x B y = A; y = B Present state input Next state output A B x A B y y 56
Mealy and Moore Models There are two models for sequential circuits Mealy Moore They differ in the way the outputs are generated Mealy: output is a function of both present states and inputs Moore output is a function of present state only 57
Example: Mealy and Moore Machines x y clock D C Q C reset S a Mealy machine External inputs x and y are asynchronous Thus, outputs may have momentary (incorrect) values Inputs must be synchronized with clocks Outputs must be sampled only during clock edges 58
Example: Moore Machines x T C Q A y clk TD C Q B reset Outputs are already synchronized with clock. They change synchronously with the clock edge. 59
Design Example - Implement the following state diagram with D FFs. / / / / x Q(t) Q(t+) D Z 6
Design Example - Implement the following state diagram with D FFs. / / / / x Q(t) Q(t+) D Z 6
Design Example - Implement the following state diagram with D FFs. / / / / x Q(t) Q(t+) D Z 62
Design Example - Implement the following state diagram with D FFs. / / / / x D Q Z clk x Q(t) Q(t+) D Z 63
Design Example - 2 Design a sequential circuit that counts up (,,,,, ) when x=, and counts down (,,,,, ) when x=. Use JK FFs. 64
Design Example - 2 Design a sequential circuit that counts up (,,,,, ) when x=, and counts down (,,,,, ) when x=. Use JK FFs. 65
Design Example - 2 Design a sequential circuit that counts up (,,,,, ) when x=, and counts down (,,,,, ) when x=. Use JK FFs. x= x= x= x= x= 66
Design Example - 2 x A B A(t+) B(t+) JA KA JB KB x= x= x= x= x= 67
Design Example - 2 x A B A(t+) B(t+) JA KA JB KB x= x= x= x= x= 68
Design Example - 2 x A B A(t+) B(t+) JA KA JB KB Q(t+) Q(t)= J= X Q(t)= x= x= x= x= x= K= 69 Q(t+) X Q(t)= Q(t)=
Design Example - 2 x A B A(t+) B(t+) JA KA JB KB X X X X Q(t+) Q(t)= J= X Q(t)= x= x= x= x= x= K= 7 Q(t+) X Q(t)= Q(t)=
Design Example - 2 x A B A(t+) B(t+) JA KA JB KB X X X X X X X X Q(t+) Q(t)= J= X Q(t)= x= x= x= x= x= K= 7 Q(t+) X Q(t)= Q(t)=
Design Example - 2 x A B A(t+) B(t+) JA KA JB KB X X X X X X X X X X X X Q(t+) Q(t)= J= X Q(t)= x= x= x= x= x= K= 72 Q(t+) X Q(t)= Q(t)=
Design Example - 2 x A B A(t+) B(t+) JA KA JB KB X X X X X X X X X X X X X X X X Q(t+) Q(t)= J= X Q(t)= x= x= x= x= x= K= 73 Q(t+) X Q(t)= Q(t)=
Design Example - 2 x A B A(t+) B(t+) JA KA JB KB X X X X X X X X X X X X X X X X x= x= x= x= x= J A =? K A =? J B =? K B =? 74
Design Example - 2 x A B A(t+) B(t+) JA KA JB KB X X X X X X X X X X X X X X X X x= x= x= x= x= AB x X X AB x X X 75 X X X X
Design Example - 2 JA = xb+x B KA = xb+x B JB= KB= Let s draw the circuit 76
Design Example - 3 OUTPUTS: design with JK flip-flops STATE TRANSITIONS: 77
Design Example - 3 A(t) B(t) C(t) A (t+) B (t+) C (t+) z z2 z3 z4 z5 z6 JA KA JB KB JC KC J= Q(t+) X Q(t)= Q(t)= K= Q(t+) X Q(t)= Q(t)= Mealy or Moore? 78
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 JA KA JB KB JC KC J= Q(t+) X Q(t)= Q(t)= K= Q(t+) X Q(t)= Q(t)= 79
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 JA KA JB KB JC KC J= Q(t+) X Q(t)= Q(t)= K= Q(t+) X Q(t)= Q(t)= 8
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 JA KA JB KB JC KC X X X X X X X J= Q(t+) X Q(t)= Q(t)= K= Q(t+) X Q(t)= Q(t)= 8
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 JA KA JB KB JC KC X X X X X X X J= Q(t+) X Q(t)= Q(t)= K= Q(t+) X Q(t)= Q(t)= 82
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 JA KA JB KB JC KC X X X X X X X X X X X X X X X X X X J= Q(t+) X Q(t)= Q(t)= K= Q(t+) X Q(t)= Q(t)= 83
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 JA KA JB KB JC KC X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X BC A BC A X X X X X X X X X X 84 JA= KA=
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 JA KA JB KB JC KC X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X BC A BC A X X X X X X X X X X 85 JA=BC KA=C
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 JA KA JB KB JC KC X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X BC A X X BC A X X X X X X X X 86 JB= KB=
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 JA KA JB KB JC KC X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X BC A X X BC A X X X X X X X X 87 JB=A C KB=C
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 JA KA JB KB JC KC X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X BC A X X BC A X X X X X X X X 88 JC= KC=
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 JA KA JB KB JC KC X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X BC A X X BC A X X X X X X X X 89 JC= KC=
Design Example - 3 JA QA JB QB JC QC C C C KA KB KC 9 We can also solve for outputs z-z6 by looking at K-maps of A(t),B(t),C(t)
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 JA KA JB KB JC KC JA=BC JB=A C JC= KA=C KB=C KC= 9
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 JA KA JB KB JC KC JA=BC JB=A C JC= KA=C KB=C KC= 92
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 JA KA JB KB JC KC JA=BC JB=A C JC= A(t+)=BCA +C A B(t+)=A CB +C B C(t+)=C KA=C KB=C KC= 93
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 JA KA JB KB JC KC 94
Design Example - 3 now let s redo the design with D FFs 95
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 DA DB DC A(t+)=BCA +C A = B(t+)=A CB +C B = C(t+)=C = 96
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 DA DB DC A(t+)=BCA +C A = DA B(t+)=A CB +C B = DB C(t+)=C = DC 97
Design Example - 3 A B C A(t) B(t) C(t) (t+) (t+) (t+) z z2 z3 z4 z5 z6 DA DB DC A(t+)=BCA +C A = DA B(t+)=A CB +C B = DB C(t+)=C = DC 98
Design Example - 4 Design a logic circuit with JK flip-flops that detects the sequence and outputs in that case, otherwise. 99
Design Example - 4?
Design Example - 4
Design Example - 4 X
Design Example - 4 I.C.
Design Example - 4 consider the sequence:
consider the sequence: I.C. ()
Design Example - 4 / / / / / I.C. / / 6 /
Design Example - 4 now we represent with states / / / / / / / 7 /
Design Example - 4 x(t) A(t) B(t) A B (t+) (t+) Z JA KA JB KB 8
Design Example - 4 A B x(t) A(t) B(t) (t+) (t+) 9 Z JA KA JB KB
Design Example - 4 A B x(t) A(t) B(t) (t+) (t+) Z JA KA JB KB X X X X X X X X X X X X X X X X
Design Example - 4 AB x AB x JA= AB x KA= AB x JB= KB=
Design Example - 4 AB x X X X X JA=x B AB x X X X X JB=x AB x X X X X KA=xB+x B AB x X X X X KB=x 2
Design Example - 4 JA QA JB QB C C KA KB 3
Design Example - 4 DA QA DB QB C C 4