Combinational Logic Design/Circuits

Similar documents
Minimization techniques

Unit 2 Session - 6 Combinational Logic Circuits

This form sometimes used in logic circuit, example:

211: Computer Architecture Summer 2016

Ex: Boolean expression for majority function F = A'BC + AB'C + ABC ' + ABC.

Simplification of Boolean Functions. Dept. of CSE, IEM, Kolkata

CHAPTER III BOOLEAN ALGEBRA

Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions

Digital Logic Design. Combinational Logic

CHAPTER III BOOLEAN ALGEBRA

Chap 2. Combinational Logic Circuits

Combinational Logic Fundamentals

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps

Boolean Algebra and Logic Simplification

MC9211 Computer Organization

Combinational Logic Circuits Part II -Theoretical Foundations

ENG2410 Digital Design Combinational Logic Circuits

UNIT 4 MINTERM AND MAXTERM EXPANSIONS

Chapter 7 Logic Circuits

Chapter 2 Combinational Logic Circuits

Chapter 2 : Boolean Algebra and Logic Gates

EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive

EEE130 Digital Electronics I Lecture #4

UNIT 5 KARNAUGH MAPS Spring 2011

ELCT201: DIGITAL LOGIC DESIGN

Chapter 2 Boolean Algebra and Logic Gates

Midterm1 Review. Jan 24 Armita

Combinational Logic. Review of Combinational Logic 1

MODULAR CIRCUITS CHAPTER 7

Review. EECS Components and Design Techniques for Digital Systems. Lec 06 Minimizing Boolean Logic 9/ Review: Canonical Forms

Vidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution

Logic. Combinational. inputs. outputs. the result. system can

Unit 3 Session - 9 Data-Processing Circuits

KP/Worksheets: Propositional Logic, Boolean Algebra and Computer Hardware Page 1 of 8

ELC224C. Karnaugh Maps

Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing

( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function

Karnaugh Map & Boolean Expression Simplification

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18

Lecture 2 Review on Digital Logic (Part 1)

Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary

Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University

Digital Circuit And Logic Design I. Lecture 4

Logic Design I (17.341) Fall Lecture Outline

Combinational Logic. By : Ali Mustafa

Boolean Algebra and Logic Design (Class 2.2 1/24/2013) CSE 2441 Introduction to Digital Logic Spring 2013 Instructor Bill Carroll, Professor of CSE

DIGITAL ELECTRONICS & it0203 Semester 3

CPE100: Digital Logic Design I

UNIT 1. BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS

KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE

Systems I: Computer Organization and Architecture

Prof.Manoj Kavedia 2 Algebra

CS 226: Digital Logic Design

Logic Design. Chapter 2: Introduction to Logic Circuits

WEEK 3.1 MORE ON KARNAUGH MAPS

ENGG 1203 Tutorial - 2 Recall Lab 2 - e.g. 4 input XOR. Parity checking (for interest) Recall : Simplification methods. Recall : Time Delay

Chapter 2. Boolean Algebra and Logic Gates

CHAPTER1: Digital Logic Circuits Combination Circuits

Part 1: Digital Logic and Gates. Analog vs. Digital waveforms. The digital advantage. In real life...

Chapter 2 Combinational Logic Circuits

Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011

Week-I. Combinational Logic & Circuits

L2: Combinational Logic Design (Construction and Boolean Algebra)

UNIT II COMBINATIONAL CIRCUITS:

Gate-Level Minimization

Cs302 Quiz for MID TERM Exam Solved

Administrative Notes. Chapter 2 <9>

Chapter 2 Combinational logic

Binary logic consists of binary variables and logical operations. The variables are

LOGIC GATES. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.

CS470: Computer Architecture. AMD Quad Core

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.

Introduction to Digital Logic Missouri S&T University CPE 2210 Karnaugh Maps

Computer Organization I. Lecture 13: Design of Combinational Logic Circuits

COMBINATIONAL LOGIC FUNCTIONS

Chapter 4: Combinational Logic Solutions to Problems: [1, 5, 9, 12, 19, 23, 30, 33]

DHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN

Introduction to Karnaugh Maps

Review for Test 1 : Ch1 5

Signals and Systems Digital Logic System

The Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS

ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN VALUES

Every time has a value associated with it, not just some times. A variable can take on any value within a range

Chapter-2 BOOLEAN ALGEBRA

Optimizations and Tradeoffs. Combinational Logic Optimization

Simplifying Logic Circuits with Karnaugh Maps

L4: Karnaugh diagrams, two-, and multi-level minimization. Elena Dubrova KTH / ICT / ES

Number System conversions

Logic Simplification. Boolean Simplification Example. Applying Boolean Identities F = A B C + A B C + A BC + ABC. Karnaugh Maps 2/10/2009 COMP370 1

Logic Gate Level. Part 2

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 2 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

Ch 2. Combinational Logic. II - Combinational Logic Contemporary Logic Design 1

Design of Combinational Logic

Class Website:

Digital Logic Design ABC. Representing Logic Operations. Dr. Kenneth Wong. Determining output level from a diagram. Laws of Boolean Algebra

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits


BOOLEAN ALGEBRA CLASS XII. Presented By : Dinesh Patel PGT CS KV IIT Powai

Transcription:

3 ` Combinational Logic Design/Circuits Chapter-3(Hours : 12 Marks:24 ) Combinational Logic design / Circuits 3.1 Simplification of Boolean expression using Boolean algebra. 3.2 Construction of logical circuits forms Boolean expressions. 3.3 Boolean expressions using Sum of products and product of sums forms. 3.4 K-map representation of logical functions. 3.5 Minimization of logical expressions using K-map ( 2, 3, 4 variables). 3.6 Standardization of SOP & POS equations 3.7 Concept of Adders / Subtractor. 3.8 Truth table, K-map, Simplified logical expression and logical circuit using basic gates and universal gates of : (a) Half adder and full adder. (b) Half subtractor and full subtractor. 3.9 Block diagram, Truth table, Logical expression and logic diagram of Multiplexers (4:1 and 8:1), Multiplexer IC. 3.10 Block diagram and Truth table of Demultiplexer (1:4; 1:8;1:16), Demultiplexer IC. 3.11 Block diagram and Truth table of Encoders, Priority Encoders ICs and Decoder. 3.12 Block diagram, Truth table, working principle, Applications, pin functions of Decimal to BCD Encoder (IC 74147) and BCD to 7-segment Decoder. Block diagram and function table of Parity generator (IC 74180), Digital comparator IC (7485); Block diagram and pin functions of ALU 74181 Combinational Logic Circuit Combination Logic circuits are made up from basic logic AND, OR or NOT gates that are "combined" or connected together to produce more complicated switching circuits. As combination logic circuits are made up from individual logic gates they can also be considered as "decision making circuits" and combinational logic is about combining logic gates together to process two or more signals in order to produce at least one output signal according to the logical function of each logic gate. Common combinational circuits made up from individual logic gates include Multiplexers, Decoders and De-multiplexers, Full and Half Adders etc. Classification of Combinational Logic One of the most common uses of combination logic is in Multiplexer and De-multiplexer type circuits. Here, multiple inputs or outputs are connected to a common signal line and logic gates are used 1

to decode an address to select a single data input or output switch. A multiplexer consist of two separate components, a logic decoder and some solid state switches, but before we can discuss multiplexers, decoders and de-multiplexers in more detail we first need to understand how these devices use these "solid state switches" in their design. Standard Representation For Logical Function Q1.What is Variable and list the standard from of the Boolean Function Ans.A Variable in complemented or uncomplemented form is known as Literal. Thus Boolean functions or equation are expressed in terms of literal. The values assumed by literal are in binary form. Any Boolean function can be expressed in two standard or canonical forms 1) Sum of product (SOP) 2) Product of sum (POS) If each term in SOP and POS form contain all the literal (variables) then these are known as standard SOP or standard POS form. Q2.What SOP and How SOP Equations are represented? Ans.Standard SOP form Each individual term in standard SOP form is called as minterm. Y = PQR + PQR + PQR + PQR + PQR 2

This contain all the independent variable in SOP form which is obtained by first ANDing and then ORing them i.e. minterm or each term. Hence above equation has 5 minterm's PQR,PQR,PQR,PQR,PQR. The possible number of minterm is equal to 2 to the power of number of variable i.e. if 3 variables are present in equation then there are 2 3 = 8 minterm's. Minterm with normal complemented variables is taken as 0 and uncomplemented is taken as 1. Fig. Shows the truth able for 3 variables Boolean expressions. A B A Decimal equivalent Minterm(mi) Notation 0 0 0 0 CBA m0 0 0 1 1 CBA m1 0 1 0 2 CBA m2 0 1 1 3 CBA m3 1 0 0 4 CBA m4 1 0 1 5 CBA m5 1 1 0 6 CBA m6 1 1 1 7 CBA m7 Using these notation we can write equation as Y = m7 +m6+m5+m4+m3+m2+m1+m0 Y = m Σ (0,1,2,3,4,5,6,7) Hence it is easy to used notation instead of minterm. The symbol Σ represent ORing of minterm. Q3. Write truth table and equation in SOP form for following minterm. Y = m(1,3,6,7) Ans : Minterm are M1,M2,M3,M4,M5,M6,M7. And equation has 3 variables. Hence the truth table is M table for minterm available in function write 1. A B C Minterm Notations Y 0 0 0 ABC M0 0 0 0 1 ABC M1 1 0 1 0 ABC M2 0 0 1 1 ABC M3 1 1 0 0 ABC M4 0 1 0 1 ABC M5 0 1 1 0 ABC M6 1 1 1 1 ABC M7 1 Y = ABC +ABC+ABC+ABC. 3

In general each row of truth table has functional value 1 described by minterm. The minterm is product of literal. The complement variable has value logic 0 and uncomplemented variable has value logic 1. Combining all the products term (minterm) constructed for the variable having value=1 i.e. minterm value = 1 by Boolean OR operation results in minterm canonical form. Q4.What POS and How POS Equations are represented? Ans.Product of Sum( POS ) Product of sum method is also called as maxterm canonical form. Consider the equation Y = (A+B+C)(A+B+C)(A+B+C) In this approach independent variables are ORing is followed by ANDing of individual term. Each individual is called as maxterm. Number of maxterm depends on number of literal or variables i.e. if equation has three variables then there will be 2 3 = 8 maxterm. Each maxterm is represented by M i where subscript i is decimal equivalent of natural binary number. The maxterm with complemented variable is taken as 1 and uncomplemented variable is taken as 0. Table shows possible maxterm for 3 variables equation. A B C Decimal equivalent Maxterm Notation Mi 0 0 0 0 M0 A+B+C 0 0 1 1 M1 A+B+C 0 1 0 2 M2 A+B+C 0 1 1 3 M3 A+B+C 1 0 0 4 M4 A+B+C 1 0 1 5 M5 A+B+C 1 1 0 6 M6 A+B+C 1 1 1 7 M7 A+B+C Using this notation above equation can be written as M2.M3.M4 = πm( i=2,3,6) = πm(2,3,6) Where π is represented ANDing of maxterm Y = (A+B+C)(A+B+C)(A+B+C) Q5.Write truth table and equation in POS form for following minterm. Y = ( A+B+C)(A+B+C)(A+B+C) 4

A B C Decimal equivalent Y = πm(2,3,6) Maxterm Mi Notation 0 0 0 0 M0 A+B+C 1 0 0 1 1 M1 A+B+C 1 0 1 0 2 M2 A+B+C 0 0 1 1 3 M3 A+B+C 0 1 0 0 4 M4 A+B+C 1 1 0 1 5 M5 A+B+C 1 1 1 0 6 M6 A+B+C 0 1 1 1 7 M7 A+B+C 0 In general each row of truth table represent that has functional (i.e. output) of logical 0. It is described by maxterm. Maxterm is sum of all the term. In maxterm representation complemented variable has value 1 and uncomplemented variable has value 0. Combining all the sum term(maxterm) constructed for variable having value logic 0 by Boolean AND operation results in maxterm canonical form. Q6.Write truth table and equation in SOP form for following minterm. πm(2,3,6,7) Solution: A B C Decimal Maxterm Mi Notation Y equivalent 0 0 0 0 M0 A+B+C 1 0 0 1 1 M1 A+B+C 1 0 1 0 2 M2 A+B+C 0 0 1 1 3 M3 A+B+C 0 1 0 0 4 M4 A+B+C 1 1 0 1 5 M5 A+B+C 1 1 1 0 6 M6 A+B+C 0 1 1 1 7 M7 A+B+C 0 Substitute 0 for all values represented in equation and then AND all maxterm from truth table (A+B+C) (A+B+C) (A+B+C) (A+B+C) Q7.Describe Conversion of SOP to standard SOP form Ans.The SOP form can be converted to standard SOP form by ANDing the term in the expression with term form by ORing the variable and its complement which are not present in that term. AB+AB+BC In first term C is missing, AND it with(c+c) Y 5

In second term B is missing, AND it with(b+b) In third term A missing, AND it with (A+A) Y = AB(C+C)+AC(B+B)+BC(A+A) = ABC+ABC+ABC+ABC+ABC+ABC Y = ABC+ABC+ABC+ABC+ABC Hence above equation is standard SOP equation. Q8.Describe the step Conversion of standard SOP to POS Ans.The Boolean expression in standard SOP form can be converted to standard POS as follows: 1) Complement the Boolean expression in standard SOP form which will contain missing minterm. 2) Complement the individual missing minterm to get maxterm and by using demorgan law change OR(sum) to AND (product). Q9.Describe the Conversion of POS to standard POS Ans.The POS form can be converted to standard POS form by ORing the terms in the expression with terms formed by ANDing the variable and its complement which are not present in that term. Y = (A+B)(A+C)(B+C) to standard POS form. 1 st term A+B, C is missing, OR with it C.C 2 nd term A+C, B is missing, OR it with B.B 3 rd term B+C, A is missing, Or it with A.A Y = (A+B+C.C)(A+C+B.B)(B+C+A.A) = (A+B+C)(A+B+C)(A+B+C)(A+B+C)(A+B+C)(A+B+C) Y = (A+B+C)(A+B+C)(A+B+C)(A+B+C) Hence above equation is in standard POS form. Q10.Convert Y = ABC+ABC+ABC+ABC+ABC in standard SOP form to standard POS form. Terms in the minterm are m1, m3, m4, m5, m7 1) Step1:Missing minterm are M0,M2,M6. Y = Σ(m0,m2,m6) Y = Σ(m0,m2,m6) 2) Step2: Complement equation using DMT. Y = π(m0,m2,m6) Y = (A+B+C)(A+B+C)(A+B+C) Q11.Describe the Conversion of standard POS to Standard SOP form The Boolean expression in standard POS form can be converted to standard SOP form by following, following procedure 6

1) Complement the Boolean expression in standard POS form which will contain missing maxterm. 2) Complement the individual missing maxterm to get the minterm and by using demorgan(dmt) law change AND(product) to OR(sum). Q12.Convert the Boolean expression SPOS to SSOP (A+B+C) (A+B+C) (A+B+C) = (M0,M3,M4) Solution 1) Step1: Missing maxterm are M1,M2,M5,M6,M7. Y = πm1,m2,m5,m6,m7. 2) Step2 : Complement expression by DMT. Y = πm1.m2.m5.m6.m7 = ABC+ ABC+ ABC+ ABC+ ABC Q13.List the different Boolean expression simplification technique Ans.The SSOP or SPOS equation that has more than just a few products are difficult to reduce by algebraic method. Karnaugh map or K-map method is used for simplification of Boolean expression. It is graphical method of representation. But if number of variables are more than 4 or exceeds 4 than it is difficult to solve using K-map than other following techniques are used. 1) Variable entered mapping 2) Quine MC cluskey method Hence to solve any Boolean expression there are four methods out of Which two are listed above and other two are 1) Algebraic method 2) K-map method. Q14.What is Karnaugh or K-map?Describe Ans. The Karnaugh map, like Boolean algebra, is a simplification tool applicable to digital logic. Maurice Karnaugh, a telecommunications engineer, developed the Karnaugh map at Bell Labs in 1953. Karnaugh map or K-map method is used for simplification of Boolean expression. It is graphical method of representation k-map for two, three and four variable is shown in fig. In an n-variable K- map there are 2 n cells. Each cell corresponds to one of the combination of n- variables. In k-map one cell represent one minterm or maxterm. In k-map the variables and all possible values of the variable are indicated to identify cell. GRAY code is used for identification of cell. 0 1 00 01 Sample Two, Three and Four Variable KMaps 11 10 0021132 variable k-map (n=2) F(AB) 00264113753 variable k-map (n=3) F(ABC) 00041280115139113715111 012614104-Variable K-Map (n=4) 7

8

Q15.Describe Two Variable K Maps? Ans.2-variable k-map: Table shows truth table for 2 variable equation In 2 variable A & B has four combination corresponds to 4-minterm (or maxterm) and needs four location in k-map. These four locations corresponds to 4 rows of truth table. A 1 is placed in those boxes where minterm are included (1) and 0 is included where the minterm are absent or excluded (0). Hence for above truth table the k-map is Truth Table A B Y 0 0 0 0 1 1 1 0 0 1 1 1 Minterms K- Map Entry 0 1 0 AB AB 1 AB AB 0 1 0 0 1 1 0 1 Q16.Describe Three Variable K Maps? Ans. 3 variable k-map : Truth table for three variable k-map is as shown. For three variable equation k-map will have 8 cells as shown(2 3 = 8). A 1 is placed in those boxes where minterm are included (1) and 0 is included where the minterm are absent or excluded (0). Hence for above truth table the k-map is K Map For 3 Variable 0 ABC ABC ABC ABC 1 ABC ABC ABC ABC In this case also enter 1 for minterm's whose 1 and 0 for the maxterm's 00 01 10 11 0 0 1 0 1 1 1 0 1 1 Truth Table A B C Y 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 1 9

Q17.Describe Three Variable K Maps? Ans. 4 variable k-map : Table shows truth table for 4-variable Boolean expression. For 4 variable equation k-map has 16 cells i.e. 2 4 = 16 A 1 is placed in those boxes where minterm are included (1) and 0 is included where the minterm are absent or excluded (0). Hence for above truth table the k-map is Truth Table ABCDY000010001100100001100100 101011011000111010001100111010 11011011001110111110111110 K-Map for 4-Variable is as shown 00ABCDABCDABCDABCD01ABCDABC DABCDABCD11ABCDABCDABCDABC D10ABCDABCDABCDABCD K Map 0011110111111100001000 11 Q18.Describe the terms Minterm and Maxterm Ans.Minterm A product in as SSOP is called as Minterm.A minterm is a Boolean expression resulting in 1 for the output of a single cell, and 0s for all other cells in a Karnaugh map, or truth table. If a minterm has a single 1 and the remaining cells as 0s, it would appear to cover a minimum area of 1s. 10

The example above left shows the minterm ABC, a single product term, as a single 1 in a map that is otherwise 0s. Another minterm A'BC' is shown above right. The point to noted is that the address of the cell corresponds directly to the minterm being mapped. That is, the cell 111 corresponds to the minterm ABC above left. Above right we see that the minterm A'BC' corresponds directly to the cell 010. A Boolean expression or map may have multiple minterms. Maxterm A product in as SPOS is called as Maxterm.A maxterm is a Boolean expression resulting in a 0 for the output of a single cell expression, and 1s for all other cells in the Karnaugh map, or truth table. The illustration above left shows the maxterm (A+B+C), a single sum term, as a single 0 in a map that is otherwise 1s. If a maxterm has a single 0 and the remaining cells as 1s, it would appear to cover a maximum area of 1s. The maxterm is a 0, not a 1 in the Karnaugh map. A maxterm is a sum term, (A+B+C) in our example, not a product term. Therefore (A+B+C) is mapped into the cell 000. For the equation Out=(A+B+C)=0, all three variables (A, B, C) must individually be equal to 0. Only (0+0+0)=0 will equal 0. Thus we place our sole 0 for minterm (A+B+C) in cell A,B,C=000 in the K-map, where the inputs are all0. This is the only case which will give us a 0 for our maxterm. All other cells contain 1s because any input values other than ((0,0,0) for (A+B+C) yields 1s upon evaluation. Q19.List the Procedure for placing a minterm in a K-map Ans. Following are the steps to Place Minterm in KMAP identify the minterm (product term) term to be mapped. Write the corresponding binary numeric value. Use binary value as an address to place a 1 in the K-map Repeat steps for other minterms (P-terms within a Sum-Of-Products). 11

Q20.List the Procedure for placing a maxterm in a K-map Ans. Following are the steps to Place Maxterm in KMAP Identify the Sum term to be mapped. Write corresponding binary numeric value. Form the complement Use the complement as an address to place a 0 in the K-map Repeat for other maxterms (Sum terms within Product-of-Sums expression). Q21.List the procedure for writing the Sum-Of-Products reduced Boolean equation from a K-map: Ans : The procedure for writing the Sum-Of-Products reduced Boolean equation from a K-map: Form largest groups of 1s possible covering all minterms. Groups must be a power of 2. Write binary numeric value for groups. Convert binary value to a product term. Repeat steps for other groups. Each group yields a p-terms within a Sum-Of- Products. Q22.List the procedure for writing the Product-Of-Sums Boolean reduction for a K- map: Ans.The procedure for writing the Product-Of-Sums Boolean reduction for a K-map: Form largest groups of 0s possible, covering all maxterms. Groups must be a power of 2. Write binary numeric value for group. Complement binary numeric value for group. Convert complement value to a sum-term. Repeat steps for other groups. Each group yields a sum-term within a Product-Of- Sums result. Q23.Describe the terms PAIR, QUAD and OCTECTS related to KMAPS Ans.Simplification of logical function with k-map is based on the principle of combining terms in adjacent cells. Two cells are said to be adjacent if they differ in only one variable. Also left two cells and right two cells are adjacent Similarly simplification of logical function is achieved by grouping adjacent 1 s or 0 s in group of 2 i where i= 0,1,2,3 i.e. up to the number of variables. PAIR : Grouping two adjacent ones: If there are two adjacent ones in k- map these can be grouped together and the resulting term will have one literal less than original two terms (minterm) i.e. Pairs. 12

0101011010 AB+AB 0110010000 AC 0000010110 Y = BC 00110001001111010010010 0Other possibilities 00010001011111000010011 1Other possibilities QUAD : Grouping adjacent 4 one s: A quad is group of four 1 s that are 1) Horizontally or vertically adjacent. 2) 1 s may be end to end. 3) 1 s in form of a square. In quad group two variable and their complement are eliminated. 0111110000 Y = C 00010001010011010 0100100 Y = AB 000000011111110000100 000 CD 0110011100 Y = 00011001011011000 0100000 Y = 000000010110110110100 000 13

OCTECT: Grouping of adjacent 8 one s: Other than pair there is one more group of adjacent 1 s i.e. the octet. This is a group of 8-1 s as shown in fig. An octect group eliminates three variables and its complement. 00 0 0 0 0 01 1 1 1 1 11 1 1 1 1 10 0 0 0 0 00 0 0 0 0 01 1 1 1 1 11 1 1 1 1 10 0 0 0 0 00 0 0 0 0 01 1 1 1 1 11 1 1 1 1 10 0 0 0 0 Overlapping Groups: When there are pairs, quads, octet in a k-map. There is possibility that these group overlap i.e. it is possible to combine a particular 1 in k-map in more than one way. 0 1 1 1 1 1 0 1 0 0 Y = 00 1 1 1 1 01 1 1 1 1 11 1 1 1 1 10 1 1 0 0 00 1 1 0 1 01 1 1 1 1 11 1 1 1 1 10 1 1 0 0 Q24.Describe the term ROLLING, Redundant Group, Corner related to KMAP Ans. Rolling the map :Rolling of map is also possible as shown in fig. In k-map rolling is done so that the left side touches the right side. If you see carefully it is two pair forming quad. 0 1 0 0 1 1 1 0 0 1 00 1 0 0 1 01 0 0 0 0 11 0 0 0 0 10 1 0 0 1 00 0 1 1 0 01 1 0 0 1 11 1 0 0 1 10 0 1 1 0 00 1 1 1 1 01 0 0 0 0 11 0 0 0 0 10 1 1 1 0 Other possibilities 0 1 0 0 1 1 0 0 0 0 00 1 0 0 1 01 1 0 0 1 11 0 0 0 0 10 0 1 0 0 00 0 0 1 0 01 1 0 0 1 11 0 0 0 0 10 1 0 1 1 00 1 0 0 1 01 1 0 0 1 11 1 0 0 1 10 1 0 0 1 14

Eliminate redundant group After you finished encircling groups, eliminate any redundant group. This is a group whose 1 s are already grouped. In fig. All pairs are grouped, then if you form quad, already all 1 s of quad are grouped in pair. Therefore quad is redundant it should be eliminated. 00 0 0 1 0 00 0 0 1 0 01 1 1 1 0 01 1 1 1 1 11 0 1 1 1 11 0 1 1 1 Corner 10 0 1 0 0 10 0 1 0 0 Fold up the corners of the map below like it is a napkin to make the four cells physically adjacent. The four cells above are a group of four because they all have the Boolean variables B' and D' in common. In other words, B=0 for the four cells, and D=0 for the four cells. The other variables (A, B) are 0 in some cases, 1 in other cases with respect to the four corner cells. Thus, these variables (A, B) are not involved with this group of four. This single group comes out of the map as one product term for the simplified result: Out=B'C' Q25. Find grouping for following k-map? 00 0 0 0 0 01 0 0 1 0 11 1 1 1 1 10 0 1 1 1 15

Q26.List the Rules for simplification of k-maps Ans.Rules for Simplification of KMAP 2 variables k-maps 1) Any two in adjacent is one then k-map may be k-map combined to represent single variable. 2) Any single 1 on map represent the AND function (product) of two variables. 3) The total expression corresponding to 1 s of map the ORed function(sum) of various variable term which covers all 1 s in the map 3 variable k-maps 1) A group of 4-adjacent 1 s can be combined to represent a single variable. 2) A group of 2-adjacent 1 s can be combined to represent 2 variable. 3) Any single 1 on map represent three variable. 4 variable k-map 1) Grouping of 8-1 s represent a single variable term. 2) Group of 4-1 s represent two variables term. 3) Group of 2-1 s represent 3 variable term. 4) Individual 1 s represent 4-variable terms. Notes 1) Top row is considered to be adjacent to bottom row. 2) Extreme left hand row is adjacent to the extreme right hand row. 3) Always try to overlap group of possible i.e. try to make largest group. 4) Sometimes take care that all the 1 s should not overlap. Q27.Simplify the Following Ans. 16

Circuit Diagram for the Solution obtained 17

Q28. Simplify the following Boolean expression: 1) f(a,b,c) = πm(0,2,4,6,7) Solution: A B C Y 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1 AB 00 1 1 1 1 01 0 0 1 0 Y = 2. f(a,b,c,d) = πm(0,1,5,7,8,9,12,13,15) Solution: A B C D Y 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 00 1 1 1 1 01 1 1 1 1 11 0 1 1 0 10 0 0 0 0 2. f(a,b,c,d) = πm(0,1,2,4,5,8,9,10) Implementation using NAND and OR gate after simplification. Solution: A B C D Y A B C D Y 0 0 0 0 1 1 0 0 0 1 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 1 1 0 0 0 0 1 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 1 0 0 0 1 1 1 0 1 1 1 1 0 00 1 1 0 1 01 1 1 0 1 11 0 0 0 0 10 1 0 0 1 18

Q29. Simplify 1) f(a,b,c,d) = πm(1,3,4,5,6,7,8,9,13,15) Implement using NOR gate Solution: AB 00 1 0 1 0 01 0 0 0 0 11 0 0 0 1 10 1 0 1 1 2) f(a,b,c,d) = πm(4,5,6,7,8,12) Solution: AB f= 00 1 0 0 0 01 1 0 1 1 11 1 0 1 1 10 1 0 1 1 19