課程名稱 : 數位邏輯設計 P-1/41 2012/6/11 extbook: igital esign, 4 th. Edition M. Morris Mano and Michael. iletti Prentice-Hall, Inc. 教師 : 蘇慶龍 INSRUOR : HING-LUNG SU E-mail: kevinsu@yuntech.edu.tw
hapter 6 P-2/41 2012/6/11 hapter 6 Registers and ounters
Outline of hapter 6 P-3/41 2012/6/11 6.1 Registers 6.2 Shift Registers 6.3 Ripple ounters 6.4 Synchronous ounters 6.5 Other ounters 6.6 HL for Registers and ounters
6.1 Registers P-4/41 2012/6/11 6.1 Registers 6.2 Shift Registers 6.3 Ripple ounters 6.4 Synchronous ounters 6.5 Other ounters 6.6 HL for Registers and ounters
6.1 Registers P-5/41 2012/6/11 Registers 1. A register is a group of flip-flops. 2. An n-bit register consists of a group of n flip-flops capable of storing n bits of binary information. 3. A counter is essentially a register that goes through a predetermined sequence of states. 4. he simplest register is one that consists of only flipflop without any gates 5. he common clock input triggers all flip-flop on the positive or negative clock edges. 6. he clear inputs asynchronously goes to the R (reset) input of all four flip-flops. 7. he R inputs must be maintained at logic 1 during normal clocked operation.
6.1 Registers P-6/41 2012/6/11 I 0 A 0 R I 1 A 1 4-Bit Registers R I 2 A 2 lear = 0 ; A x =0 lock = ; A x = I x Normal Operation ; lear = 1 R I 3 A 3 lock R lear (Active Low)
6.1 Registers P-7/41 2012/6/11 1/0 0/1 1/0 Load A 0 I 0 0/1 A 1 Register with Parallel Load I 1 1/0 A 2 Parallel Load ( ) No hange ( ) I 2 A 3 I 3 lock
6.2 Shift Registers P-8/41 2012/6/11 6.1 Registers 6.2 Shift Registers 6.3 Ripple ounters 6.4 Synchronous ounters 6.5 Other ounters 6.6 HL for Registers and ounters
6.2 Shift Registers P-9/41 2012/6/11 4-Bit Shift Registers Serial Input SI SO Serial Output lock
6.2 Shift Registers P-10/41 2012/6/11 Serial ransfer vs. Parallel ransfer 1. Serial Mode of igital Systems: Manipulation one bit at a time. 2. Serial ransfer: ransferring one bit at a time by shifting the bits out of the source register into the destination register. 3. Parallel ransfer: All the bits of the register are transferred at the same time.
6.2 Shift Registers P-11/41 2012/6/11 Serial ransfer form Register A to Register B Block iagram Shift ontrol External lock External lock Shift Register A Shift Register B SI SO SI SO Internal lock iming iagram Shift ontrol Internal lock 1 2 3 4 4-bit ata randferring
Self-copy 6.2 Shift Registers P-12/41 2012/6/11 iming of Serial ransfer Example iming Pulse Shift Register A Shift Register B Initial Value 1 0 1 1 0 0 1 0 After 1 1 1 0 1 1 0 0 1 After 2 1 1 1 0 1 1 0 0 After 3 0 1 1 1 0 1 1 0 After 4 1 0 1 1 1 0 1 1 Serial ransfer
6.2 Shift Registers P-13/41 2012/6/11 Serial Addition: Slower but requiring less equipment Shift ontrol lock Serial Input Shift Register A Shift Register B x y z FA S Q R Register A + Register B = Register A + (Augend) (Addend) (Sum) lear
6.2 Shift Registers P-14/41 2012/6/11 Second Form of Serial Adder: Implemented with JK FF State able for Serial Adder Present Next Flip-Flop State Inputs State Output Input Q( in ) x y Q( out ) S J Q K Q 0 0 0 0 0 0 X 0 0 1 0 1 0 X 0 1 0 0 1 0 X 0 1 1 1 0 1 X 1 0 0 0 1 X 1 1 0 1 1 0 X 0 1 1 0 1 0 X 0 1 1 1 1 1 X 0 Simplified Equation J Q = xy K Q = x y = (x+y) S = x + y + Q
6.2 Shift Registers P-15/41 2012/6/11 Second Form of Serial Adder: ircuit iagram Shift ontrol lock Shift Register A x S Serial Input Shift Register B y J Q ( in/out ) K lear
6.2 Shift Registers P-16/41 2012/6/11 General Shift Register 1. A clear control to clear the register to 0 2. A clock input to synchronize the operations 3. A shift-right control to enable the shift right operation and the serial input and output lines associated with the shift right 4. A shift-left control to enable the shift left operation and the serial input and output lines associated with the shift left 5. A parallel-load control to enable a parallel load transfer and n input lines associated with the parallel transfer 6. n parallel output lines 7. A control state that leaves the information in the register unchanged in the presence of the clock
6.2 Shift Registers P-17/41 2012/6/11 lassification of Shift Register 1. Unidirectional Shift Register: A register capable of shifting in one direction 2. Bidirectional Shift Register: A register can shift in both directions 3. Universal Shift Register: Bidirectional shift register + parallel load capability
6.2 Shift Registers P-18/41 2012/6/11 4-bit Universal Shift Register ircuit iagram A 3 A 2 A 1 A 0 Function able Mode ontrol Register S 1 S 0 Operation 0 0 No hange 0 1 Shift Right 1 0 Shift Left 1 1 Parallel Load lear lock S 1 S 0 4 1 MUX 3 2 1 0 4 1 MUX 3 2 1 0 4 1 MUX 3 2 1 0 4 1 MUX 3 2 1 0 Serial Input for Shift-right Serial Input for Shift-left I 3 I 2 I 1 I 0 Parallel Inputs
6.3 Ripple ounters P-19/41 2012/6/11 6.1 Registers 6.2 Shift Registers 6.3 Ripple ounters 6.4 Synchronous ounters 6.5 Other ounters 6.6 HL for Registers and ounters
6.3 Ripple ounters P-20/41 2012/6/11 ounters 1. ounter: A register that goes through a prescribed sequence of status upon the application of input pulses is called a counter. 2. he input pulses may be clock pulse or they may originate from some external source and may occur at a fixed interval of time or at random. 3. he sequence of status may follow the binary sequence is called a binary counter. 4. An n-bit binary counter consists of n flip-flop and can count in binary from 0 to 2 n -1.
6.3 Ripple ounters P-21/41 2012/6/11 Ripple ounters vs. Synchronous ounters 1. Ripple ounters: he flip-flop output transition servers as a source for triggering other flip-flops. he inputs of some or all flip-flops are triggered not by the common clock pluses. 2. Synchronous ounters: he input of all flip-flops receive the common clock.
6.3 Ripple ounters P-22/41 2012/6/11 4-Bit Binary Ripple ounters Binary ounter with -FF Binary ounter with -FF ount R A 0 ount R A 0 Ripple Propagation Binary ounter Sequence A 1 A 1 A 3 A 2 A 1 A 0 R R A 2 R R A 2 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 A 3 A 3 Negative Edge rigger R R Reset 1 Reset
ount Sequence 6.3 Ripple ounters P-23/41 2012/6/11 4-Bit Binary Ripple ount-own ounters Binary ounter with -FF Binary ounter with -FF ount R A 0 ount R A 0 Ripple Propagation Binary ounter Sequence A 1 A 1 A 3 A 2 A 1 A 0 R R A 2 R R A 2 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 A 3 A 3 R R Positive Edge rigger Reset 1 Reset
6.3 Ripple ounters P-24/41 2012/6/11 B Ripple ounters State iagram of a ecimal B ounter B ounter Sequence 0000 0001 0010 0011 0100 1001 1000 0111 0110 0101 rigger Higher igit If Q 8 = 1 then Q 2 = 0 2 Q 8 Q 4 Q 2 Q 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 4 If (Q 2 or Q 4 = 0) and Q 1 then Q 8 Remain at 0 If (Q 2 and Q 4 = 1 and Q 1 ) then Q 8 omplement 3 1
6.3 Ripple ounters P-25/41 2012/6/11 ircuit of B Ripple ounters B ounter ount J K Q 1 J K J K Q 2 Q 4 Q 8 Q 4 Q 2 Q 1 B ounter 3 ecimal B ounter Q 8 Q 4 Q 2 Q 1 B ounter Q 8 Q 4 Q 2 Q 1 B ounter 10 2 igit 10 1 igit 10 0 igit J K Q 8 1
6.4 Synchronous ounters P-26/41 2012/6/11 6.1 Registers 6.2 Shift Registers 6.3 Ripple ounters 6.4 Synchronous ounters 6.5 Other ounters 6.6 HL for Registers and ounters
6.4 Synchronous ounters P-27/41 2012/6/11 Review of Ripple and Synchronous ounters 1. Ripple ounters: he flip-flop output transition servers as a source for triggering other flip-flops. he inputs of some or all flip-flops are triggered not by the common clock pluses. 2. Synchronous ounters: he input of all flip-flops receive the common clock.
6.4 Synchronous ounters P-28/41 2012/6/11 State ransition of 4-bit Binary ounters A 3 A 2 A 1 A 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
6.4 Synchronous ounters P-29/41 2012/6/11 ount Enable (E) J K A 0 A 0 and E =1 J K A 1 If (A 0 and E) =1 and lcok hen A 1 = A 1 4-Bit Synchronous Binary ounters J K A 2 A 0 ~A 2 and E =1 J K A 3 If (A 0 ~A 2 and E) =1 and lcok hen A 3 = A 3 o Next Stage lock
ount Sequence 6.4 Synchronous ounters P-30/41 2012/6/11 State ransition of 4-bit Binary own ounters A 3 A 2 A 1 A 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 A 0
6.4 Synchronous ounters P-31/41 2012/6/11 Up own A 0 4-bit Binary Up- own ounters A 1 A 2 Function able Up own Function 0 0 No hange 0 1 own ount 1 0 Up ount 1 1 Up ount A 3 lock
6.4 Synchronous ounters P-32/41 2012/6/11 B ounters Excitation able Q(t) Q(t+1) Present State Next State Output Flip-Flop Inputs Q 8 Q 4 Q 2 Q 1 Q 8 Q 4 Q 2 Q 1 y Q 8 Q 4 Q 2 Q 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 K-Map Q1 = 1 Q2 = Q 8 Q 1 Q4 = Q 2 Q 1 Q8 = Q 8 Q 1 + Q 4 Q 2 Q 1 y = Q 8 Q 1
6.4 Synchronous ounters P-33/41 2012/6/11 ount 4-Bit Binary ounter with Parallel Load Load 1 0 1 I 0 J K A 0 I 1 J K A 1 Function able lear lock Load ount Function I 2 J K A 2 0 X X X lear to 0 1 1 X load Inputs 1 0 1 Up ount 1 0 0 No hange I 3 J K A 3 lear lock arry- Output
6.4 Synchronous ounters P-34/41 2012/6/11 Implementation B ounters Using ounters with Parallel Load ount to 9 Load 0 After ount to 9 lear to 0 A 3 A 2 A 1 A 0 A 3 A 2 A 1 A 0 Load ounter with Parallel Load ount=1 lear=1 lock lear ounter with Parallel Load ount=1 Load=0 lock Inputs=0 Input have no effect
6.5 Other ounters P-35/41 2012/6/11 6.1 Registers 6.2 Shift Registers 6.3 Ripple ounters 6.4 Synchronous ounters 6.5 Other ounters 6.6 HL for Registers and ounters
6.5 Other ounters P-36/41 2012/6/11 ounter with Unused States Sate able Present Next State Stare Flip-Flop Inputs A B A B J A K A J B K B J K 0 0 0 0 0 1 0 X 0 X 1 X 0 0 1 0 1 0 0 X 1 X X 1 0 1 0 1 0 0 1 X X 1 0 X 1 0 0 1 0 1 X 0 0 X 1 X 1 0 1 1 1 0 X 0 1 X X 1 1 1 0 0 0 0 X 1 X 1 0 X Boolean Function J A =B K A =B J B = K B =1 J =B K =1
6.5 Other ounters P-37/41 2012/6/11 omplement omplement ounter with Unused States (ontinued) 1 1 1 1 J A K 1 J B K 0 Unused State 111 000 001 110 010 101 1 0 Reset 1 J K 1 100 011 lock Unused State
6.5 Other ounters P-38/41 2012/6/11 4-Bit Ring ounter iming Sequence Shift Right 0 1 2 3 lock Ring ounter with Initial Value = 0 0 0 1 2 3 1 2 2X4 ecoder 3 ount Enable 2-Bit ounter Ring ounter Implemented by ecoder
6.5 Other ounters P-39/41 2012/6/11 4-Bit Johnson ounter: k-bit ounter with 2k states 4-Stage Switch-ail Ring ounter A B E E lock ount Sequence and Required ecoding Sequence Flip-Flop Outputs AN gate required Number A B E for output 1 0 0 0 0 A E 2 1 0 0 0 A B 3 1 1 0 0 B 4 1 1 1 0 E 5 1 1 1 1 A E 6 0 1 1 1 A B 7 0 0 1 1 B 8 0 0 0 1 E
6.6 HL for Registers and ounters P-40/41 2012/6/11 6.1 Registers 6.2 Shift Registers 6.3 Ripple ounters 6.4 Synchronous ounters 6.5 Other ounters 6.6 HL for Registers and ounters
6.6 HL for Registers and ounters P-41/41 2012/6/11 Referred to A