An interfacial investigation of high-dielectric constant material hafnium oxide on Si substrate B

Similar documents
Quantum Mechanical Simulation for Ultra-thin High-k Gate Dielectrics Metal Oxide Semiconductor Field Effect Transistors

Characterization of Charge Trapping and Dielectric Breakdown of HfAlOx/SiON Dielectric Gate Stack

Effects of plasma treatment on the precipitation of fluorine-doped silicon oxide

Thin Solid Films 529 (2013) Contents lists available at SciVerse ScienceDirect. Thin Solid Films

Electrical measurements of voltage stressed Al 2 O 3 /GaAs MOSFET

Frequency dispersion effect and parameters. extraction method for novel HfO 2 as gate dielectric

Low Frequency Noise in MoS 2 Negative Capacitance Field-effect Transistor

J. Price, 1,2 Y. Q. An, 1 M. C. Downer 1 1 The university of Texas at Austin, Department of Physics, Austin, TX

Traps in MOCVD n-gan Studied by Deep Level Transient Spectroscopy and Minority Carrier Transient Spectroscopy

1658 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 7, JULY 2003

Comparative studies of Ge and Si p-channel metal oxide semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

A comparison study on hydrogen sensing performance of Pt/MoO3 nanoplatelets coated with a thin layer of Ta2O5 or La2O3

Characteristics and parameter extraction for NiGe/n-type Ge Schottky diode with variable annealing temperatures

Electronic structure of transition metal high-k dielectrics: interfacial band offset energies for microelectronic devices

Supporting information

Effective Capacitance Enhancement Methods for 90-nm DRAM Capacitors

Leakage Mechanisms. Thin films, fully depleted. Thicker films of interest for higher voltage applications. NC State

Enhancing the Performance of Organic Thin-Film Transistor using a Buffer Layer

Large Storage Window in a-sinx/nc-si/a-sinx Sandwiched Structure

Control of Flat Band Voltage by Partial Incorporation of La 2 O 3 or Sc 2 O 3 into HfO 2 in Metal/HfO 2 /SiO 2 /Si MOS Capacitors

(a) (b) Supplementary Figure 1. (a) (b) (a) Supplementary Figure 2. (a) (b) (c) (d) (e)

Song and Feng Pan b) * Laboratory of Advanced Materials (MOE), School of Materials Science and Engineering,

Stretching the Barriers An analysis of MOSFET Scaling. Presenters (in order) Zeinab Mousavi Stephanie Teich-McGoldrick Aseem Jain Jaspreet Wadhwa

CONSTANT CURRENT STRESS OF ULTRATHIN GATE DIELECTRICS

Subthreshold and scaling of PtSi Schottky barrier MOSFETs

DISTRIBUTION OF POTENTIAL BARRIER HEIGHT LOCAL VALUES AT Al-SiO 2 AND Si-SiO 2 INTERFACES OF THE METAL-OXIDE-SEMICONDUCTOR (MOS) STRUCTURES

Fabrication and Characterization of Al/Al2O3/p-Si MOS Capacitors

A Bottom-gate Depletion-mode Nanowire Field Effect Transistor (NWFET) Model Including a Schottky Diode Model

ECE 340 Lecture 39 : MOS Capacitor II

Influence of electrode materials on CeO x based resistive switching

EECS130 Integrated Circuit Devices

23.0 Review Introduction

DEPOSITION OF THIN TiO 2 FILMS BY DC MAGNETRON SPUTTERING METHOD

Formation mechanism and Coulomb blockade effect in self-assembled gold quantum dots

CVD-3 LFSIN SiN x Process

Department of Electronic Engineering, Chienkuo Technology University, No. 1, Chieh Shou N. Rd., Changhua City, 500 Taiwan, R.O.C.

Size-dependent Metal-insulator Transition Random Materials Crystalline & Amorphous Purely Electronic Switching

Temperature Dependent Current-voltage Characteristics of P- type Crystalline Silicon Solar Cells Fabricated Using Screenprinting

Solid-State Electronics

A final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room).

CVD-3 MFSIN-HU-2 SiN x Mixed Frequency Process

Solid-State Electronics

M R S Internet Journal of Nitride Semiconductor Research

Theoretical Study on Graphene Silicon Heterojunction Solar Cell

Improved Interfacial and Electrical Properties of GaSb Metal Oxide

CVD-3 MFSIN-HU-1 SiN x Mixed Frequency Process

Moores Law for DRAM. 2x increase in capacity every 18 months 2006: 4GB

Metal Semiconductor Contacts

Planar Organic Photovoltaic Device. Saiful I. Khondaker

Review Energy Bands Carrier Density & Mobility Carrier Transport Generation and Recombination

C-V and G-V Measurements Showing Single Electron Trapping in Nanocrystalline Silicon Dot Embedded in MOS Memory Structure

Nanostrukturphysik (Nanostructure Physics)

Multiple Gate CMOS and Beyond

Normally-Off GaN Field Effect Power Transistors: Device Design and Process Technology Development

CVD-3 SIO-HU SiO 2 Process

Nanofabrication Lab Process Development for High-k Dielectrics

Fermi Level Pinning at Electrical Metal Contacts. of Monolayer Molybdenum Dichalcogenides

Scaling Issues in Planar FET: Dual Gate FET and FinFETs

Solid-State Electronics

A New High Voltage 4H-SiC Lateral Dual Sidewall Schottky (LDSS) Rectifier: Theoretical Investigation and Analysis

An Analytical Model for a Gate-Induced-Drain-Leakage Current in a Buried-Channel PMOSFET

MENA9510 characterization course: Capacitance-voltage (CV) measurements

High Performance, Low Operating Voltage n-type Organic Field Effect Transistor Based on Inorganic-Organic Bilayer Dielectric System

TRANSVERSE SPIN TRANSPORT IN GRAPHENE

Al/Ti/4H SiC Schottky barrier diodes with inhomogeneous barrier heights

Supporting Information for: Sustained sub-60 mv/decade switching via the negative capacitance effect in MoS 2 transistors

Atmospheric pressure Plasma Enhanced CVD for large area deposition of TiO 2-x electron transport layers for PV. Heather M. Yates

Integrating MEMS Electro-Static Driven Micro-Probe and Laser Doppler Vibrometer for Non-Contact Vibration Mode SPM System Design

SUPPLEMENTARY INFORMATION

Determination of interface state density in high-k dielectric-silicon system from conductance-frequency measurements

VSP A gate stack analyzer

Schottky Rectifiers Zheng Yang (ERF 3017,

Bipolar resistive switching in amorphous titanium oxide thin films

Current mechanisms Exam January 27, 2012

Effects of Antimony Near SiO 2 /SiC Interfaces

ALD high-k and higher-k integration on GaAs

Supporting Online Material for

Quantification of Trap State Densities at High-k/III-V Interfaces

Removal of Cu Impurities on a Si Substrate by Using (H 2 O 2 +HF) and (UV/O 3 +HF)

Optimization of the Dielectric Constant of a Blocking Dielectric in the Nonvolatile Memory Based on Silicon Nitride

Electrostatics of Nanowire Transistors

SUPPLEMENTARY INFORMATION

MSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University

Threshold voltage shift of heteronanocrystal floating gate flash memory

META-STABILITY EFFECTS IN ORGANIC BASED TRANSISTORS

Black phosphorus: A new bandgap tuning knob

Gate Carrier Injection and NC-Non- Volatile Memories

Energy position of the active near-interface traps in metal oxide semiconductor field-effect transistors on 4H SiC

LaTiON/LaON as band-engineered charge-trapping layer for nonvolatile memory applications

Role of Schottky-ohmic separation length on dc properties of Schottky diode

R&D Issues for High-k Gate Dielectrics

Performance Analysis of Ultra-Scaled InAs HEMTs

Supplementary Figure 1 shows overall fabrication process and detailed illustrations are given

Lecture 9: Metal-semiconductor junctions

CVD: General considerations.

Defect and Temperature Dependence of Tunneling in InAs/GaSb Heterojunctions

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

L ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling

Low Leakage Current Transport and High Breakdown Strength of Pulsed Laser Deposited HfO 2 /SiC MIS Device Structures

Steep-slope WSe 2 Negative Capacitance Field-effect Transistor

Transcription:

Thin Solid Films 488 (2005) 167 172 www.elsevier.com/locate/tsf An interfacial investigation of high-dielectric constant material hafnium oxide on Si substrate B S.C. Chen a, T, J.C. Lou a, C.H. Chien b, P.T. Liu b, T.C. Chang c,d a Institute of Electronics, National Chiao Tung University, 1001 Ta-hsueh Rd., Hsin Chu, Taiwan, ROC b National Nano Device Laboratory, 1001-1 Ta-hsueh Rd., Hsin Chu, Taiwan, ROC c Department of Physics and Institute of Electro-Optical Engineering, National Sun Yat-Sen University, 70 Lien-hai Rd., Kaohsiung, Taiwan, ROC d Center for Nanoscience and Nanotechnology, National Sun Yat-Sen University, Kaohsiung, Taiwan, R.O.C. Available online 2 March 2005 Abstract In this study, the hump in the capacitance voltage (C V) curves, variation of leakage current, interfacial layer increase, and electron trapping in non-surface treated hafnium oxide (HfO 2 ) samples were observed and investigated. From the results of the investigation, it was found that both rapid thermal oxidation and NH 3 surface treatments improved the C V curves. In addition, it was observed that samples treated with ammonia exhibited a lower leakage current when compared with the others. From the results of the dielectric leakage current study, a severe electron trapping effect was exhibited under higher electric field stress. Finally, the conduction mechanism in the HfO 2 thin film was dominated by Frenkel Poole emission in a high electric field. D 2005 Elsevier B.V. All rights reserved. Keywords: Dielectrics; Electrical properties and measurements; Surface and interface state; Transmission electron microscopy (TEM) 1. Introduction The continuous shrinkage in Metal-Oxide-Semiconductor Field Effect Transistor dimensions is accompanied by a scaling of gate oxide thickness. It is well known that the scaling of conventional SiO 2 is approaching the predicted limit due to large direct tunneling leakage current, thereby presenting a fundamental challenge to continual scaling. Therefore, an alternative gate dielectric material is needed to replace SiO 2. High dielectric constant (high-k) materials are the potential candidates because a thicker film is utilized to reduce the leakage current while maintaining the same gate capacitance. Such a suitable high-k material should have a wide band gap, high barrier height for both electrons and holes, and good thermal stability. As many investigations of high-k materials have reported [1], hafnium oxide (HfO 2 )is B This paper was presented at the ICMCTF 2004 conference. T Corresponding author. Tel.: +886 3 5712121x54221; fax: +886 3 5724361. E-mail address: scchen.ee92g@nctu.edu.tw (S.C. Chen). considered as one of the candidates with the most potential. In this experiment, Metal Organic Chemical Vapor Deposition (MOCVD) technology is used to deposit an HfO 2 film. Two forms of surface treatment, Rapid Thermal Oxidation and NH 3 surface treatment, were studied for their effects on the electrical characteristics of HfO 2 thin films. Planar Metal-Insulator-Semiconductor capacitors were utilized to realize the measurements of the electrical characteristics such as leakage current, electron trapping effect, and the extraction of the conduction mechanism in HfO 2 thin film. 2. Experimental details To begin, the p-type Si wafers were cleaned with standard RCA clean. The samples were divided into two groups. One group was distinguished as being without any surface treatment before HfO 2 deposition, while the other was classified as having undergone surface treatment before HfO 2 deposition. The two surface treatments used for this 0040-6090/$ - see front matter D 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2005.01.023

168 S.C. Chen et al. / Thin Solid Films 488 (2005) 167 172 (a) Top Electrode ( Pt ) 3. Results and discussions 3.1. Thermal stability HfO 2 Si-Substrate Backside Electrode ( Al ) (b) Top Electrode ( Pt ) HfO 2 SiO 2 or SiN X Si-Substrate Backside Electrode ( Al ) Fig. 1. MIS capacitor structure in this study: (a) Direct HfO 2 deposition without surface treatment, and (b) RTO and NH 3 surface treatment prior to the HfO 2 deposition. An interfacial layer grew after these surface treatments. study include rapid thermal oxidation (RTO) and ammonia (NH 3 ) surface treatment. RTO is intended to deposit an ultra thin SiO 2 layer (~10 2, measured by an optical measurement system-ellipsometer ) at 700 8C followed by annealing at 1100 8C using a rapid thermal process system. The NH 3 - treatment was performed in a high temperature furnace at 800 8C for 1 h. After the NH 3 -treatment, a SiN X layer (~10 2) was deposited. A MOCVD system with a gas flow of O 2 / N 2 O at 250/250 sccm and a pressure of 5 mbar was used to deposit the HfO 2 film at 400 8C. The thickness of the HfO 2 films were 100 2 and 50 2 for the non-surface treated and surface treated samples, respectively. After HfO 2 deposition, a high temperature post deposition annealing was performed at 600, 800, and 1000 8C, for 30 s, respectively. The gate electrode and the backside contact were created by a Physical Vapor Deposition system. The dual electron gun system was used to deposit the Pt film (1000 2) as the top gate electrode, and the thermal evaporation system was employed to deposit the Al film (5000 2) as the backside contact. The MIS capacitor structure used in this study is shown in Fig. 1. The capacitance voltage (C V) and current density electric field (J E) characteristics were investigated by HP-4284 and HP- 4156C systems. Transmission electron microscopy (TEM) was used to determine the exact thickness, and to identify the interface between HfO 2 and Si substrate and the interface between HfO 2 and gate electrode. After the deposition of high-k materials, other high temperature processes, such as source/drain activation, are sometimes performed during very large scale industrial fabrication of integrated circuits. Such high-temperature treatments are likely to change the morphology and properties of high-k thin films [2]. Fig. 2 shows the capacitance equivalent thickness (CET) of HfO 2 samples without surface treatment after various post deposition annealing (PDA) at 600, 800, and 1000 8C. The CET is almost the same as the as-deposited samples after post deposition annealing at 800 8C. However, the CET increases drastically after 1000 8C PDA. This is due to the significant increase in the thickness of the interfacial layer between the HfO 2 and the Si substrate. The exact composition of such interfacial layer is not yet clear, but it is believed that the dielectric constant of the interfacial layer is much lower than that of HfO 2. Therefore, the presence of the additional interfacial layer would significantly increase the CET and thus reducing the effective dielectric constant. Fig. 3 exhibits the current density electric field (J E) curves of the HfO 2 samples at various PDA temperatures. The electric field is defined as the gate bias divided by the CET. For the as-deposited samples with 600 and 800 8C PDA, a higher annealing temperature leads to higher leakage current. Since a higher PDA temperature could possibly cause the dielectric materials to crystallize, it contributes to a larger leakage current. The capacitance of PDA 600 and 800 8C at strong accumulation are 1.05 AF/ cm 2 and 1.11 AF/cm 2, respectively. The capacitance did not decrease significantly at 800 8C PDA. Therefore, the effect of dielectric crystallization is much more obvious than the growing of a thicker interfacial layer. For the 1000 8C- CET (Angstrom) 50 48 46 44 42 40 38 36 34 32 30 As-deposited 600 800 1000 PDA Temperature ( C) Fig. 2. CET of HfO 2 samples after post deposition annealing temperatures of 600, 800, and 1000 8C, respectively.

S.C. Chen et al. / Thin Solid Films 488 (2005) 167 172 169 electrons, resulting in the electron trapping effect that was observed in the as-deposited HfO 2 samples. The asdeposited HfO 2 thin film samples without any PDA treatment have considerable initial traps. Therefore, electron trapping becomes significant after the gate injection stress. Fig. 8 shows the leakage current of the PDA treated HfO 2 samples after a gate injection stress. The 600, 800, and 1000 8C PDA all show nearly identical results. Due to high temperature annealing reducing the defects in the HfO 2 thin film, electron trapping is eliminated in high temperature Fig. 3. J E curves of HfO 2 samples with various PDA temperatures. annealed sample, the thicker interfacial layer helps resist large leakage current. Fig. 4(a), (b), and (c) show the influence of PDA temperatures on HfO 2 in TEM analyses. In Fig. 4 (c), an obvious change of growth in the interfacial layer can be observed at 1000 8C PDA. The increased thickness is about 30 2, which results in the lower leakage current in the HfO 2 thin film after the 1000 8C PDA. 3.2. Effects of surface treatments Fig. 5 shows the comparison of the C V characteristics between surface-treated and non-surface-treated samples. The hump of the C V curve can be observed in the samples without surface treatment. Both RTO and NH 3 surface treatments significantly reduced the C V hump that was observed in the non-surface-treated sample. It was observed that both surface treatments changed the interfacial layer at the dielectric/si interface, and improved the dielectric properties [3]. InFig. 6, the leakage currents of the samples with various surface treatments are shown. The NH 3 surface treatment not only improved the C V curves, but also reduces the leakage current. This is due to the introduction of nitrogen which actually increases the dielectric constant of the interfacial layer in the NH 3 treated samples. After the HfO 2 deposition at the same physical thickness (50 2), the capacitance of RTO and NH 3 surface treatment at strong accumulation are measured at 1.39 AF/cm 2 and 1.60 AF/ cm 2, respectively. The results indicate that the higher capacitance of the NH 3 treated samples is due to the increasing dielectric constant of the interfacial layer. Moreover, the NH 3 pre-treatment provides strong Si N bonds and sufficient barrier height for the interfacial layer to suppress the leakage current [3,4]. 3.3. Electron trapping effect Fig. 7 shows the leakage current of the as-deposited HfO 2 film after a gate injection stress, after which, a reduction of leakage current became evident. This is due to the fact that electrons were captured in the HfO 2 film, and it is these captured electrons that resisted subsequent injected Fig. 4. Transmission electron microscopy (TEM) of HfO 2 samples with various PDA temperatures: (a) As-deposited HfO 2 ; (b) HfO 2 with 600 8C PDA; and (c) HfO 2 with 1000 8C PDA.

170 S.C. Chen et al. / Thin Solid Films 488 (2005) 167 172 Capacitance (µf/cm 2 ) 1.5 1.0 0.5 0.0 HfO 2 without surface treatment Rapid thermal oxidation NH 3 surface treatment annealed samples. Fig. 9(a) shows the comparison of the electron trapping effects under high electric field stress. Electron trapping effects were observed in all samples, but a more extensive electron trapping effect was observed in the HfO 2 samples without surface treatment. In Fig. 9(b), the change in the leakage current after a high electric field stress is demonstrated. The electron trapping effect in RTO or NH 3 treated samples was not as severe when compared to samples without surface treatment. 3.4. Carrier conduction mechanism CET : 2.65nm CET : 2.80nm CET : 2.43nm -0.5-3 -2-1 0 1 2 Gate Bias ( V ) Fig. 5. C V curves of RTO and NH 3 surface treatment. Among electrical characteristics, the carrier conduction mechanism in the insulator was worthy enough to be measured. Typically, two possible mechanisms are explored in the metal insulator interface: Schottky emission and Frenkel Poole emission [5]. The Schottky Richardson emission, generated by the thermionic effect, is caused by electron transport across the potential energy barrier via 10-9 field-assisted lowering at a metal insulator interface. The leakage current equation is as follows: J ¼ A T T 2 exp b se 1=2 / s ð1þ where b s =(e 3 /4pe 0 e) 1/2, A * is the effective Richardson constant, and / s is the contact potential barrier. The slope can be extracted in ln J vs. E 1/2 plots. ln J ¼ b pffiffiffi s E þ ln A T T 2 / s slope ¼ b s : As-deposited HfO 2 CET : 3.22nm Electron Trapping - 1 st Leakage current measurement - 2 nd Leakage current measurement -4-3 -2-1 0 Fig. 7. Leakage current after gate injection stress of as-deposited HfO 2 samples. The electron trapping effect can be observed. ð2þ The Frenkel Poole emission is due to field-enhanced thermal excitation of trapped electrons in the insulator into the conduction band. The leakage current equation is as follows: J ¼ J 0 exp b FPE 1=2 / FP ð3þ where J 0 =r 0 E is the low-field current density, r 0 is the low-field conductivity, b FP =(e 3 /4pe 0 e) 1/2, e is the elec- 10-1 10-3 Leakage Current under Gate Injection HfO 2 (6.5nm) (CET:2.65nm) HfO 2 (10nm) (CET:3.35nm) HfO 2 (5nm) RTO- treatment (CET:2.80nm) HfO 2 (5nm) NH 3 - treatment (CET:2.43nm) -2.0-1.5-1.0-0.5 0.0 Fig. 6. J E curves of RTO and NH 3 surface treatment. 10-2 10-3 10-9 10-10 800 C PDA CET~31Å 600 C PDÅ CET~33Å 1000 C PDA CET~48Å Open - 1 st Leakage current measurement Closed - 2 nd Leakage current measurement -4-3 -2-1 0 Fig. 8. Leakage current after gate injection stress of HfO 2 with various PDA temperatures. Electron trapping was eliminated after annealing.

S.C. Chen et al. / Thin Solid Films 488 (2005) 167 172 171 (a) (b) Normalized J ( (J - Jo)/Jo @ -7MV/cm) tronic charge, e 0 is the permittivity of free space, e is the high frequency relative dielectric constant, T is the absolute temperature, E is the applied electric field, K B ln J 10-1 10-2 10-3 10-9 -4-6 -8-10 1.2 1 0.8 0.6 0.4 0.2 0 0.98052729 Open : Before Stress Closed : After Stress Stress : 13.33 (MV/CM) : 50 sec : without surface treatment (Group A) : R apid thermal oxidation (Group B) : NH 3 surface treatment (Group C) -8-6 -4-2 0 0.75150319 As-deposited HfO 2 under Gate Injection Frenkel-Poole emission dominated -12 RT -14 50 C 75 C -16 100 C 125 C -18 Schottky emission dominated 150 C Fitting Line -20 0.50 0.75 1.00 1.25 1.50 E 1/2 ( MV/cm ) 1/2 0.81510486 Group A Group B Group C Surface Treatment Fig. 9. (a) The comparison of the electron trapping effect under high electric field stress. Severe electron trapping was observed in HfO 2 samples without surface treatment. (b) The change of the leakage current after the high electric field stress. (Group A: without surface treatment, Group B: RTO, Group C: NH 3 surface treatment. J and J 0 are the leakage current before and after electric stress, respectively.) Fig. 10. Conduction mechanism fitting of as-deposited HfO 2 samples under gate injection. ln J -8-10 -12-14 -16-18 is the Boltzmann constant, and / FP is the contact potential barrier. The slope can be extracted in ln J vs. E 1/2 plots. lnj ¼ b FP pffiffiffi E slope ¼ b FP : As-deposited HfO 2 under Substrate Injection Frenkel-Poole emission dominated Schottky emission dominated -20 0.50 0.75 1.00 1.25 1.50 E 1/2 ( MV/cm ) 1/2 þ ln ð J0 Þ / FP RT 50 C 75 C 100 C 125 C 150 C Fitting Line Fig. 11. Conduction mechanism fitting of as-deposited HfO 2 samples under substrate injection. ð4þ From the above equations, the leakage current behaviors of insulating films can be investigated further by the current density ( J ) electric field (E) characteristics, such as ln J vs. E 1/2 plots. It is found that the leakage current density is linearly related to the square root of the applied electric field. The linear variations of the current correspond either to the Schottky emission or to the Frenkel Poole conduction mechanism [6]. For trap states with coulomb potentials, the expression is virtually identical to that of the Schottky emission. The barrier height, however, is the depth of the trap potential well, and the quantity b FP is larger than in the case of the Schottky emission by a factor of 2. Distinguishing between the two processes can be done by comparing the theoretical value of b with the obtained experimental values through the calculating of the slope in the ln J-E 1/2 curves. The dielectric constant of HfO 2 is 13 extracted by C V measurement, and the theoretical b values are 3.3610 23 for the Frenkel Poole and 1.6810 23 for the b at room temperature (RT) : Table 1 b value extracted from this experiment Gate injection Substrate injection b at room temperature (RT) : 5.5810 23 1.6910 23 b at 50 8C : 5.7110 23 b at 50 8C : 2.8010 23 b at 75 8C : 4.8610 23 b at 75 8C : 2.2210 23 b at 100 8C : 4.1210 23 b at 100 8C : 2.8610 23 b at 125 8C : 3.5410 23 b at 125 8C : 2.6710 23 b at 150 8C : 3.3410 23 b at 150 8C : 3.5710 23

172 S.C. Chen et al. / Thin Solid Films 488 (2005) 167 172 Gate Schottky emission. Figs. 10 and 11 show the curve-fitting results of the As-deposit HfO 2 samples under gate and substrate injection. From the slopes of the fitted curves, the experimental b value was extracted and is shown in Table 1. In the cases of gate and substrate injection, the conduction mechanism in as-deposited HfO 2 thin film is dominated by the Schottky emission in a lower electric field, and by the Frenkel Poole emission in a higher electric field. When the samples are under a higher electric field, the tunneling effect becomes obvious. [7,8] This tunneling effect enhances the Frenkel Poole emission. A schematic band diagram of the Frenkel Poole emission is shown in Fig. 12. Therefore, it can be concluded that the conduction mechanism in a higher electric field is evidently dominated by the Frenkel Poole emission. In addition, the interfacial layer grew after the PDA treatments, as shown in Fig. 4. The interface changed to the SiO 2 -like or silicate-like layer [9,10], and has a sufficient barrier height to suppress the Schottky emission, resulting in the conduction mechanism of the HfO 2 thin film being dominated by the Frenkel Poole emission in a high electric field. 4. Conclusions In closing, the thermal stability of the high dielectric constant material HfO 2, deposited by MOCVD was investigated under various high temperature PDA treatments. It was found that a higher annealing temperature leads to Φ B Dielectrics Si-substrate Fig. 12. Schematic band diagram of Frenkel Poole emission. higher leakage current. Since the higher PDA temperature makes the dielectric materials crystallize, it contributes to a larger leakage current. For the 1000 8C-annealed sample, the thicker interfacial layer helps resist a large leakage current, and consequently reduces it. The NH 3 surface treatment not only improved the C V curves, but also reduced the leakage current. The NH 3 pre-treatment provides strong Si N bonds and a sufficient barrier height for the interfacial layer to suppress the leakage current. The as-deposited HfO 2 thin film without any PDA treatment has considerable initial traps and a severe electron trapping effect. This electron trapping effect can be suppressed by high temperature annealing. Rapid thermal oxidation and NH 3 surface treatments can also improve the electron trapping effect in the HfO 2 film. It was also found that the conduction mechanism in the HfO 2 thin film is dominated by the Frenkel Poole emission in a high electric field. Acknowledgement This work was performed at National Nano Device Laboratory and was financially supported by National Nano Device Laboratory under Contract No. 92A0500001 and by the National Science Council of Taiwan, ROC under Contract Nos. NSC92-2112-M-110-020 and NSC92-2215- E-110-006. References [1] G.D. Wilk, R.M. Wallace, J.M. Anthony, J. Appl. Phys. 89 (2001) 10. [2] M.-Y. Ho, G.D. Wilk, P.M. Voyles, J. Appl. Phys. 93 (2003) 3. [3] S. Gopalan, R. Choi, K. Onishi, R. Nieh, C. Kang, H. Cho, S. Krishnan, J. Lee, 60th Device Research Conference at the University of California, Santa Barbara, June 24 26, 2002, p. 195. [4] R. Choi, C.S. Kang, B.H. Lee, K. Onishi, R. Nieh, S. Gopalan, E. Dharmarajan, J.C. Lee, Symp. VLSI Tech. Dig. (2001) 15. [5] S.M. Sze, Physics of semiconductor devices, Chap. 7, Wiley, New York, 1981, p. 402. [6] P.T. Liu, T.C. Chang, Y.L. Yang, Y.F. Cheng, S.M. Sze, IEEE Trans. Electron Devices 47 (2000) 1733. [7] M. Lax, Phys. Rev. 119 (1960) 1502. [8] T.H. Ning, J. Appl. Phys. 47 (1976) 3203. [9] A.R. Chowdhuri, C.G. Takoudis, R.F. Klie, N.D. Browning, Appl. Phys. Lett. 80 (2002) 4241. [10] T.M. Klein, D. Niu, W.S. Epling, W. Li, D.M. Maher, Appl. Phys. Lett. 75 (1999) 4001.