FM Hepburn Intel iscrete GFX VER : POWER /TT ONNETOR PG R-SOIMM PG, R-SOIMM PG, SYSTEM RESET IRUIT TT HRGER RUN POWER SW +.V_SUS/+V_SUS +V/+.V/+.V MHZ R II MHZ R II ST-O PG PG PG PG ST Merom or Penryn ( Micro-FPG) restline MI interface ufg PG, MHz FS PG,,,,, FN & THERML SMS PG PIEx GR x (M bits) PG US. x PIEx LOK SLGSPV (QFN-) PG TI MS POWER PI EXPRESS GFX REGULTOR +.V_RUN/+.V_VP REGULTOR +.V_SUS/+.V_RUN /+.V_R_VTT PG,,,, US conn x LVS HMI VG PG PG PG PU VR / +.V_LW/+V_LW/ +V_LW VG ore Panel onnector HMI ONN. RT ONN. LN MM PG PG PG PG PG PG PG RJ/Magnetics PG UIO/MP ST /H PG udio udio SPK conn Jacks x PG PG ST-H PG amera + -MI PG USER INTERFE PG ST IH US. SPI FLSH Mbyts LP K ITE PG PG IH-M G X PS/ Touchpad PG PG,,, IR TSOPTR PG Keyboard PG PIEx US. PIEx US. PIEx US. US. iometric PG MHz PI -in- ard Reader R PG EXPRESS-R R PG MINI-R WLN MINI-R WWN MINI-R WPN ONN. PG PG PG ard Reader ONN. PG QUNT OMPUTER Schematic lock iagram PG Size ocument Number Rev FM ate: Wednesday, November, Sheet of
Table of ontents PGE ESRIPTION Schematic lock iagram Front Page - Merom - restline - IHM - RII SO-IMM(P) lock Generator - MS LNK PGE LNK PGE L ONN / HMI ONN RT ONN /PI IEEE Express/ard Reader SIO (ITE) FLSH / RT MINI-ard (WPN, WWN) MINI-ard (WLN) US ST (H & _ROM) TP / KEYOR SWITH / /LE FN / THERML zelia OE UIO ONN LN (RTL/) LN RJ- / TRNSFORM System Reset ircuit lank Page hanger (MX) lank Page.VP &.VRUN.VSUS &.VTT VG_M PU_ISL (PHSE) MX (+V,.V) Run Power Switch in & att & SREW EMI P SMUS LOK Power lock iagram POWER PLNE +PWR_SR +RT_ELL +.V_LW +V_LW +V_LW +.V_LN +V_SUS +.V_SUS +.V_SUS +.V_R_VTT +V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_LOM +.V_GFX_PIE +.V_VP +V_ORE +LV +V_MO +V_H VOLTGE V~+V +.V~+.V +.V +V +V +.V +V +.V +.V +.V +V +.V +.V +.V +.V +.V +.V~+.V +.V +V +V PGE,,,,,,,,,,,,, Power States,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ESRIPTION MIN POWER RT POWER L/HRGE POWER LRGE POWER LN POWER SLP_S# TRL POWER SLP_S# TRL POWER SOIMM POWER SOIMM POWER,,,,,,,,, SLP_S# TRL POWER,,,,,,,,,,,,,,,,,,,,,,,,,, SLP_S# TRL POWER,,,,,, SVO POWER, GN PLNE PGE ESRIPTION GN GN_.V GN_/ GN_ GN_R GN_ISL LISTOG/IH POWER LISTOG/IH POWER VG POWER PU ORE POWER L Power Module Power H Power ONTROL SIGNL LWON LWON +V_LW UX_ON SUS_ON.V_SUS_ON R_ON.V_R_VTT_ON RUN_ON.V_RUN_ON RUN_ON.V_RUN_ON.V_RUN_ON RUN_ON +.V,,,,,,,,, PU/LISTOG/IH POWER.V_RUN_ON IMVP_VR_ON LV_TST_EN & ENV MO_EN# H_EN# TIVE IN S~S S~S S~S S~S S~S GN LL QUNT OMPUTER Index & Power Status Size ocument Number Rev FM ate: Wednesday, November, Sheet of
H_#[..] H_ST# H_REQ#[..] H_#[..] H_ST# H_M# H_FERR# H_IGNNE# H_STPLK# H_INTR H_NMI H_SMI# ITP_TI ITP_TMS ITP_TK ITP_TO ITP_TRST# H_RESET# ITP_TK +.V_VP LK_ITP_LK# LK_ITP_LK H_#[..] H_REQ#[..] H_#[..] ITP_TK ITP_TRST# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_REQ# H_REQ# H_REQ# H_REQ# H_REQ# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# Populate ITPFlex for bringup R /F R /F R R */F_N R /F U J []# S# H L []# NR# E L []# PRI# G K []# M []# EFER# H N []# RY# F J []# SY# E N []# P []# R# F P []# L []# IERR# P []# INIT# P []# R []# LOK# H M ST[]# RESET# K REQ[]# RS[]# F H REQ[]# RS[]# F K REQ[]# RS[]# G J REQ[]# TRY# G L REQ[]# HIT# G Y []# HITM# E U []# R []# PM[]# W []# PM[]# U []# PM[]# Y []# PM[]# U []# PRY# R []# PREQ# T []# TK T []# TI W []# TO W []# TMS Y []# TRST# U []# R# V []# W []# []# THERML []# []# PROHOT# V ST[]# THERM THERM M# FERR# IGNNE# THERMTRIP# R JITP IH STPLK# LINT LINT SMI# M RSV[] N RSV[] T RSV[] V RSV[] RSV[] RSV[] RSV[] RSV[] RSV[] F RSV[] TI TMS R *_N TK TO TRST# - R *./F_N RESET# FO LKN LKP GN GN GN GN GN GN R GROUP R GROUP RESERVE ONTROL XP/ITP SIGNLS H LK LK[] LK[] *ITPFlex_N R H_IERR# +.V_VP H_INIT# H_LOK# R ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_TK ITP_TI ITP_TO ITP_TMS ITP_TRST# ITP_RESET# H_PROHOT# H_THERM H_THERM H_THERM R H_THERM +.V_VP ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# *P_N H_S# H_NR# H_PRI# H_EFER# H_RY# H_SY# H_R# R H_RESET# H_RS# H_RS# H_RS# H_TRY# H_HIT# H_HITM# H_THERM R ITP_RESET# ITP_RESET# +.V_VP T H_THERM H_THERM +.V_VP LK_PU_LK LK_PU_LK# Layout Note: Place couple.uf ecoupling caps with in." ITP connector. VTT VTT VTP R# # PM# PM# PM# PM# PM# PM# N N GN_ GN_ R *.U_N *.U_N +.V_SUS Layout Note: Place R,R,R,R, R, R close to PU +.V_VP H_PROHOT# H_THERM R /F Q MMST--F +.V_VP +.V_VP +.V_RUN Layout Note: Place R close to PU. H_RESET# Layout Note: Place voltage divider within." of GTLREF pin Q R K/F R K/F H_#[..] H_STN# H_STP# H_INV# H_#[..] H_STN# H_STP# H_INV#, PU_MH_SEL, PU_MH_SEL, PU_MH_SEL +.V_LW *NW--F_N R M.U Voltage Level shift R *.K_N PU_PROHOT# Q NW--F ITP disable guidelines H_THERMTRIP#. H_#[..] H_#[..] H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# U E []# F []# E []# G []# F []# G []# E []# E []# K []# G []# J []# J []# H []# F []# K []# H []# J STN[]# H STP[]# H INV[]# N []# K []# P []# R []# L []# M []# L []# M []# P []# P []# P []# T []# R []# L []# T []# N []# L STN[]# M STP[]# N INV[]# V_PU_GTLREF PU_TEST GTLREF PU_TEST TEST PU_TEST TEST PU_TEST TEST F PU_TEST TEST F PU_TEST TEST TEST SEL[] SEL[] SEL[] - R *K/F_N PU_TEST R *K/F_N PU_TEST *.U_N PU_TEST R *_N PU_TEST Place close to the PU_TEST pin. Make sure PU_TEST routing is reference to GN and away from other noisy signal. Signal Resistor Value onnect To Resistor Placement TI ohm +/- % VTT Within." of the ITP TMS TRST# TK TO ITP_EN ohm +/- % ohm +/- % ohm +/- % Open R epop VTT GN GN VTT +VRUN Within." of the ITP Within." of the ITP Within." of the ITP Within." of the ITP lose to KM Pin T GRP T GRP T GRP T GRP []# Y []# []# V []# V []# V []# T []# U []# U []# Y []# W []# Y []# W []# W []# []# []# STN[]# Y STP[]# INV[]# U []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# STN[]# STP[]# INV[]# OMP[] R MIS OMP[] U OMP[] OMP[] Y PRSTP# E PSLP# PWR# PWRGOO SLP# PSI# E H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# OMP OMP OMP OMP T PU_TEST T PU_TEST For the purpose of testability, route these signals through a ground referenced Z = ohm trace that ends in a via that is near a GN via and is accessible through an oscilloscope connection. E H_# H_# H_# H_# H_# H_# H_# E H_# F H_# H_# E H_# H_# H_# H_# F H_# H_# E F OMP OMP OMP OMP H_#[..] H_#[..] FS LK SEL SEL SEL QUNT OMPUTER Merom Processor (HOST US) H_#[..] H_STN# H_STP# H_INV# H_#[..] H_STN# H_STP# H_INV# Note: H_PRTSTP need to daisy chain from IH to IMVP to PU. H_PRSTP#,, H_PSLP# H_PWR# H_PWRGOO H_PUSLP# H_PSI# R./F omp, connect with Zo=.ohm,omp, connect with Zo=ohm, make those traces length shorter than.".trace should be at least mils away from any other toggling signal. Size ocument Number Rev FM R./F R./F R./F ate: Wednesday, November, Sheet of
+V_ORE +V_ORE +V_ORE +V_ORE +V_ORE inside cavity, north side, primary layer. +V_ORE +.V_VP ll use U V(+-%,XS,)Pb-Free. inside cavity, north side, secondary layer. inside cavity, south side, secondary layer. inside cavity, south side, primary layer. U U U U U U.U U U U U U U.U U U U U U U.U U U U U U U.U U U.U U U U U U U.U +V_ORE +PWR_SR + *U_N +V_ORE U V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] E V[] V[] E V[] V[] E V[] V[] E V[] V[] E V[] V[] E V[] V[] E V[] V[] E V[] V[] F V[] V[] F V[] V[] F V[] V[] F V[] V[] F V[] V[] F V[] V[] F E V[] V[] F E V[] E V[] VP[] G E V[] VP[] V E V[] VP[] J E V[] VP[] K E V[] VP[] M E V[] VP[] J E V[] VP[] K F V[] VP[] M F V[] VP[] N F V[] VP[] N F V[] VP[] R F V[] VP[] R F V[] VP[] T F V[] VP[] T F V[] VP[] V F V[] VP[] W V[] V[] V[] V[] V[] V[] V[] VI[] V[] VI[] F V[] VI[] E V[] VI[] F V[] VI[] E V[] VI[] F V[] VI[] E V[] V[] VSENSE V[] VSENSE F V[] V[] VSSSENSE V[] VSSSENSE E - + U. + U. +.V_VP + U + *U_N VI VI VI VI VI VI VI VSENSE VSSSENSE.U VSENSE VSSSENSE +.V_RUN Layout Note: Place near PIN. +V_ORE U R /F R /F U VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] F VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] N VSS[] N VSS[] N VSS[] P VSS[] - VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U VSS[] U VSS[] U VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] VSS[] F. Layout out: Place these inside socket cavity on North side secondary. Layout Note: Need to add uf cap on PWR_SR for cap singing. Place on PWR_SR near +V_ORE. Route VSENSE and VSSSENSE traces at.ohms and length matched to within mil. Place PU and P within inch of PU. QUNT OMPUTER Merom Processor (POWER) Size ocument Number Rev FM ate: Wednesday, November, Sheet of
+.V_VP +.V_VP R /F R /F R./F R./F H_SWING R./F H_SOMP H_SOMP# H_ROMP.U H_#[..] Layout Note: H_ROMP trace should be -mil wide with -mil spacing. +.V_VP R K/F R K/F H_RESET# H_PUSLP#.U H_#[..] H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_SWING H_ROMP H_SOMP H_SOMP# R H_REF U E H_#_ G H_#_ G H_#_ M H_#_ H H_#_ H H_#_ G H_#_ F H_#_ N H_#_ H H_#_ M H_#_ N H_#_ N H_#_ H H_#_ P H_#_ K H_#_ M H_#_ W H_#_ Y H_#_ V H_#_ M H_#_ J H_#_ N H_#_ N H_#_ W H_#_ W H_#_ N H_#_ Y H_#_ Y H_#_ P H_#_ W H_#_ N H_#_ H_#_ E H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ Y H_#_ H_#_ E H_#_ H_#_ G H_#_ J H_#_ H H_#_ J H_#_ E H_#_ E H_#_ H H_#_ J H_#_ H H_#_ J H_#_ E H_#_ J H_#_ J H_#_ E H_#_ J H_#_ H H_#_ H H_#_ H_SWING H_ROMP W H_SOMP W H_SOMP# H_PURST# E H_PUSLP# H_VREF H_VREF TMP_ HOST H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_S# H_ST#_ H_ST#_ H_NR# H_PRI# H_REQ# H_EFER# H_SY# HPLL_LK HPLL_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_INV#_ H_INV#_ H_INV#_ H_INV#_ H_STN#_ H_STN#_ H_STN#_ H_STN#_ H_STP#_ H_STP#_ H_STP#_ H_STP#_ H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_RS#_ H_RS#_ H_RS#_ J M F L G K L J K P R H L M N J E E N G H G E F M M H K E G K L E M K H L K J M E H E H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#[..] H_#[..] H_S# H_ST# H_ST# H_NR# H_PRI# H_R# H_EFER# H_SY# LK_MH_LK LK_MH_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_INV# H_INV# H_INV# H_INV# H_STN# H_STN# H_STN# H_STN# H_STP# H_STP# H_STP# H_STP# H_REQ# H_REQ# H_REQ# H_REQ# H_REQ# H_RS# H_RS# H_RS# Layout Note: Place the. uf decoupling capacitor within mils from GMH pins. restline (HOST) QUNT OMPUTER Size ocument Number Rev FM ate: Wednesday, November, Sheet of
U U +V_PEG SM_ROMP_VOH.U.U SM_ROMP_VOL.U.U +.V_RUN, R M, R M, PU_MH_SEL, PU_MH_SEL, PU_MH_SEL T T R T T T R T T T T T T R +.V_RUN T T R R PM_MUSY#,, H_PRSTP# PM_EXTTS# PM_EXTTS#, IH_PWRG, PRSLPVR S_N_PIE_RST#,,,,, PLTRST# +.V_SUS R.K/F R K/F Santa Rosa Platform MOW WW For Gb RM support, change Pin-J to R M, change Pin-E to R M. R K R K R K/F PM_EXTTS# PM_EXTTS# +.V_VP R THERMTRIP_MH# Layout Note: Location of all MH_FG strap resistors needs to be close to minmize stub. FG FG *.K/F_NFG FG FG FG *.K/F_NFG FG FG FG FG FG FG *.K/F_NFG FG FG *.K/F_NFG *.K/F_NFG R *_N P RSV P RSV R RSV N RSV R RSV R RSV M RSV N RSV J RSV R RSV M RSV L RSV M RSV RSV H RSV RSV J RSV K RSV F RSV H RSV K RSV J RSV F RSV G RSV RSV RSV J RSV E RSV H RSV W RSV K RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV P FG_ N FG_ N FG_ FG_ FG_ F FG_ N FG_ G FG_ J FG_ FG_ R FG_ L FG_ J FG_ E FG_ E FG_ K FG_ M FG_ M FG_ L FG_ N FG_ L FG_ G PM_M_USY# L PM_EXTTS# PM_PRSTP# L PM_EXTTS# PM_EXT_TS#_ J PM_EXT_TS#_ W PLTRST#_R PWROK V THERMTRIP_MH# RSTIN# N THERMTRIP# G PRSLPVR R R J N_ K N_ K N_ L N_ L N_ L N_ L N_ K N_ J N_ E N_ N_ N_ N_ N_ N_ K N_ TMP_ R PLTRST#_R R MUXING RSV LK MI FG GRPHIS VI PM ME N MIS SM_K_ SM_K_ SM_K_ SM_K_ SM_K#_ SM_K#_ SM_K#_ SM_K#_ SM_KE_ SM_KE_ SM_KE_ SM_KE_ SM_S#_ SM_S#_ SM_S#_ SM_S#_ SM_OT_ SM_OT_ SM_OT_ SM_OT_ SM_ROMP SM_ROMP# SM_ROMP_VOH SM_ROMP_VOL SM_VREF_ SM_VREF_ PLL_REF_LK PLL_REF_LK# PLL_REF_SSLK PLL_REF_SSLK# PEG_LK PEG_LK# MI_RXN_ MI_RXN_ MI_RXN_ MI_RXN_ MI_RXP_ MI_RXP_ MI_RXP_ MI_RXP_ MI_TXN_ MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_ MI_TXP_ MI_TXP_ MI_TXP_ GFX_VI_ GFX_VI_ GFX_VI_ GFX_VI_ GFX_VR_EN L_LK L_T L_PWROK L_RST# L_VREF SVO_TRL_LK SVO_TRL_T LK_REQ# IH_SYN# TEST_ TEST_ V V W W W E Y G G K G E H J J E L K K L R W H H K K N J N N M J N N J J M M J J M M E E M K T N M H K G G R SMROMPP SMROMPN SM_ROMP_VOH SM_ROMP_VOL MH_LVREF M_LK_R M_LK_R M_LK_R M_LK_R M_LK_R# M_LK_R# M_LK_R# M_LK_R# R_KE_IMM, R_KE_IMM, R_KE_IMM, R_KE_IMM, R_S_IMM#, R_S_IMM#, R_S_IMM#, R_S_IMM#, M_OT, M_OT, M_OT, M_OT, V_R_MH_REF LK_MH_GPLL LK_MH_GPLL# MI_MRX_ITX_N MI_MRX_ITX_N MI_MRX_ITX_N MI_MRX_ITX_N MI_MRX_ITX_P MI_MRX_ITX_P MI_MRX_ITX_P MI_MRX_ITX_P MI_MTX_IRX_N MI_MTX_IRX_N MI_MTX_IRX_N MI_MTX_IRX_N MI_MTX_IRX_P MI_MTX_IRX_P MI_MTX_IRX_P MI_MTX_IRX_P T T T T T L_LK L_T IH_L_PWROK, IH_L_RST# LK_GPLLREQ# MH_IH_SYN# R K R SMROMPP SMROMPN Non-iMT MH_LVREF.U +.V_SUS R /F +.V_RUN FG FG R /F FG FG FG R K/F R /F SVO_RTL_T J L_KLT_TRL H L_KLT_EN E L_TRL_LK E L_TRL_T L LK L T K L_V_EN L LVS_IG L LVS_VG N LVS_VREFH N LVS_VREFL LVS_LK# LVS_LK LVS_LK# E LVS_LK G LVS_T#_ E LVS_T#_ F LVS_T#_ G LVS_T_ E LVS_T_ F LVS_T_ G LVS_T#_ LVS_T#_ LVS_T#_ E LVS_T_ LVS_T_ LVS_T_ E TV_ G TV_ K TV_ F TV_RTN J TV_RTN L TV_RTN M TV_ONSEL_ P TV_ONSEL_ H RT_LUE G RT_LUE# K RT_GREEN J RT_GREEN# F RT_RE E RT_RE# K RT LK G RT T F RT_HSYN RT_TVO_IREF E RT_VSYN TMP_ Low=MIx MI X Select High=MIx(efault) PI Express Graphic Lane FS ynamic OT MI Lane Reversal SVO/PIE oncurrent Operation SVO Present. LVS TV VG PI-EXPRESS GRPHIS Low= Reveise Lane High=Normal operation Low=ynamic OT isable High=ynamic OT Enable(default). Low=Normal(default). High=Lane Reversed Low=Only SVO or PIEx is operational (defaults) High=SVO and PIEx are operating simultaneously via PEG port Low=No SVO evice Present (default) High=SVO evice Present PEG_OMPI N PEG_OMPO M PEG_RX#_ J PEG_RX#_ L PEG_RX#_ N PEG_RX#_ T PEG_RX#_ T PEG_RX#_ U PEG_RX#_ Y PEG_RX#_ Y PEG_RX#_ PEG_RX#_ W PEG_RX#_ PEG_RX#_ PEG_RX#_ G PEG_RX#_ H PEG_RX#_ G PEG_RX#_ G PEG_RX_ J PEG_RX_ L PEG_RX_ M PEG_RX_ U PEG_RX_ T PEG_RX_ T PEG_RX_ W PEG_RX_ W PEG_RX_ PEG_RX_ Y PEG_RX_ PEG_RX_ PEG_RX_ H PEG_RX_ G PEG_RX_ H PEG_RX_ G VG_PIE_R PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_N[..] PIE_MRX_GTX_P[..] PIE_MTX_GRX_N[..] PIE_MTX_GRX_P[..] PIE_MTX_GRX N PIE_MTX_GRX_N PEG_TX#_ N.U PIE_MTX_GRX N.U PIE_MTX_GRX_N PEG_TX#_ U PIE_MTX_GRX N PIE_MTX_GRX_N PEG_TX#_ U.U PIE_MTX_GRX N.U PIE_MTX_GRX_N PEG_TX#_ N PIE_MTX_GRX N PIE_MTX_GRX_N PEG_TX#_ R.U PIE_MTX_GRX N.U PIE_MTX_GRX_N PEG_TX#_ T PIE_MTX_GRX N PIE_MTX_GRX_N PEG_TX#_ Y.U PIE_MTX_GRX N.U PIE_MTX_GRX_N PEG_TX#_ W PIE_MTX_GRX N.U PIE_MTX_GRX_N PEG_TX#_ W PIE_MTX_GRX N PIE_MTX_GRX_N PEG_TX#_.U PIE_MTX_GRX N PIE_MTX_GRX_N PEG_TX#_.U PIE_MTX_GRX N PIE_MTX_GRX_N PEG_TX#_.U PIE_MTX_GRX N PIE_MTX_GRX_N PEG_TX#_.U PIE_MTX_GRX N PIE_MTX_GRX_N PEG_TX#_ H.U PIE_MTX_GRX N PIE_MTX_GRX_N PEG_TX#_ E.U PIE_MTX_GRX N PIE_MTX_GRX_N PEG_TX#_ H.U PIE_MTX_GRX P PIE_MTX_GRX_P PEG_TX_ M.U PIE_MTX_GRX P.U PIE_MTX_GRX_P PEG_TX_ T PIE_MTX_GRX P PIE_MTX_GRX_P PEG_TX_ T.U PIE_MTX_GRX P.U PIE_MTX_GRX_P PEG_TX_ N PIE_MTX_GRX P PIE_MTX_GRX_P PEG_TX_ R.U PIE_MTX_GRX P.U PIE_MTX_GRX_P PEG_TX_ U PIE_MTX_GRX P.U PIE_MTX_GRX_P PEG_TX_ W PIE_MTX_GRX P PIE_MTX_GRX_P PEG_TX_ Y.U PIE_MTX_GRX P PIE_MTX_GRX_P PEG_TX_ Y.U PIE_MTX_GRX P.U PIE_MTX_GRX_P PEG_TX_ PIE_MTX_GRX P PIE_MTX_GRX_P PEG_TX_.U PIE_MTX_GRX P PIE_MTX_GRX_P PEG_TX_.U PIE_MTX_GRX P PIE_MTX_GRX_P PEG_TX_.U PIE_MTX_GRX P PIE_MTX_GRX_P PEG_TX_ G.U PIE_MTX_GRX P PIE_MTX_GRX_P PEG_TX_ E.U PIE_MTX_GRX P PIE_MTX_GRX_P PEG_TX_ H.U QUNT OMPUTER restline (VG,MI) R./F Size ocument Number Rev FM ate: Wednesday, November, Sheet of
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R M R M R M R M R M R M R M R M R QS R QS R QS R QS R QS R QS R QS R QS R M R M R M R M R M R M R M R M R S R WE# R RS# R S# R S R S R M R M R M R M R M R M R QS# R QS# R QS# R QS# R QS# R QS# R QS# R QS# R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R S R S R S R S# R WE# R RS# R M R QS# R QS# R QS# R QS# R QS# R QS# R QS# R QS# R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R QS R QS R QS R QS R QS R QS R QS R QS R M R M R M R M R M R M R [..] R S, R WE#, R RS#, R S, R S, R S#, R QS#[..] R M[..], R QS[..] R M[..] R [..] R S#, R S, R S, R S, R QS#[..] R M[..], R QS[..] R M[..] R WE#, R RS#, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM restline (R) Wednesday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM restline (R) Wednesday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM restline (R) Wednesday, November, R SYSTEM MEMORY UE TMP_ R SYSTEM MEMORY UE TMP_ S_Q_ P S_Q_ R S_Q_ S_Q_ E S_Q_ S_Q_ Y S_Q_ F S_Q_ F S_Q_ J S_Q_ J S_Q_ J S_Q_ L S_Q_ W S_Q_ K S_Q_ K S_Q_ K S_Q_ K S_Q_ J S_Q_ L S_Q_ J S_Q_ J S_Q_ K S_Q_ J S_Q_ W S_Q_ L S_Q_ K S_Q_ K S_Q_ E S_Q_ K S_Q_ S_Q_ S_Q_ E S_Q_ S_Q_ G S_Q_ N S_Q_ J S_Q_ L S_Q_ K S_Q_ L S_Q_ K S_Q_ K S_Q_ J S_Q_ J S_Q_ F S_Q_ H S_Q_ N S_Q_ G S_Q_ S_Q_ K S_Q_ E S_Q_ S_Q_ J S_Q_ S_Q_ S_Q_ R S_Q_ T S_Q_ V S_Q_ Y S_Q_ Y S_Q_ U S_Q_ T S_Q_ V S_Q_ S_Q_ S_S_ Y S_S_ G S_S_ G S_S# E S_M_ R S_M_ S_M_ K S_M_ L S_M_ H S_M_ J S_M_ F S_M_ W S_QS_ T S_QS_ S_QS_ K S_QS_ K S_QS_ J S_QS_ L S_QS_ E S_QS_ V S_QS#_ U S_QS#_ S_QS#_ L S_QS#_ K S_QS#_ K S_QS#_ K S_QS#_ F S_QS#_ V S_M_ S_M_ G S_M_ G S_M_ E S_M_ S_M_ G S_M_ G S_M_ W S_M_ F S_M_ E S_M_ S_M_ S_M_ Y S_M_ S_RS# V S_RVEN# Y S_WE# R SYSTEM MEMORY U TMP_ R SYSTEM MEMORY U TMP_ S_Q_ R S_Q_ W S_Q_ G S_Q_ J S_Q_ S_Q_ G S_Q_ H S_Q_ E S_Q_ W S_Q_ E S_Q_ G S_Q_ E S_Q_ S_Q_ F S_Q_ H S_Q_ G S_Q_ F S_Q_ R S_Q_ W S_Q_ T S_Q_ W S_Q_ W S_Q_ Y S_Q_ Y S_Q_ V S_Q_ T S_Q_ V S_Q_ T S_Q_ W S_Q_ V S_Q_ U S_Q_ T S_Q_ S_Q_ S_Q_ R S_Q_ E S_Q_ S_Q_ S_Q_ Y S_Q_ G S_Q_ W S_Q_ S_Q_ S_Q_ S_Q_ Y S_Q_ R S_Q_ T S_Q_ T S_Q_ Y S_Q_ S_Q_ R S_Q_ R S_Q_ R S_Q_ N S_Q_ M S_Q_ N S_Q_ T S_Q_ T S_Q_ N S_Q_ M S_Q_ N S_Q_ W S_Q_ S_Q_ F S_S_ S_S_ K S_S_ F S_S# L S_M_ T S_M_ S_M_ S_M_ W S_M_ W S_M_ G S_M_ Y S_QS_ T S_QS_ E S_QS_ S_QS_ S_QS_ S_QS_ H S_QS_ S_QS_ P S_M_ N S_QS#_ T S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ H S_QS#_ S_QS#_ P S_M_ J S_M_ S_M_ S_M_ E S_M_ G S_M_ J S_M_ K S_M_ H S_M_ L S_M_ K S_M_ J S_M_ J S_M_ L S_M_ S_RS# E S_RVEN# Y S_WE# T T T T
VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF +V_GMH_L +.V_RUN +.V_VP +.V_SUS +.V_VP +.V_VP +.V_VP +.V_SUS Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM restline (V,NTF) Wednesday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM restline (V,NTF) Wednesday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM restline (V,NTF) Wednesday, November, Layout Note: Place where LVS and R taps. Layout Note: Place on the edge. Layout Note: Inside GMH cavity. Layout Note: Place close to GMH edge. Layout Note: Inside GMH cavity. Layout Note: mils from edge. Non-iMT V_SM.U.U POWER V NTF VSS NTF VSS S V XM V XM NTF UF TMP_ POWER V NTF VSS NTF VSS S V XM V XM NTF UF TMP_ V_NTF_ V_NTF_ K V_NTF_ P V_NTF_ U V_NTF_ F V_NTF_ F V_NTF_ H V_NTF_ H V_NTF_ H V_NTF_ H V_NTF_ J V_NTF_ K V_NTF_ K V_NTF_ K V_NTF_ V_NTF_ L V_NTF_ L V_NTF_ V_NTF_ P V_NTF_ R V_NTF_ R V_NTF_ T V_NTF_ T V_NTF_ T V_NTF_ U V_NTF_ V_NTF_ U V_NTF_ U V_NTF_ U V_NTF_ U V_NTF_ V V_NTF_ V V_NTF_ V V_NTF_ V_NTF_ V_NTF_ VSS_NTF_ T VSS_NTF_ T VSS_NTF_ U VSS_NTF_ U VSS_NTF_ V VSS_NTF_ V VSS_NTF_ VSS_NTF_ VSS_NTF_ V_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ F VSS_NTF_ K VSS_NTF_ M VSS_NTF_ P VSS_NTF_ R VSS_NTF_ R VSS_NTF_ R V_NTF_ Y V_XM_ K V_XM_ K V_XM_ J V_XM_ J V_XM_NTF_ L V_XM_NTF_ L V_XM_NTF_ L V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ P V_XM_NTF_ P V_XM_NTF_ R V_NTF_ Y V_NTF_ Y V_NTF_ Y V_NTF_ Y VSS_S VSS_S VSS_S VSS_S L VSS_S L VSS_S V_NTF_ V_NTF_ V_NTF_ V_NTF_ J V_NTF_ VSS_NTF_ F V_NTF_ J V_XM_ K V_XM_NTF_ L V_XM_NTF_ L V_XM_NTF_ L VSS_NTF_ M V_XM_NTF_ M V_XM_NTF_ M V_NTF_ M VSS_NTF_ P V_XM_NTF_ P V_XM_NTF_ P V_XM_NTF_ R V_XM_NTF_ R V_XM_ T V_XM_ T V_NTF_ V.U.U U U U U U U U U R R U U.U.U + U. + U..U.U.U.U SMKL--F SMKL--F.U.U.U.U POWER V ORE V SM V GFX V GFX NTF V SM LF UG TMP_ POWER V ORE V SM V GFX V GFX NTF V SM LF UG TMP_ V_ V_ K V_ J V_ J V_ H V_ H V_ H V_ F V_ T V_ V_SM_ V_SM_ F V_SM_ J V_SM_ W V_SM_ Y V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ E V_SM_ E V_SM_ E V_SM_ U V_SM_ F V_SM_ G V_SM_ G V_SM_ G V_SM_ H V_SM_ H V_SM_ H V_SM_ J V_SM_ J V_SM_ U V_SM_ K V_SM_ K V_SM_ K V_SM_ K V_XG_NTF_ U V_XG_NTF_ U V_XG_NTF_ U V_XG_NTF_ U V_XG_NTF_ U V_XG_NTF_ U V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ T V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ T V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ T V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ F V_XG_NTF_ F V_XG_NTF_ H V_XG_NTF_ H V_XG_NTF_ H V_XG_NTF_ H V_XG_NTF_ T V_XG_NTF_ J V_XG_NTF_ J V_XG_NTF_ J V_XG_NTF_ K V_XG_NTF_ K V_XG_NTF_ L V_XG_NTF_ L V_XG_NTF_ L V_XG_NTF_ L V_XG_NTF_ L V_XG_NTF_ T V_XG_NTF_ L V_XG_NTF_ M V_XG_NTF_ M V_XG_NTF_ M V_XG_NTF_ M V_XG_NTF_ M V_XG_NTF_ P V_XG_NTF_ P V_XG_NTF_ P V_XG_NTF_ T V_XG_NTF_ P V_XG_NTF_ P V_XG_NTF_ P V_XG_NTF_ U V_XG_NTF_ U V_SM_ L V_SM_ V V_SM_ W V_XG_NTF_ T V_ T V_SM_ U V_XG_ R V_XG_ T V_XG_ W V_XG_ W V_XG_ Y V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ F V_XG_ F V_XG_ H V_XG_ H V_XG_ H V_XG_ H V_XG_NTF_ P V_XG_NTF_ P V_XG_NTF_ R V_XG_NTF_ R V_XG_NTF_ R V_XG_NTF_ R V_XG_NTF_ R V_ R V_XG_ H V_XG_ J V_XG_ N V_SM_LF W V_SM_LF V_SM_LF E V_SM_LF V_SM_LF V_SM_LF W V_SM_LF T V_XG_ V_XG_ V_ H V_XG_NTF_ M V_SM_ U V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ Y.U.U.U.U.U.U.U.U.U.U.U.U U U.U.U + U. + U.
Non-iMT +.V_RUN _m_.ohm L LMS +V_HPLL L LMS +V_MPLL R./F +V_MPLL_L U +.V_RUN m Mx. F_ohm+-%_mHz L U F_ohm+-%_MHz.ohm.U.U +.V_RUN LMPSGPT +V_PEG_PLL R /F U. +.V_RUN Non-iMT PJP SHORT U.U PJP + U SHORT.U.. +.V_RUN U U. U U.U +.V_RUN +.V_RUN Non-iMT.U U.U.U.U +V_HPLL +V_MPLL +V_PEG_PLL +V_SM U +V_SM_K +V_PEG_PLL.U J K U UH V_RT V_RT H L M K V_PLL V_PLL V_HPLL V_MPLL V_LVS V_PEG_G V_PEG_PLL V_TV V_TV V_TV V_TV V_TV V_TV M V_RT L V_TV N U VSYN V G W V_SM_ V V_SM_ U V_SM_ U V_SM_ U V_SM_ T V_SM_ T V_SM_ T V_SM_ T V_SM_ T V_SM_ R V_SM_NTF_ R V_SM_NTF_ V_SM_K_ V_SM_K_ N VSS G VSS_LVS VSS_PEG_G V_Q V_HPLL V_PEG_PLL J V_LVS_ H V_LVS_ TMP_ +VTTLF +VTTLF +VTTLF RT PLL K SM PEG LVS POWER TV TV/RT LVS X XF SM K HV MI PEG VTT VTTLF VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_NTF V_XF_ V_XF_ V_XF_ V_MI V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_TX_LVS V_HV_ V_HV_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_RXR_MI_ V_RXR_MI_ VTTLF VTTLF VTTLF U U U U U U U U U U T T T T T T T T T R R R T U U T T T R J K K J J W W V V H H F H +V_SM_K +VTTLF +VTTLF +VTTLF +.V_VP Place on the edge. +.V_RUN.U. +V_X_L +.V_RUN +V_RXR_MI +.V_VP.U Place on the edge..u. U.U.U. +V_X_R L Reserved L pad for inductor. U Place caps close to V_X. + U + U +V_PEG +.V_RUN.U U. U. + U L L.uH NoniMT +.V_RUN PJP uh+-%_..uh +.V_VP uh+-%_. V_HV *SMKL--F_N U +.V_VP R *_N +.V_VP +.V_RUN +.V_RUN +V_HV_L U. Place caps close to V_XF.U.U.U L uhh +V_SM_K R uh+-%_m /F +V_SM_K_L U.U U. +.V_SUS QUNT OMPUTER restline (POWER) Size ocument Number Rev FM ate: Wednesday, November, Sheet of
Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM restline (VSS) Wednesday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM restline (VSS) Wednesday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM restline (VSS) Wednesday, November, VSS UJ TMP_ VSS UJ TMP_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ H VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ K VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ P VSS_ P VSS_ P VSS_ P VSS_ P VSS_ R VSS_ T VSS_ T VSS_ T VSS_ U VSS_ U VSS_ U VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ Y VSS_ Y VSS_ Y VSS_ V VSS_ V VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ P VSS_ T VSS_ T VSS_ T VSS_ R VSS_ VSS_ VSS_ VSS_ F VSS_ F VSS_ T VSS_ V VSS_ H VSS UI TMP_ VSS UI TMP_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_ E VSS_ E VSS_ F VSS_ F VSS_ F VSS_ F VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ K VSS_ K VSS_ K VSS_ K VSS_ L VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ P VSS_ P VSS_ P VSS_ R VSS_ R VSS_ R VSS_ R VSS_ R VSS_ R VSS_ T VSS_ T VSS_ T VSS_ T VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ F VSS_ F VSS_ F VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ K VSS_ K VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ V VSS_ V VSS_ W VSS_ W VSS_ K VSS_ K VSS_ K VSS_ L VSS_ L VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ K VSS_ K VSS_ L VSS_ L VSS_ L VSS_ L VSS_ VSS_ VSS_
.KHZ R M +RT_ELL +RT_ELL IH_RTX W IH_RTX R K/F IH_INTVRMEN IH_LN_SLP R.KHZ R K/F P P R *_N R *_N IH_Z_OE_ITLK IH_Z_OE_SYN IH_Z_OE_RST# IH_Z_OE_SOUT ST_RX- ST_RX+ ST_TX- ST_TX+ +RT_ELL ST_TX-_ ST_TX+_ ST_TX-_ ST_TX+_ IH_RTRST# IH_INTRUER# Z_IT_LK Z_SYN Z_RST# Z_SOUT Place all series terms close to IH except for SIN input lines,which should be close to source.placement of R, R, R & R should equal distance to the T split trace point. asically, keep the same distance from T for all series termination resistors. P P P P istance between the IH- M and cap on the "P" signal should be identical distance between the IH- M and cap on the "N" signal for same pair. R M *P_N R K U R R R R T Reserved for Intel Nineveh T design. T T T T T +.V_SUS IH_RTX IH_RTX IH_RTRST# GLN_LK LN_RX LN_RX LN_RX LN_TX LN_TX LN_TX R./F +.V_PIE_IH GLN_OMP IH_Z_OE_SIN T T T +.V_SUS ST_T# ST_RX- ST_RX+ ST_TX- ST_TX+ T T R *K_N R R Z_IT_LK Z_SYN Z_RST# Z_SOUT ST_TX-_ ST_TX+_ LK_PIE_ST# LK_PIE_ST Place within mils R./F of IH ball STIS IHM Internal VR Enable Strap (Internal VR for VccSus., VccSus., VccL.) Low = Internal VR isabled IH_INTVRMEN High = Internal VR Enabled(efault) U G RTX F RTX F IH_INTRUER# INTRUER# IH_INTVRMEN F IH_LN_SLP INTVRMEN LN_SLP GLN_LK LN_RSTSYN LN_RX LN_RX LN_RX LN_TX E LN_TX LN_TX H J H_IT_LK J H_SYN E H_RST# J H_SIN H H_SIN H H_SIN H_SIN E F RTRST# GLN_OK#/GPIO GLN_OMPI GLN_OMPO H_SOUT STLE# F STRXN F STRXP H STTXN H STTXP G STRXN G ST_TX-_ STRXP J ST_TX+_ STTXN J STTXP F STRXN F STRXP E STTXN E STTXP ST_LKN ST_LKP G STRIS# G STRIS RT LP LN / GLN IH *K_N E *K_N H_OK_EN#/GPIO G H_OK_RST#/GPIO ST NHHM-SLQ-MM# PU IE IHM LN SLP Strap (Internal VR for VccLN. and VccL.) Low = Internal VR isabled IH_LN_SLP High = Internal VR Enabled(efault) FWH/L E FWH/L F FWH/L G FWH/L F FWH/LFRME# LRQ# G LRQ#/GPIO E GTE F M# G PRSTP# F PSLP# E FERR# PUPWRG/GPIO IGNNE# G F INIT# E INTR RIN# H NMI SMI# G STPLK# THRMTRIP# TP E V U V T V T T T R T V V U V U S# Y S# Y IOR# W IOW# W K# Y IEIRQ Y IORY Y REQ W SIO_GTE H_PRSTP# H_PSLP# H_FERR# SIO_RIN# THERMTRIP#_IH IE_IRQ IE_IORY T T T T T T T T T T T T T T T T T T T T T LP_L, LP_L, LP_L, LP_L, T T LP_LFRME#, SIO_GTE H_M# H_PRSTP#,, H_PSLP# H_FERR# H_PWRGOO H_IGNNE# H_INIT# H_INTR SIO_RIN# H_NMI H_SMI# H_STPLK# T T T T R.K R.K T +.V_RUN H_PRSTP# H_PSLP# H_FERR# SIO_GTE SIO_RIN# THERMTRIP#_IH R *_N +.V_VP R *_N R K +.V_RUN +.V_VP R R K R +.V_RUN XOR hain Entrance Strap IH RSV H SOUT escription RSV Enter XOR hain Normal Operation (efault) Set PIE port config bit R *K_N Z_SOUT R *K_N IH_RSV QUNT OMPUTER IH-M (PU,IE,ST,LP,,LN) Size ocument Number Rev FM ate: Wednesday, November, Sheet of
IH_SPI_S#_R PI_GNT# Place TX blocking caps close IH. PIE_RX- PIE_RX+ PIE_TX- PIE_TX+ PIE_TX- PIE_TX+ R *K_N PI_[..] R *K_N T PI_PIRQ# PI_PIRQ# T LP PI SPI WWN Noise - IH improvements O# O# O# O# *.U_N *.U_N *.U_N *.U_N O# US_O_# US_O_# *.U_N *.U_N *.U_N O# *.U_N.U.U.U.U.U.U.U.U.U.U oot IOS Strap PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# GNT# No stuff No stuff Stuff PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ GLN_TXN_ GLN_TXP_ SPI_S# No stuff Stuff No stuff U E E G F E E E E Non-iMT +.V_SUS PI O# O# O# US_O_# Interrupt I/F F PIRQ# PIRQ# PIRQ# PIRQ# MiniWWN MiniWLN PIE_RX-/GLN_RX- PIE_RX+/GLN_RX+ Giga it LOM MiniWPN PIE_TX- PIE_TX+ PIE_TX-/GLN_TX- PIE_TX+/GLN_TX+ PIE_TX- PIE_TX+ PIE_RX- PIE_RX+ PIE_RX- PIE_RX+ PIE_RX- PIE_RX+ US_O_# US_O_# NHHM-SLQ-MM# Express ard RP KX PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ GLN_TXN_ GLN_TXP_ IH_SPI_S#_R US_O_# US_O_# O# O# O# O# O# O# +.V_SUS PI_REQ# REQ# PI_GNT# GNT# PI_REQ# REQ#/GPIO E PI_GNT# GNT#/GPIO S_WWN_PIE_RST# REQ#/GPIO PI_GNT# GNT#/GPIO F S_LOM_PIE_RST# REQ#/GPIO PI_GNT# GNT#/GPIO /E# /E# E /E# F /E# E PI_IRY# IRY# PR PI_RST#_G PIRST# G PI_EVSEL# EVSEL# PI_PERR# PERR# PI_PLOK# PLOK# PI_SERR# SERR# F PI_STOP# STOP# PI_TRY# TRY# PI_FRME# FRME# PI_PLTRST# PLTRST# G LK_PI_IH PILK PME# G PIRQE#/GPIO F PIRQF#/GPIO G PIRQG#/GPIO F PIRQH#/GPIO T T T T S_WPN_PIE_RST# S_WLN_PIE_RST# S_N_PIE_RST# IH_IRQH_GPIO US_O_# O# O# O# U P PERN P PERP N PETN N PETP M PERN M PERP L PETN L PETP K PERN K PERP J PETN J PETP H PERN H PERP G PETN G PETP F PERN F PERP E PETN E PETP PI_REQ# PI_GNT# T T S_WWN_PIE_RST# T S_LOM_PIE_RST# T PI E# PI E# PI E# PI E# PI_IRY# PI_PR PI_EVSEL# PI_PERR# PI_PLOK# PI_SERR# PI_STOP# PI_TRY# PI_FRME# LK_PI_IH IH_PME#, S_WPN_PIE_RST# S_WLN_PIE_RST# S_N_PIE_RST# T PI-Express irect Media Interface PERN/GLN_RXN PERP/GLN_RXP PETN/GLN_TXN PETP/GLN_TXP SPI_LK SPI_S# E SPI_S# SPI_MOSI F SPI_MISO J O# G O#/GPIO G O#/GPIO E O#/GPIO F O#/GPIO G O#/GPIO O#/GPIO J O#/GPIO O# H O# SPI US MIRXN V MIRXP V MITXN U MITXP U MIRXN Y MIRXP Y MITXN W MITXP W MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MI_LKN T MI_LKP T MI_ZOMP Y MI_IROMP Y USPN G USPP G USPN H USPP H USPN H USPP H USPN J USPP J USPN K USPP K USPN K USPP K USPN L USPP L USPN M USPP M USPN M USPP M USPN N USPP N USRIS# F USRIS F R./F MI_OMP USRIS NHHM-SLQ-MM# Short F and F at the package and keep length to less than mils. Trace Impedance should be ohms +/- %. IH_USP- Side pair top / left IH_USP+ IH_USP- Side pair bottom / right IH_USP+ IH_USP- Pair top / left IH_USP+ IH_USP- Pair bottom / right IH_USP+ IH_USP- amera IH_USP+ IH_USP- Mini ard (WWN) PI Pullups IH_USP+ IH_USP- Mini ard (WPN) IH_USP+ IH_USP- Express ard IH_USP+. PI_EVSEL# IH_USP- Mini ard (WLN) PI_FRME# IH_USP+ PI_REQ# IH_USP- iometric PI_PIRQ# IH_USP+ +.V_RUN R./F PI_GNT# MI_MTX_IRX_N MI_MTX_IRX_P MI_MRX_ITX_N MI_MRX_ITX_P MI_MTX_IRX_N MI_MTX_IRX_P MI_MRX_ITX_N MI_MRX_ITX_P MI_MTX_IRX_N MI_MTX_IRX_P MI_MRX_ITX_N MI_MRX_ITX_P MI_MTX_IRX_N MI_MTX_IRX_P MI_MRX_ITX_N MI_MRX_ITX_P LK_PIE_IH# LK_PIE_IH R *K_N away override strap. Low = swap override enabled. S_N_PIE_RST# High = efault. +.V_PIE_IH Place within mils of IH LK_PI_IH R *_N *.P_N Reserved for EMI.Place resister and cap close to IH. +.V_RUN PI_RST#_G PI_PLTRST# PI_REQ# PI_PLOK# PI_PERR# S_WPN_PIE_RST# R S_WWN_PIE_RST# R S_WLN_PIE_RST# R S_LOM_PIE_RST# R S_N_PIE_RST# R IOS should not enable the internal GPIO pull up resistor. Non-iMT.U.U +.V_SUS U +.V_SUS RP.KX QUNT OMPUTER IH-M (US,MI,PIE,PI) +.V_RUN PI_RST# PI_STOP# IH_IRQH_GPIO PI_SERR# PI_TRY# +.V_RUN PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_IRY# K K K K K dd uffers as needed for Loading and fanout concerns. TSZFU(TL,F,T) U RP.KX TSZFU(TL,F,T) PLTRST#,,,,, Size ocument Number Rev FM ate: Wednesday, November, Sheet of
+.V_SUS +.V_SUS LKRUN# IH_SMT IH_SMLK IH_SMLINK IH_SMLINK IH_SMLK R IH_SMLINK IH_SMT R IH_SMLINK +.V_RUN Non-iMT Non-iMT SF. RP R *_N Option to " isable " clkrun. Pulling it down will keep the clks running. R.KX RP R.K *KX_N K. PIE_MR_ET# PLTRST_ELY#,, IH_SMLK,, IH_SMT T T T PM_MUSY# H_STP_PI# H_STP_PU#, LKRUN#,,, PIE_WKE#, IRQ_SERIRQ THERM_LERT# MH_IH_SYN# +.V_SUS T ITP_RESET# US_MR_ET# SPKR R R R R IH_RSV,, IMVP_PWRG T IH_SMLK IH_SMT RSV_IH_L_RST# IH_SMLINK IH_SMLINK IH_RI# RSV_LPP# LKRUN# PIE_WKE# IRQ_SERIRQ THERM_LERT# IMVP_PWRG SPKR Non-iMT *K_N RSV_IH_L_RST# K IH_RI# K SIO_EXT_SI# K PIE_WKE# R MH_IH_SYN#_R U J SMLK SMT G LINKLERT# SMLINK E SMLINK F F SUS_STT#/LPP# SYS_RESET# G MUSY#/GPIO US_MR_ET# G SMLERT#/GPIO E STP_PI#/GPIO G STP_PU#/GPIO H LKRUN#/GPIO E WKE# F SERIRQ THRM# VRMPWRG US_MR_ET# US_MR_ET# J US_MR_ET# TH/GPIO US_MR_ET# J TH/GPIO SIO_EXT_WKE# H SIO_EXT_SMI# TH/GPIO SIO_EXT_SMI# E SIO_EXT_SI# GPIO SIO_EXT_SI# GPIO T G PIE_MR_ET# R TH/GPIO H PIE_MR_ET# GPIO PIE_MR_ET# E PIE_MR_ET# GPIO PIE_MR_ET# G SLOK/GPIO WLN_RIO_IS# H QRT_STTE/GPIO MER_L_ET# QRT_STTE/GPIO ST_LKREQ# G PLTRST_ELY# STLKREQ#/GPIO PLTRST_ELY# F SLO/GPIO WPN_RIO_IS_MINI# J STOUT/GPIO WWN_RIO_IS# STOUT/GPIO J J J J RI# TP SPKR MH_SYN# TP SM ST GPIO locks SYS GPIO Power MGT MIS GPIO ontroller Link NHHM-SLQ-MM# STGP/GPIO STGP/GPIO STGP/GPIO STGP/GPIO +.V_RUN LK_IH_M LK_IH_M IH_SUSLK IH_TLOW# RSV_IH_LN_RST# IH_RSMRST# IH_L_PWROK RSV_IH_L_LK RSV_IH_L_T L_VREF L_VREF RSV_GPIO RSV_GPIO RSV_WOL_EN LK_IH_M LK_IH_M T SIO_SLP_S# T SIO_SLP_S# IH_PWRG, PRSLPVR, +.V_SUS SIO_PWRTN# IH_RSMRST# LK_PWRG IH_L_PWROK, L_LK T L_T T T IH_L_RST# T T T +.V_SUS UM Package:R- iscrete Package: R Non-iMT Non-iMT Place these close to IH. LK_IH_M LK_IH_M R *_N IH_PWRG PRSLPVR R R K K IH_RSMRST# R *K_N RSV_IH_LN_RST# R K IH_L_PWROK R M +.V_SUS RSV_GPIO R K *.P_N *.P_N +.V_RUN +.V_LW +.V_RUN R R R R R *.K_N IMVP_PWRG K K K K K US_MR_ET# US_MR_ET# PIE_MR_ET# PIE_MR_ET# PIE_MR_ET# +.V_RUN SPKR No Reboot strap. Low = efault. SPKR High = No Reboot. SMbus address These are for backdrive issue. +.V_RUN Q,, IH_SMT MEM_ST +.V_RUN Non-iMT L_VREF L_VREF R /F +.V_RUN LK LK SUSLK SLP_S# SLP_S# SLP_S# S_STTE#/GPIO PWROK PRSLPVR/GPIO TLOW# PWRTN# LN_RST# RSMRST# K_PWRG LPWROK SLP_M# L_LK L_LK L_T L_T L_VREF L_VREF L_RST# MEM_LE/GPIO ME_E_LERT/GPIO E_ME_LERT/GPIO WOL_EN/GPIO J J F G G G G F H E IH_PWRG PRSLPVR J E H G E E J F E F F H J J J F G R.K R.K R.K T T R *_N R R *K_N NW--F RP.KX.U R.K/F *.U_N R *.K/F_N R */F_N R R R +.V_SUS R R R *K_N MH_IH_SYN#_R K IRQ_SERIRQ K THERM_LERT# K SIO_EXT_SMI# K US_MR_ET# K RSV_WOL_EN..,, IH_SMLK Q NW--F MEM_SLK QUNT OMPUTER IH-M (PM,GPIO,SM,L) Size ocument Number Rev FM ate: Thursday, November, Sheet of
+IH_VREF_SUS +IH_VREF_RUN +.V_MIPLL TP_VSUS._ TP_VSUS._ TP_VSUS._ TP_VSUS._ +VSUS_[~] TP_VL. +VL_ +VSTPLL +VSTPLL_L +VSTPLL TP_VSUSLN TP_VSUSLN +.V_MIPLL_R +VSUS_[~] +.V_VP +.V_RUN +.V_SUS +.V_RUN +V_RUN +V_SUS +.V_SUS +RT_ELL +.V_RUN +.V_VP +.V_SUS +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_PIE_IH +.V_RUN +.V_RUN +.V_PIE_IH +.V_VP +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_VP Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM IH-M (POWER,GN) Wednesday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM IH-M (POWER,GN) Wednesday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM IH-M (POWER,GN) Wednesday, November, uh+-%_m F_ohm+-%_mHz_._. ohm uh+-%_m Non-iMT Non-iMT Non-iMT Non-iMT Non-iMT WWN Noise - IH improvements WWN Noise - IH improvements Place,, close to /..U.U U. U. T T *.U_N *.U_N.U..U..U.U.U.U.U.U U U U U U U T T/R T T/R.U.U.U.U L LMPGSN L LMPGSN R R.U.U L uh L uh.u.u.u.u *.U_N *.U_N.U.U *.U_N *.U_N *.U_N *.U_N U U.U.U.U.U.U.U + U + U T T SMKL--F SMKL--F.U.U *.U_N *.U_N.U.U *.U_N *.U_N *.U_N *.U_N.U.U U U L uh L uh.u.u U. U. SMKL--F SMKL--F.U.U *U_N *U_N.U.U U U *.U_N *.U_N UE NHHM-SLQ-MM# UE NHHM-SLQ-MM# VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E VSS[] E VSS[] VSS[] E VSS[] E VSS[] E VSS[] E VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] F VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] J VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E VSS[] E VSS[] F VSS[] E VSS[] F VSS[] F VSS[] F VSS[] G VSS[] E VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] H VSS_NTF[] H VSS_NTF[] J VSS_NTF[] J VSS_NTF[] J VSS_NTF[] J VSS_NTF[] VSS_NTF[] VSS[] VSS[] VSS[] VSS[] VSS[] U VSS[] K VSS[] W *.U_N *.U_N R R R R T T R R.U.U T T R R U U.U.U.U.U U U.U.U U U T T.U.U T T.U.U ORE VGP TX RX IE US ORE PI GLN POWER VP_ORE VPSUS VPUS UF NHHM-SLQ-MM# ORE VGP TX RX IE US ORE PI GLN POWER VP_ORE VPSUS VPUS UF NHHM-SLQ-MM# VREF[] VREF[] T VREF_SUS G V [] V [] V [] V [] V [] V [] V [] V [] V [] E V [] E V [] E V [] F V [] F V [] G V [] H V [] H V [] J V [] J V [] K V [] K V [] L V [] L V [] L V [] M V [] M V [] N V [] N V [] N V [] P V [] P V [] R V [] R V [] R V [] R V [] T V [] T V [] T V [] T V [] T V [] U V_[] F VMIPLL R V [] E V [] F V [] G V [] H V [] J VSTPLL J V_[] V [] V [] V [] V [] V [] VUSPLL VLN_[] F VLN_[] G V_[] V_[] V_[] V_[] V_[] V_[] E V_[] F V_[] G V_[] L V_[] L V_[] L V_[] L V_[] L V_[] L V_[] M V_[] M V_[] P V_[] P V_[] T V_[] T VLN_[] F VLN_[] G VH VSUSH V_PU_IO[] V_PU_IO[] V_[] V_[] U V_[] V V_[] W V_[] W V_[] W V_[] Y V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] E V_[] E V_[] F VRT VSUS_[] VSUS_[] VSUS_[] VSUS_[] G VSUS_[] H VSUS_[] P VSUS_[] P VSUS_[] VSUS_[] N VSUS_[] P VSUS_[] P VSUS_[] P VSUS_[] P VSUS_[] P VSUS_[] R VSUS_[] R VSUS_[] R V [] V [] V [] V [] V [] G V [] G VSUS_[] J VSUS_[] F V [] F V [] L V [] L V [] M V [] M VSUS_[] V_[] V [] W V_[] U V_[] V V_[] V V_[] V V_[] U V_[] V V_[] V V_[] V VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_ VGLNPLL V_[] F V_[] V_[] E V_[] VSUS_[] R V [] H VSUS_[] V [] V [] VSUS_[] J V_MI[] E V_MI[] E VL_ G VL_[] G VL_[] F VL_ V [] W V [] V V [] U V [] Y V [] V V [] V T T
R M R M R QS R QS# R M R M R M R R QS R R M R R M R M R M R QS# R M R QS R S R WE# R R M R M R M R S# R QS# R R M R R M R QS# R M R M R R R R QS R R R QS R R R R R R QS# R QS R R R R R QS# R M_OT M_OT R S R QS# R QS R QS# R R RS# R R R M R QS R R R M R R R R M R M R M R S R M R M R M R QS R R QS R R M_OT R M R QS# R M R QS# R R R R M R R R R M R M R QS R RS# R R M R S R R R QS# R QS R M R R QS# R M R M R LK_SLK LK_ST PM_EXTTS# PM_EXTTS# R R R R R R R R R R R R QS R S R M LK_SLK R QS# R QS R QS# R R M R M R QS LK_ST R WE# R M R QS# R R R R R M R M R M R R QS# R R S R R M R R R M R R R R QS R S# M_OT R M R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R QS#[..] R [..] R M[..], R M[..] R QS[..] R_S_IMM#, R_S_IMM#, R QS#[..] R [..] R M[..], R S, R M[..] M_OT, M_LK_R R RS#, R QS[..] R_S_IMM#, R_S_IMM#, R S, R RS#, R_KE_IMM, R S, R_KE_IMM, R S, M_LK_R# M_LK_R PM_EXTTS# M_LK_R M_LK_R# M_LK_R MEM_ST MEM_SLK R S#, R S, R WE#, R_KE_IMM, M_OT, R S#, R WE#, R S, R_KE_IMM, M_OT, M_LK_R# M_LK_R# M_OT, R M, PM_EXTTS# R M, +.V_RUN +.V_SUS V_R_MH_REF +.V_RUN +.V_SUS +.V_SUS V_R_MH_REF +.V_SUS +.V_RUN +.V_RUN V_R_MH_REF V_R_MH_REF +.V_RUN +.V_SUS +.V_SUS +.V_SUS +.V_SUS Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM R SO-IMM Wednesday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM R SO-IMM Wednesday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM R SO-IMM Wednesday, November, LOK, LOK, SMbus address SMbus address KE, KE, Place these aps near So-imm. Place these aps near So-imm. Place these aps near So-imm. Place these aps near So-imm. H. H..U..U..U..U..U.U P R SRM SO-IMM (P) JIM R_IMM P R SRM SO-IMM (P) JIM R_IMM VREF VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS KE V N _ V V V /P WE# V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS Q Q VSS M VSS Q Q VSS Q Q VSS M VSS K K# VSS Q Q VSS VSS Q Q VSS N M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS KE V V V V RS# S# V OT V N VSS Q Q VSS M VSS Q Q VSS Q Q VSS VSS M VSS Q Q VSS Q Q VSS NTEST VSS QS# QS VSS Q Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS Q Q VSS Q Q VSS K K# VSS M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS S S VSS.U.U R K R K.U..U. P R SRM SO-IMM (P) JIM -- P R SRM SO-IMM (P) JIM -- VREF VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS KE V N _ V V V /P WE# V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS Q Q VSS M VSS Q Q VSS Q Q VSS M VSS K K# VSS Q Q VSS VSS Q Q VSS N M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS KE V V V V RS# S# V OT V N VSS Q Q VSS M VSS Q Q VSS Q Q VSS VSS M VSS Q Q VSS Q Q VSS NTEST VSS QS# QS VSS Q Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS Q Q VSS Q Q VSS K K# VSS M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS S S VSS + *U/.V_N. + *U/.V_N..U..U..U..U..U.U.U..U..U.U.U.U.U.U R K R K.U.U.U.U.U.U.U..U..U.U.U.U.U..U..U..U..U..U. R K R K.U..U..U..U. R K R K.U..U..U.U.U..U.
+.V_R_VTT Layout note: Place cap close to every R-pack terminated to SMR_VTERM..U.U.U.U.U.U.U.U.U.U.U.U.U.U +.V_R_VTT.U.U.U.U.U.U.U.U.U.U.U.U.U.U +.V_R_VTT, R M[..] R M[..], R M R M RP RP R M R M R M R M X RP X RP R M R M, R RS#, R S, M_OT, R S R RS# R S R M M_OT R S R M X RP X RP X RP X RP X RP X RP R RS# R S M_OT R M R M R M R RS#, R S, M_OT, Please these resistor closely IMM,all trace length< mil. R M R M R M R M X RP X RP X RP X RP R M R M R M R M Please these resistor closely IMM,all trace length< mil., R S, R S#, R WE# R M R S R S# R WE# R M R M X RP X RP X RP X RP X RP X RP R WE# R S R S# R M R M R M R WE#, R S, R S#, X X R, M_OT R M_OT, R M R R R S, R, R_S_IMM# R R_S_IMM#, R R, R_S_IMM# R_S_IMM#, R R, R_KE_IMM R_KE_IMM, R R, R_KE_IMM R_KE_IMM, R, R M R R M, QUNT OMPUTER R RES. RRY Size ocument Number Rev FM ate: Wednesday, November, Sheet of
dd capacitor pads for improving WWN. LK_XTL_IN P P *P_N *P_N LK_IH_M LK_IH_M LK_PI_ *P_N LK_PI_PR *P_N LK_PI_IH ST_LKREQ# LK_GPLLREQ# LK_LP_EUG LK_PI_PR LK_PI_ LK_PI_IH LK_IH_M, PU_MH_SEL, PU_MH_SEL, PU_MH_SEL LK_IH_M LK_PWRG Y LK_XTL_OUT.MHZ.MHz ST_LKREQ# LK_GPLLREQ# LK_LP_EUG R *_N LK_PI_PR R LK_PI_ LK_PI_IH LK_IH_M. P R /F R /F R R R L R.K LMGSN R.K L R.K LMGSN LK_IH_M R +K_V_PI +K_V_PLL +K_V_ +K_V_SR +K_V_MIN Only for debug ST_LKREQ#_ LK_GPLLREQ#_ PI_PR PI_SIO M_SEL PI_IH FS FS FS LK_XTL_OUT LK_XTL_IN LK_ST LK_SLK U V_PI V_REF V_PLL V_ V_SR V_PU V_IO V_IO V_IO V_IO V_IO V_IO GN GN GN GN GN GN GN GN GN R#_/PI- R_/PI- TME/PI- SR_EN/PI- M_SEL/PI- ITP_EN/PIF-# FS/US FS/TEST_MOE FS/TEST_SEL/REF RESET# K_PWRG/P# XOUT XIN ST SLK SLGSPV K QFN PU- PU-# PU- PU-# SR-/PU_ITP SR-#/PU_ITP# SR-/OT SR-#/OT# SR-/SE SR-#/SE SR-/ST SR-#/ST# R#_/SR- R#_/SR-# SR- SR-# PI_STOP#/SR- PU_STOP#/SR-# SR- SR-# R#_F/SR- R#_E/SR-# SR- SR-# SR- SR-# R#_H/SR- R#_G/SR-# GN PU_LK PU_LK# MH_LK MH_LK# PIE_MINI PIE_MINI# OT_SS OT_SS# M_SS M_NSS PIE_ST PIE_ST# PIE_MINI PIE_MINI# MH_GPLL MH_GPLL# PIE_EXPR PIE_EXPR# MINILK_REQ#_ R_LK_REQ#_ PIE_MINI PIE_MINI# PIE_IH PIE_IH# PIE_LOM PIE_LOM# RP x RP x RP x RP x RP x RP x RP x RP x RP x R /F R /F RP x RP x RP x MINILK_REQ# R_LK_REQ# LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# LK_PIE_MINI LK_PIE_MINI# LK_PIE_VG LK_PIE_VG# LK_VG_M_SS LK_VG_M_NSS LK_PIE_ST LK_PIE_ST# LK_PIE_MINI LK_PIE_MINI# LK_MH_GPLL LK_MH_GPLL# H_STP_PI# H_STP_PU# LK_PIE_EXPR LK_PIE_EXPR# MINILK_REQ# R_LK_REQ# LK_PIE_MINI LK_PIE_MINI# LK_PIE_IH LK_PIE_IH# LK_PIE_LOM LK_PIE_LOM# LK_GPLLREQ# ST_LKREQ# R_LK_REQ# MINILK_REQ# PI_PR H_STP_PI# H_STP_PU# Silego need pull up but other? R R R R R R R *K_N *K_N +.V_RUN +.V_RUN K K K K *K_N +.V_RUN L LMPGSN ohms@mhz.u L LMPGSN ohms@mhz.u R. R. R. +K_V_MIN.U +K_V_PI +K_V_PLL +K_V_.U.U UM without imt.u.u.u..u.u *U_N. These are for backdrive issue.,, SMT LK_ITP_LK LK_ITP_LK# SMbus address +.V_RUN RP Q NW--F +.V_RUN *x_n Non-iMT RP.KX LK_ST PIE_MINI PIE_MINI# PI_IH M_SEL +.V_RUN R POP: For Internal pull-low. R POP: For internal pull-high. +.V_RUN R *K_N R *K_N R K M_SEL M_SEL (PIN) =UM = isc. GRFX down OTT SRT PI_SIO PI_IH FS FS FS PU SR PI PIN PIN PIN PIN OT SR R *K_N R *K_N RSV / M_T Mout / M_ MSSout R. +K_V_SR.U,, SMLK Q NW--F LK_SLK R *K_N QUNT OMPUTER LOK GENERTOR Size ocument Number Rev FM ate: Wednesday, November, Sheet of
PIE_MTX_GRX_P[..] PIE_MTX_GRX_N[..] U PIE_MRX_GTX_P[..] PIE_MRX_GTX_N[..] PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N W W W V V V U U P P PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PRT OF P I - E X P R E S S I N T E R F E PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN Y Y Y Y V V V V T T T T P P PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_N.U.U.U.U.U.U.U.U.U.U.U.U.U.U.U.U.U PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX N PIE_MTX_GRX_P PIE_MTX_GRX_N P N PIE_RXP PIE_RXN PIE_TXP PIE_TXN P P PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX_N PIE_MRX_GTX_N.U.U PIE_MRX_GTX N PIE_MRX_GTX N PIE_MTX_GRX_P PIE_MTX_GRX_N N N PIE_RXP PIE_RXN PIE_TXP PIE_TXN M M PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX_N PIE_MRX_GTX_N.U.U PIE_MRX_GTX N PIE_MRX_GTX N PIE_MTX_GRX_P PIE_MTX_GRX_N M M PIE_RXP PIE_RXN PIE_TXP PIE_TXN M M PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX_N PIE_MRX_GTX_N.U.U PIE_MRX_GTX N PIE_MRX_GTX N PIE_MTX_GRX_P PIE_MTX_GRX_N K K PIE_RXP PIE_RXN PIE_TXP PIE_TXN L L PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX_N PIE_MRX_GTX_N.U.U PIE_MRX_GTX N PIE_MRX_GTX N PIE_MTX_GRX_P PIE_MTX_GRX_N K J PIE_RXP PIE_RXN PIE_TXP PIE_TXN L L PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX_N PIE_MRX_GTX_N.U.U PIE_MRX_GTX N PIE_MRX_GTX N PIE_MTX_GRX_P PIE_MTX_GRX_N J J PIE_RXP PIE_RXN PIE_TXP PIE_TXN J J PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX_N PIE_MRX_GTX_N.U.U PIE_MRX_GTX N PIE_MRX_GTX N PIE_MTX_GRX_P PIE_MTX_GRX_N H H PIE_RXP PIE_RXN PIE_TXP PIE_TXN G G PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX_N PIE_MRX_GTX_N.U.U PIE_MRX_GTX N PIE_MRX_GTX N LK_PIE_VG LK_PIE_VG# PLTRST_ELY# R lock PIE_REFLKP PIE_REFLKN SM US N_SMLK N_SMT G PERST M-S alibration PIE_LRN PIE_LRP N_ N_ F E E H R R.K/F K/F +PIE_V PIE_MRX_GTX_N.U PIE_MRX_GTX N QUNT OMPUTER VG-M-S (PIe) Size ocument Number Rev FM ate: Wednesday, November, Sheet of
MEMORY SIZE M M M M +.V_ELY GPIO Straps table GPIO GPIO GPIO GPIO GPIO GPIO GPIO +.V_ELY RM_FG RM_FG RM_FG RM_FG GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO HMI_H_EN TEMP_FIL# GFX_LKREQ# VGHSYN LK_VG_M_SSIN_R THERML_INT# TEMP_FIL# _EN XTIN RM_TYPE_FG RM_TYPE_FG RM_TYPE_FG RM_TYPE_FG XTOUT RM_TYPE_FG RM_TYPE_FG RM_TYPE_FG RM_TYPE_FG GPIO GPIO GPIO GPIO GPIO GPIO GPIO LK_VG_M_SSIN_R R *_N T TEMP_FIL# T GFX_LKREQ# R K T T T T R K TEMP_FIL# T T R T /F T T R *_N OS_SPRE LK_VG_M_SS LK_VG_M_NSS MEMORY PERTURE SIZE SELET FG GPIO X X X X OS_OUT.. FG FG FG GPIO GPIO GPIO R K R *K_N R *K_N R *K_N ESRIPTION OF EFULT SETTINGS PIE FULL TX OUTPUT SWING PIE TRNSMITTER E-EMPHSIS ENLE TI reserved configuration straps. TI reserved configuration straps. EUG SIGNLS MUXE OUT llows either PIe.GT/s or.gt/s operation TI Internal use only. GFX_ORE_NTRL GFX_ORE_NTRL TI Usage X X RSV RSV Memory Straps MHz M(M*) Samsung MHz M(M*) Hynix MHz M(M*) Samsung MHz M(M*) Qimonda +.V_RUN FM Usage GPIO Serial ROM clock to ROM. TI Usage = O NOT INSTLL RESISTOR, X = ESIGN EPENNT, recommended settings RSV = TI RESERVE (O NOT INSTLL) R K R K R *K_N R *K_N R *K_N R *K_N R *K_N R *K_N R K R *K_N R K R *K_N R /F R /F Y R *_N *MHZ_N R *M_N *P_N *P_N X R R *_N R *_N R *K_N R *K_N R K R *K_N R. R R *K_N PNEL_KEN RM_ RM_ RM_ RM_ TYPE_FG TYPE_FG TYPE_FG TYPE_FG +.V_RUN R /F.U. HMI_H_EN RM_FG GPIO RM_FG RM_FG RM_FG T +PLL_PV +PIE_PV +MPV +PLL_V R K U J TXM_PP J TXP_PN L TXM_PP K TXP_PN L TXM_PP K TXP_PN K TXM_PP L TXP_PN VLI E PSYN_NEW K VPNTL_MVP_ L VPNTL_MVP_ PRT OF INTEGRTE TXM_PP TMS/P PORT TXP_PN TXM_PP TXP_PN TXM_PP TXP_PN TXM_PP TXP_PN P_PV P_PVSS P_PV P_PVSS P_VR_ P_VR_ V VPNTL_ P_VR_ V VPNTL_ P_VR_ W VPNTL_ P_VSSR_ W VPLK P_VSSR_ P_VSSR_ Y VPT_ P_VSSR_ Y VPT_ P_VSSR_ Y VPT_ VPT_ P_VSSR_ VPT_ P_VSSR_ VPT_ P_VSSR_ VPT_ P_VSSR_ VPT_ P_VSSR_ VPT_ VPT_ P_LR VPT_ VPT_ EXT TMS HP VPT_ F VO VPT_ R G VPT_ R H VPT_ G VPT_ G H VPT_ G H VPT_ J VPT_ J VPT_ J / RT VPT_ K VPT_ HSYN K VPT_ VSYN RSET Y GPIO_ V GPIO_ V V GPIO_ V GENERL GPIO_ PURPOSE VSSQ U GPIO_ I/O U GPIO_ VI T GPIO_ T GPIO LON VSSI T GPIO ROMSO T GPIO ROMSI R R GPIO ROMSK R R GPIO_ R GPIO_ G P GPIO_ G P GPIO HP N GPIO PWRNTL (TV/RT) N GPIO SSIN P GPIO THERML_INT P GPIO HP P GPIO TF P GPIO PWRNTL Y V GPIO EN N GPIO ROMS OMP Y GPIO LKREQ M GPIO JMOE VSYN M GPIO TI HSYN M GPIO TK M GPIO TMS V L GPIO TO VQ Y GEN_ Y GEN_ VSSQ V GEN_ H GEN HP VI G GEN_E VSSI VREFG RSET H PLL_PV G PLL_PVSS SL S H PIE_PV SERIL USES T PLL & LK MPV XTL MPVSS T LK E PLL_V T_P_UXN J XTLIN LK_P_UXP J XTLOUT T_P_UXN LK_P_UXP TS_FO H TEST TESTEN THERML PLUS PLLTEST MINUS M-S K L J J L K L K L K E F J J K L L K J H H J F G J H G L K L K L K K K J L H J J L K L K L K J J J E F H H G F E G J H F H F G E E E R VIP_ R VGHSYN +V +TPV R /F +VQ L_T L_LK +P_VR +P_VR R R R +V_ +V_ R /F R R +V LVS L_T L_LK HMI HMI_S HMI_SL G_T_ G_LK_ RT VG_THERMP VG_THERMN HMI_LK- HMI_LK+ HMI_TX- HMI_TX+ HMI_TX- HMI_TX+ HMI_TX- HMI_TX+. VG_RE VG_GRN VG_LU VGHSYN VGVSYN R /F R /F +.V_RUN VG_LU VG_GRN VG_RE R /F L_T L_LK QUNT OMPUTER VG-GGLM (VIEO) Q R MMST--F R K K +.V_ELY HMI_ET IS only Layout Note: Place ohm termination resistors close to TI HIP.. R.K R.K. Size ocument Number Rev FM ate: Friday, November, Sheet of