FM6B Hepburn Intel UMA

FM Hepburn Intel UM VER : POWER /TT ONNETOR PG R-SOIMM PG, R-SOIMM PG, SYSTEM RESET IRUIT TT HRGER RUN POWER SW +.V_SUS/+V_SUS +V/+.V/+.V MHZ R II MHZ R II ST-O PG PG PG PG ST Merom or Penryn ( Micro-FPG) restline MI interface ufg PG, MHz FS PG,,,,, FN & THERML SMS PG LOK SLGSPV (QFN-) PG US. x PIEx LVS SVO IH VG SiI POWER REGULTOR +.V_RUN/+.V_VP REGULTOR +.V_SUS/+.V_RUN /+.V_R_VTT PG US conn x PG HMI PG PG PU VR / +.V_LW/+V_LW/+V_LW PG Panel onnector PG HMI ONN. RT ONN. LN MM PG PG PG PG RJ/Magnetics PG SiI udio SPK conn PG UIO/MP ST /H PG udio Jacks x PG ST-H PG amera + -MI PG USER INTERFE PG ST IH US. SPI FLSH Mbyts LP K ITE PG IH-M G X PS/ Touchpad PG PG PG,,, IR TSOPTR PG Keyboard PG PIEx US. PIEx US. PIEx US. US. iometric PG MHz PI -in- ard Reader R PG EXPRESS-R R PG MINI-R WLN MINI-R WWN MINI-R WPN ONN. PG PG PG ard Reader ONN. PG QUNT OMPUTER Schematic lock iagram PG Size ocument Number Rev FM ate: Sunday, November, Sheet of

Table of ontents PGE ESRIPTION Schematic lock iagram Front Page - Merom - restline - IHM - RII SO-IMM(P) lock Generator HMI L onn. & SSP RT onn ST onn - R REER/onn & Express ard & Smart ard - Mini ard SIO (ITE) FLSH/RT US TP / KEYOR SWITH /LE FN & Thermal - udio OE(L)/Phone Jack - LOM / Switch System Reset ircuit attery Selector & harger.vp /.VRUJN R_.VSUS,.V PU_ISL(phase) MX (+.V,+,V) RUN Power Switch IN,att & SREW EMI P SMUS LOK Power lock ianram POWER PLNE +PWR_SR +RT_ELL +.V_LW +V_LW +V_LW +.V_LN +V_SUS +.V_SUS +.V_SUS +.V_R_VTT +V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_VP +V_ORE +LV +V_MO +V_H +PTT +STT VOLTGE V~+V +.V~+.V +.V +V +V +.V +V +.V +.V +.V +V +.V +.V +.V +.V +.V +.V~+.V +.V +V +V +V~+V +V~+V Power States PGE,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ESRIPTION MIN POWER RT POWER L/HRGE POWER LRGE POWER LN POWER SLP_S# TRL POWER SLP_S# TRL POWER SOIMM POWER SOIMM POWER SLP_S# TRL POWER SLP_S# TRL POWER SVO POWER LISTOG/IH POWER LISTOG/IH POWER PU ORE POWER MIN TTERY SEON TTERY ONTROL SIGNL PU/LISTOG/IH POWER.V_RUN_ON L Power Module Power H Power LWON LWON +V_LW UX_ON SUS_ON.V_SUS_ON R_ON.V_R_VTT_ON RUN_ON.V_RUN_ON RUN_ON.V_RUN_ON.V_RUN_ON IMVP_VR_ON LV_TST_EN & ENV MO_EN# H_EN# HG_PTT HG_STT TIVE IN S~S S~S S~S S~S S~S GN PLNE PGE ESRIPTION GN GN_.V GN_/ GN_ GN_R GN_ISL GN LL QUNT OMPUTER Index & Power Status Size ocument Number Rev FM ate: Wednesday, November, Sheet of

H_#[..] H_ST# H_REQ#[..] H_#[..] H_ST# H_M# H_FERR# H_IGNNE# H_STPLK# H_INTR H_NMI H_SMI# For E test use ET ET ET ET ET ET ET ET ET ET ET ET ET ET ET ET H_STN# H_STP# H_# H_# H_STN# H_STP# H_# H_# H_STN# H_STP# H_# H_# H_STN# H_STP# H_# H_# +.V_VP H_#[..] H_REQ#[..] H_#[..] H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_REQ# H_REQ# H_REQ# H_REQ# H_REQ# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# Populate ITPFlex for bringup U J []# S# H L []# NR# E L []# PRI# G K []# M []# EFER# H N []# RY# F J []# SY# E N []# P []# R# F P []# L []# IERR# P []# INIT# P []# R []# LOK# H M ST[]# RESET# K REQ[]# RS[]# F H REQ[]# RS[]# F K REQ[]# RS[]# G J REQ[]# TRY# G L REQ[]# HIT# G Y []# HITM# E U []# R []# PM[]# W []# PM[]# U []# PM[]# Y []# PM[]# U []# PRY# R []# PREQ# T []# TK T []# TI W []# TO W []# TMS Y []# TRST# U []# R# V []# W []# []# THERML []# []# PROHOT# V ST[]# THERM THERM M# FERR# IGNNE# THERMTRIP# IH STPLK# LINT LINT SMI# M RSV[] N RSV[] T RSV[] V RSV[] RSV[] RSV[] RSV[] RSV[] RSV[] F RSV[] R GROUP R GROUP RESERVE ONTROL XP/ITP SIGNLS H LK LK[] LK[] - H_IERR# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_TK ITP_TI ITP_TO ITP_TMS ITP_TRST# ITP_RESET# H_PROHOT# H_THERM H_THERM R H_THERM R H_S# H_NR# H_PRI# H_EFER# H_RY# H_SY# H_R# +.V_VP H_INIT# H_LOK# R H_RESET# H_RS# H_RS# H_RS# H_TRY# R H_HIT# H_HITM# ITP_RESET# +.V_VP T H_THERM H_THERM +.V_VP LK_PU_LK LK_PU_LK# *P_N H_THERM H_THERM For E test use ET ET ET ET ET ET H_ST# H_# H_# H_ST# H_# H_# +.V_VP R /F H_PROHOT# Layout Note: Place R close to PU. +.V_VP H_RESET# Layout Note: Place voltage divider within." of GTLREF pin R K/F R K/F +.V_VP +.V_RUN H_#[..] H_STN# H_STP# H_INV# H_#[..] H_STN# H_STP# H_INV#, PU_MH_SEL, PU_MH_SEL, PU_MH_SEL +.V_LW Q *NW--F_N Voltage Level shift R *.K_N PU_PROHOT# H_#[..] H_#[..] H_THERMTRIP#, H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# R *K/F_N R *K/F_N *.U_N R *_N U E []# F []# E []# G []# F []# G []# E []# E []# K []# G []# J []# J []# H []# F []# K []# H []# J STN[]# H STP[]# H INV[]# N []# K []# P []# R []# L []# M []# L []# M []# P []# P []# P []# T []# R []# L []# T []# N []# L STN[]# M STP[]# N INV[]# V_PU_GTLREF PU_TEST GTLREF PU_TEST TEST PU_TEST TEST PU_TEST TEST F PU_TEST TEST F PU_TEST TEST TEST SEL[] SEL[] SEL[] - PU_TEST PU_TEST PU_TEST PU_TEST Place close to the PU_TEST pin. Make sure PU_TEST routing is reference to GN and away from other noisy signal. T GRP T GRP T GRP T GRP []# Y []# []# V []# V []# V []# T []# U []# U []# Y []# W []# Y []# W []# W []# []# []# STN[]# Y STP[]# INV[]# U []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# STN[]# STP[]# INV[]# OMP[] R MIS OMP[] U OMP[] OMP[] Y PRSTP# E PSLP# PWR# PWRGOO SLP# PSI# E H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# E H_# H_# H_# H_# H_# H_# H_# E H_# F H_# H_# E H_# H_# H_# H_# F H_# H_# E F OMP OMP OMP OMP H_#[..] H_#[..] H_#[..] H_STN# H_STP# H_INV# H_#[..] H_STN# H_STP# H_INV# Note: H_PRTSTP need to daisy chain from IH to IMVP to PU. H_PRSTP#,, H_PSLP# H_PWR# H_PWRGOO H_PUSLP# H_PSI# T T PU_TEST PU_TEST For the purpose of testability, route these signals through a ground referenced Z = ohm trace that ends in a via that is near a GN via and is accessible through an oscilloscope connection. FS LK SEL SEL SEL ITP_TI ITP_TMS ITP_TK ITP_TO ITP_TRST# H_RESET# ITP_TK LK_ITP_LK# LK_ITP_LK R /F R /F R */F_N R ITP_TK ITP_TRST# R /F R JITP TI TMS R TK *_N TO TRST# R *./F_N RESET# Layout Note: Place R close ITP. FO LKN LKP GN GN GN GN GN GN *ITPFlex_N Layout Note: Place couple.uf ecoupling caps with in." ITP connector. VTT VTT VTP R# # PM# PM# PM# PM# PM# PM# N N GN_ GN_ +.V_VP *.U_N *.U_N R ITP_RESET# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# +.V_SUS Layout Note: Place R,R, R, R, R, R close to PU H_THERM Q MMST--F Signal TI TMS TRST# TK TO ITP_EN R M.U Q NW--F ITP disable guidelines Resistor Value. ohm +/- % onnect To Resistor Placement ohm +/- % ohm +/- % Openohm +/- % VTT VTT GN GN Within." of the ITP Within." of the ITP Within." of the ITP Within." of the ITP R epop VTT Within." of the ITP +VRUN lose to KM Pin OMP OMP OMP OMP omp, connect with Zo=.ohm,omp, connect with Zo=ohm, make those traces length shorter than.".trace should be at least mils away from any other toggling signal. QUNT OMPUTER Merom Processor (HOST US) R./F Size ocument Number Rev FM R./F R./F R./F ate: Tuesday, November, Sheet of

+V_ORE +V_ORE +V_ORE +V_ORE +V_ORE inside cavity, north side, primary layer. +V_ORE +.V_VP ll use U V(+-%,XS,)Pb-Free. U U U U inside cavity, north side, secondary layer. inside cavity, south side, secondary layer. inside cavity, south side, primary layer. U U U U U.U U U U U U.U U U U U U.U U U U U U.U U U.U U U U U U U.U +V_ORE +PWR_SR + *U_N +V_ORE U V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] E V[] V[] E V[] V[] E V[] V[] E V[] V[] E V[] V[] E V[] V[] E V[] V[] E V[] V[] F V[] V[] F V[] V[] F V[] V[] F V[] V[] F V[] V[] F V[] V[] F E V[] V[] F E V[] E V[] VP[] G E V[] VP[] V E V[] VP[] J E V[] VP[] K E V[] VP[] M E V[] VP[] J E V[] VP[] K F V[] VP[] M F V[] VP[] N F V[] VP[] N F V[] VP[] R F V[] VP[] R F V[] VP[] T F V[] VP[] T F V[] VP[] V F V[] VP[] W V[] V[] V[] V[] V[] V[] V[] VI[] V[] VI[] F V[] VI[] E V[] VI[] F V[] VI[] E V[] VI[] F V[] VI[] E V[] V[] VSENSE V[] VSENSE F V[] V[] VSSSENSE V[] VSSSENSE E - + *U_N. + *U_N +.V_VP + U + *U_N VI VI VI VI VI VI VI VSENSE VSSSENSE.U VSENSE VSSSENSE +.V_RUN Layout Note: Place near PIN. +V_ORE U R /F R /F U VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] F VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] N VSS[] N VSS[] N VSS[] P VSS[] - VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U VSS[] U VSS[] U VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] VSS[] F. Layout out: Place these inside socket cavity on North side secondary. Layout Note: Need to add uf cap on PWR_SR for cap singing. Place on PWR_SR near +V_ORE. Route VSENSE and VSSSENSE traces at.ohms and length matched to within mil. Place PU and P within inch of PU. QUNT OMPUTER Merom Processor (POWER) Size ocument Number Rev FM ate: Tuesday, November, Sheet of

+.V_VP +.V_VP R /F R /F R./F R./F H_SWING R./F H_SOMP H_SOMP# H_ROMP.U H_#[..] Layout Note: H_ROMP trace should be -mil wide with -mil spacing. +.V_VP R K/F H_RESET# H_PUSLP# H_#[..] H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_SWING H_ROMP H_SOMP H_SOMP# R H_REF U E H_#_ G H_#_ G H_#_ M H_#_ H H_#_ H H_#_ G H_#_ F H_#_ N H_#_ H H_#_ M H_#_ N H_#_ N H_#_ H H_#_ P H_#_ K H_#_ M H_#_ W H_#_ Y H_#_ V H_#_ M H_#_ J H_#_ N H_#_ N H_#_ W H_#_ W H_#_ N H_#_ Y H_#_ Y H_#_ P H_#_ W H_#_ N H_#_ H_#_ E H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ Y H_#_ H_#_ E H_#_ H_#_ G H_#_ J H_#_ H H_#_ J H_#_ E H_#_ E H_#_ H H_#_ J H_#_ H H_#_ J H_#_ E H_#_ J H_#_ J H_#_ E H_#_ J H_#_ H H_#_ H H_#_ H_SWING H_ROMP W H_SOMP W H_SOMP# H_PURST# E H_PUSLP# H_VREF H_VREF HOST H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_S# H_ST#_ H_ST#_ H_NR# H_PRI# H_REQ# H_EFER# H_SY# HPLL_LK HPLL_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_INV#_ H_INV#_ H_INV#_ H_INV#_ H_STN#_ H_STN#_ H_STN#_ H_STN#_ H_STP#_ H_STP#_ H_STP#_ H_STP#_ H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_RS#_ H_RS#_ H_RS#_ J M F L G K L J K P R H L M N J E E N G H G E F M M H K E G K L E M K H L K J M E H E H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#[..] H_#[..] H_S# H_ST# H_ST# H_NR# H_PRI# H_R# H_EFER# H_SY# LK_MH_LK LK_MH_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_INV# H_INV# H_INV# H_INV# H_STN# H_STN# H_STN# H_STN# H_STP# H_STP# H_STP# H_STP# H_REQ# H_REQ# H_REQ# H_REQ# H_REQ# H_RS# H_RS# H_RS# +.V_VP +.V_VP +.V_VP +.V_VP *.U_N +.V_VP +.V_VP +.V_VP *.U_N *.U_N *.U_N *.U_N Layout Note: should be near,,,y should be near,e,g,e should be near,,,,,,,,,, should be near E,F,H,H,G,H,G,H should be near M,L,K,M,N,N,M,M,N,P should be near H,J,L,M,L,K,J,H should be near E,G,F,,,,,, *.U_N *.U_N R K/F.U LEGM-SLT-MM# Layout Note: Place the. uf decoupling capacitor within mils from GMH pins. restline (HOST) QUNT OMPUTER Size ocument Number Rev FM ate: Tuesday, November, Sheet of

SM_ROMP_VOH.U.U SM_ROMP_VOL.U.U +.V_RUN, R M, R M, PU_MH_SEL, PU_MH_SEL, PU_MH_SEL T T R T T T R T T T T T T R +.V_RUN T T R R PM_MUSY#,, H_PRSTP# PM_EXTTS# PM_EXTTS#, IH_PWRG, PRSLPVR,,,,,, R_S_IMM# R_S_IMM# S_N_PIE_RST# PLTRST# +.V_SUS Santa Rosa Platform MOW WW For Gb RM support, change Pin-J to R M, change Pin-E to R M. R K R K PM_EXTTS# PM_EXTTS# THERMTRIP_MH# Layout Note: Location of all MH_FG strap resistors needs to be close to minmize stub. For E test use ET +.V_VP R ET R K/F R.K/F R K/F FG FG *.K/F_NFG FG FG FG *.K/F_NFG FG FG FG FG FG FG *.K/F_NFG FG FG *.K/F_NFG *.K/F_NFG R *_N R R U P RSV P RSV R RSV N RSV R RSV R RSV M RSV N RSV J RSV R RSV M RSV L RSV M RSV RSV H RSV RSV J RSV K RSV F RSV H RSV K RSV J RSV F RSV G RSV RSV RSV J RSV E RSV H RSV W RSV K RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV P FG_ N FG_ N FG_ FG_ FG_ F FG_ N FG_ G FG_ J FG_ FG_ R FG_ L FG_ J FG_ E FG_ E FG_ K FG_ M FG_ M FG_ L FG_ N FG_ L FG_ G PM_M_USY# L PM_EXTTS# PM_PRSTP# L PM_EXTTS# PM_EXT_TS#_ J PM_EXT_TS#_ W PLTRST#_R PWROK V THERMTRIP_MH# RSTIN# N THERMTRIP# G R PRSLPVR J N_ K N_ K N_ L N_ L N_ L N_ L N_ K N_ J N_ E N_ N_ N_ N_ N_ N_ K N_ PLTRST#_R R MUXING RSV LK MI FG GRPHIS VI PM ME N MIS LEGM-SLT-MM# SM_K_ V SM_K_ SM_K_ SM_K_ V SM_K#_ W SM_K#_ SM_K#_ W SM_K#_ W SM_KE_ E SM_KE_ Y SM_KE_ SM_KE_ G SM_S#_ G SM_S#_ K SM_S#_ G SM_S#_ E SM_OT_ H SM_OT_ J SM_OT_ J SM_OT_ E SM_ROMP L SM_ROMP# K SM_ROMP_VOH K SM_ROMP_VOL L SM_VREF_ R SM_VREF_ W PLL_REF_LK PLL_REF_LK# PLL_REF_SSLK H PLL_REF_SSLK# H PEG_LK K PEG_LK# K MI_RXN_ N MI_RXN_ J MI_RXN_ N MI_RXN_ N MI_RXP_ M MI_RXP_ J MI_RXP_ N MI_RXP_ N MI_TXN_ J MI_TXN_ J MI_TXN_ M MI_TXN_ M MI_TXP_ J MI_TXP_ J MI_TXP_ M MI_TXP_ M GFX_VI_ E GFX_VI_ GFX_VI_ GFX_VI_ GFX_VR_EN E L_LK M L_T K L_PWROK T L_RST# N L_VREF M SVO_TRL_LK H SVO_TRL_T K LK_REQ# G IH_SYN# G TEST_ TEST_ R SMROMPP SMROMPN SM_ROMP_VOH SM_ROMP_VOL MH_LVREF R K M_LK_R M_LK_R M_LK_R M_LK_R M_LK_R# M_LK_R# M_LK_R# M_LK_R# R_KE_IMM, R_KE_IMM, R_KE_IMM, R_KE_IMM, R_S_IMM#, R_S_IMM#, R_S_IMM#, R_S_IMM#, M_OT, M_OT, M_OT, M_OT, V_R_MH_REF MH_REFLK MH_REFLK# REF_SSLK REF_SSLK# LK_MH_GPLL LK_MH_GPLL# MI_MRX_ITX_N MI_MRX_ITX_N MI_MRX_ITX_N MI_MRX_ITX_N MI_MRX_ITX_P MI_MRX_ITX_P MI_MRX_ITX_P MI_MRX_ITX_P MI_MTX_IRX_N MI_MTX_IRX_N MI_MTX_IRX_N MI_MTX_IRX_N MI_MTX_IRX_P MI_MTX_IRX_P MI_MTX_IRX_P MI_MTX_IRX_P T T T T T L_LK L_T IH_L_PWROK, IH_L_RST# SVO_TRLLK SVO_TRLT LK_GPLLREQ# MH_IH_SYN# R L_IG UM SMROMPP SMROMPN Non-iMT MH_LVREF.U G_LK_ G_T_ VGHSYN, H_THERMTRIP# R.K/F R /F FG FG FG FG FG VGVSYN I_PWM PNEL_KEN L_LK L_T ENV R /F R /F +.V_RUN R /F SVO_RTL_T R K/F R /F L_+ L_+ L_+ SVO_INT- L_LK- L_LK+ L_LK- L_LK+ L_- +.V_SUS L_- L_- L_- L_- L_- L_+ L_+ L_+ VG_LU VG_GRN VG_RE VG_LU VG_GRN VG_RE R /F T R VG_LU L_LK L_T L_IG VG_GRN VG_RE *_N THERMTRIP_MH# MI X Select PI Express Graphic Lane FS ynamic OT MI Lane Reversal SVO/PIE oncurrent Operation UM Layout Note: Place ohm termination resistors close to GMH. SVO Present. R /F R.K/F R /F U Low=MIx High=MIx(efault) Low= Reveise Lane High=Normal operation Low=ynamic OT isable High=ynamic OT Enable(default). Low=Normal(default). High=Lane Reversed J L_KLT_TRL H L_KLT_EN E L_TRL_LK E L_TRL_T L LK L T K L_V_EN L LVS_IG L LVS_VG N LVS_VREFH N LVS_VREFL LVS_LK# LVS_LK LVS_LK# E LVS_LK G LVS_T#_ E LVS_T#_ F LVS_T#_ G LVS_T_ E LVS_T_ F LVS_T_ G LVS_T#_ LVS_T#_ LVS_T#_ E LVS_T_ LVS_T_ LVS_T_ E TV_ G TV_ K TV_ F TV_RTN J TV_RTN L TV_RTN M TV_ONSEL_ P TV_ONSEL_ H RT_LUE G RT_LUE# K RT_GREEN J RT_GREEN# F RT_RE E RT_RE# K RT LK G RT T F RT_HSYN RT_TVO_IREF E RT_VSYN Low=Only SVO or PIEx is operational (defaults) High=SVO and PIEx are operating simultaneously via PEG port Low=No SVO evice Present (default) High=SVO evice Present LVS TV VG LEGM-SLT-MM# +.V_RUN R.K R.K PI-EXPRESS GRPHIS R./F PEG_OMPI N VG_PIE_R PEG_OMPO M PEG_RX#_ J PEG_RX#_ L PEG_RX#_ N PEG_RX#_ T PEG_RX#_ T PEG_RX#_ U PEG_RX#_ Y PEG_RX#_ Y PEG_RX#_ PEG_RX#_ W PEG_RX#_ PEG_RX#_ PEG_RX#_ G PEG_RX#_ H PEG_RX#_ G PEG_RX#_ G PEG_RX_ J PEG_RX_ L PEG_RX_ M PEG_RX_ U PEG_RX_ T PEG_RX_ T PEG_RX_ W PEG_RX_ W PEG_RX_ PEG_RX_ Y PEG_RX_ PEG_RX_ PEG_RX_ H PEG_RX_ G PEG_RX_ H PEG_RX_ G PEG_TX#_ N PEG_TX#_ U PEG_TX#_ U PEG_TX#_ N PEG_TX#_ R PEG_TX#_ T PEG_TX#_ Y PEG_TX#_ W PEG_TX#_ W PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ H PEG_TX#_ E PEG_TX#_ H PEG_TX_ M PEG_TX_ T PEG_TX_ T PEG_TX_ N PEG_TX_ R PEG_TX_ U PEG_TX_ W PEG_TX_ Y PEG_TX_ Y PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ G PEG_TX_ E PEG_TX_ H VO_RE#_ VO_GREEN#_ VO_LUE#_ VO_LK#_ VO_RE_ VO_GREEN_ VO_LUE_ VO_LK_ locked ap. QUNT OMPUTER restline (VG,MI) SVO_INT+ VO_RE#_ VO_GREEN#_ VO_LUE#_ VO_LK#_ VO_RE_ VO_GREEN_ VO_LUE_ VO_LK_ L_LK L_T.U.U.U.U.U.U.U.U UM +V_PEG SVO_INT- SVO_INT+ SVO_RE- SVO_GREEN- SVO_LUE- SVO_LK- SVO_RE+ SVO_GREEN+ SVO_LUE+ SVO_LK+ Size ocument Number Rev FM ate: Tuesday, November, Sheet of

R [..] U R R R S_Q_ W R S_Q_ R S_Q_ Y R S_Q_ R R S_Q_ R R S_Q_ T R S_Q_ W R S_Q_ R S_Q_ F R S_Q_ G R S_Q_ J R S_Q_ R S_Q_ G R S_Q_ H R S_Q_ E R S_Q_ W R S_Q_ E R S_Q_ G R S_Q_ E R S_Q_ F R S_Q_ H R S_Q_ G R S_Q_ F R S_Q_ R R S_Q_ W R S_Q_ T R S_Q_ W R S_Q_ W R S_Q_ Y R S_Q_ V R S_Q_ T R S_Q_ V R S_Q_ T R S_Q_ W R S_Q_ V R S_Q_ U R S_Q_ T R S_Q_ R S_Q_ R S_Q_ E R S_Q_ R S_Q_ R S_Q_ Y R S_Q_ G R S_Q_ W R S_Q_ R S_Q_ R S_Q_ R S_Q_ Y R S_Q_ T R S_Q_ T R S_Q_ Y R S_Q_ R S_Q_ R R S_Q_ R R S_Q_ R R S_Q_ N R S_Q_ M R S_Q_ N R S_Q_ T R S_Q_ N R S_Q_ M R S_Q_ N S_Q_ R SYSTEM MEMORY S_S_ S_S_ S_S_ S_S# S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_RS# S_RVEN# S_WE# R S K R S F R S L R S# T R M R M R M W R M W R M G R M Y R M N R M T R QS E R QS R QS R QS R QS H R QS R QS P R QS T R QS# R QS# R QS# R QS# R QS# H R QS# R QS# P R QS# J R M R M K R M H R M L R M K R M J R M J R M L R M R M R M E R M G R M J R M E R RS# Y R WE# T R [..] R S, R S, R S, R S#, R M[..] R QS[..] R QS#[..] R M[..], R RS#, R WE#, UE R P R S_Q_ R R S_Q_ W R S_Q_ W R S_Q_ N R S_Q_ N R S_Q_ V R S_Q_ V R S_Q_ R S_Q_ R S_Q_ R S_Q_ E R S_Q_ R S_Q_ Y R S_Q_ F R S_Q_ F R S_Q_ J R S_Q_ J R S_Q_ J R S_Q_ L R S_Q_ K R S_Q_ K R S_Q_ K R S_Q_ K R S_Q_ J R S_Q_ L R S_Q_ J R S_Q_ J R S_Q_ K R S_Q_ J R S_Q_ L R S_Q_ K R S_Q_ K R S_Q_ E R S_Q_ K R S_Q_ R S_Q_ R S_Q_ E R S_Q_ R S_Q_ G R S_Q_ J R S_Q_ L R S_Q_ K R S_Q_ L R S_Q_ K R S_Q_ K R S_Q_ J R S_Q_ J R S_Q_ F R S_Q_ H R S_Q_ G R S_Q_ R S_Q_ K R S_Q_ E R S_Q_ R S_Q_ J R S_Q_ R S_Q_ R S_Q_ R R S_Q_ T R S_Q_ Y R S_Q_ Y R S_Q_ U R S_Q_ T S_Q_ R SYSTEM MEMORY S_S_ S_S_ S_S_ S_S# S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_RS# S_RVEN# S_WE# Y R S G R S G R S E R S# R R M R M K R M L R M H R M J R M F R M W R M T R QS R QS K R QS K R QS J R QS L R QS E R QS V R QS U R QS# R QS# L R QS# K R QS# K R QS# K R QS# F R QS# V R QS# R M G R M G R M W R M F R M E R M R M R M Y R M R M G R M E R M R M G R M V R RS# Y R WE# T R S, R S, R S, R S#, R M[..] R QS[..] R QS#[..] R M[..], R RS#, R WE#, LEGM-SLT-MM# LEGM-SLT-MM# For E test use ET ET ET ET ET ET ET ET ET R S# R RS# R WE# R M R M R QS R QS# R R ET R S# ET R RS# ET R WE# ET R M ET ET ET R M R QS R QS# ET R ET R ET R ET R S restline (R) QUNT OMPUTER Size ocument Number Rev FM ate: Tuesday, November, Sheet of

+.V_VP +.V_SUS +.V_VP UG T V_ T V_ H V_ V_ V_ K V_ J V_ J V_ H V_ H V_ H V_ F V_ V ORE R V_ U V_SM_ U V_SM_ U V_SM_ V V_SM_ W V_SM_ W V_SM_ Y V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ E V_SM_ E V_SM_ E V_SM_ F V_SM_ F V_SM_ G V_SM_ G V_SM_ G V_SM_ H V_SM_ H V_SM_ H V_SM_ J V_SM_ J V_SM_ J V_SM_ K V_SM_ K V_SM_ K V_SM_ K V_SM_ L V_SM_ U V_SM_ POWER V SM V GFX V GFX NTF R V_XG_ T V_XG_ W V_XG_ W V_XG_ Y V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ F V_XG_ F V_XG_ V_XG_ H V_XG_ H V_XG_ H V_XG_ H V_XG_ H V_XG_ V_XG_ J V_XG_ N V_XG_ LEGM-SLT-MM# V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V SM LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF T T T T T T T U U U U U U U U V V V V V V V Y Y Y Y Y Y Y Y Y Y Y F F H H H H J J J K K L L L L L L M M M M M M P P P P P P P P R R R R R V V V Y W E W T VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF Layout Note: mils from edge. + U. +.V_VP Layout Note: mils from edge. Layout Note: Inside GMH cavity for V_XG..U.U + U..U.U + *U_N..U.U U +.V_VP +.V_VP +.V_VP +.V_RUN U.U Layout Note: Inside GMH cavity. + *U_N..U + U. U. No IS U Non-iMT.U U R +V_GMH_L Layout Note: Inside GMH cavity. U.U.U Layout Note: Place close to GMH edge..u U.U.U SMKL--F.U +.V_SUS.U.U Layout Note: Place where LVS and R taps. UF V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ F V_NTF_ F V_NTF_ H V_NTF_ H V_NTF_ H V_NTF_ H V_NTF_ J V_NTF_ J V_NTF_ K V_NTF_ K V_NTF_ K V_NTF_ K V_NTF_ V_NTF_ J V_NTF_ M V_NTF_ L V_NTF_ L V_NTF_ V_NTF_ V_NTF_ V_NTF_ P V_NTF_ P V_NTF_ R V_NTF_ R V_NTF_ Y V_NTF_ Y V_NTF_ Y V_NTF_ Y V_NTF_ Y V_NTF_ T V_NTF_ T V_NTF_ T V_NTF_ U V_NTF_ U V_NTF_ U V_NTF_ U V_NTF_ U V_NTF_ U V_NTF_ V V_NTF_ V V_NTF_ V V_NTF_ V V_NTF_ V NTF L V_XM_NTF_ L V_XM_NTF_ L V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ P V_XM_NTF_ P V_XM_NTF_ P V_XM_NTF_ P V_XM_NTF_ L V_XM_NTF_ L V_XM_NTF_ L V_XM_NTF_ R V_XM_NTF_ R V_XM_NTF_ R V_XM_NTF_ POWER V XM NTF LEGM-SLT-MM# + U. U Layout Note: Place on the edge. QUNT OMPUTER restline (V,NTF) VSS NTF VSS S V XM VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_S VSS_S VSS_S VSS_S VSS_S VSS_S V_XM_ V_XM_ V_XM_ V_XM_ V_XM_ V_XM_ V_XM_ V_SM U T T U U V V F F K M M P P R R R L L T T K K K J J +.V_VP Size ocument Number Rev FM ate: Sunday, November, Sheet of

+.V_RUN R./F +V_MPLL_L +V_TVG_R +.V_RUN L LMPGSN +V_RT +.V_RUN _m_.ohm L LMS +V_HPLL +.V_RUN F_ohm+-%_mHz_m_.ohm Non-iMT L U LMS m Mx. F_ohm+-%_mHz L +V_MPLL F_ohm+-%_MHz.ohm +.V_RUN nf &.uf for V_TV:_R should be placed with in mils from restline. R U.U LMPSGPT +V_PEG_PLL +V_TV_L +.V_RUN +V_TVG +.V_RUN +.V_RUN +.V_RUN *SMKL--F_N TV Voltage Follower ircuit - mv..aps should be placed mils with in its pins. Non-iMT L uh L uh +.V_RUN F_ohm+-%_mHz_m_.ohm *nf_n.u R /F U. L LMPGSN.U R*_N PJP.U U..U SHORT R./F R R +V_TV +V_TV +V_RT_R m Mx. uh+-%_m U.U *nf_n +V_PLL +V_PLL Non-iMT.U..U R U +.V_SUS *nf_n *nf_n +.V_RUN +.V_RUN +V_TV_R +V_TV_R R +V_TV +V_TV_R INS.U *nf_n.u + U + U PJP SHORT + U..U U R.U.U U.U P.U U.U +V_RT_R +V_TVG_R +V_PLL +V_PLL +V_HPLL +V_MPLL +V_TX_LVS +V_PEG_PLL +V_SM U +V_SM_K +V_TV_R +V_TV_R +V_TV_R +V_TV_R +VQ_TV_R +V_PEG_PLL +V_LVS +.V_RUN U R J K U UH V_RT V_RT H L M K V_PLL V_PLL V_HPLL V_MPLL V_LVS V_PEG_G V_PEG_PLL V_TV V_TV V_TV V_TV V_TV V_TV M V_RT L V_TV N U VSYN V G W V_SM_ V V_SM_ U V_SM_ U V_SM_ U V_SM_ T V_SM_ T V_SM_ T V_SM_ T V_SM_ T V_SM_ R V_SM_NTF_ R V_SM_NTF_ V_SM_K_ V_SM_K_ N VSS G VSS_LVS VSS_PEG_G V_Q V_HPLL V_PEG_PLL J V_LVS_ H V_LVS_.U +VQ_TV RT PLL K SM PEG LVS POWER TV TV/RT LVS *U_N LEGM-SLT-MM#. +VTTLF +VTTLF +VTTLF U.U R *nf_n R *nf_n X XF SM K HV MI PEG.U VTT VTTLF VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_NTF V_XF_ V_XF_ V_XF_ V_MI V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_TX_LVS V_HV_ V_HV_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_RXR_MI_ V_RXR_MI_ VTTLF VTTLF VTTLF.U +V_TV_R +VQ_TV_R U U U U U U U U U U T T T T T T T T T R R R T U U T T T R J K K J J W W V V H H F H +V_SM_K +V_TX_LVS +VTTLF +VTTLF +VTTLF +.V_VP Place on the edge. +.V_RUN.U. +V_X_L +.V_RUN +V_RXR_MI +.V_VP Place on the edge..u. U.U U.U..U. +V_X_R L Reserved L pad for inductor. SHORT U Place caps close to V_X. P + U + U +V_PEG +V_SM_K +.V_RUN.U + U R /F +V_SM_K_L +.V_RUN QUNT OMPUTER restline (POWER) NoniMT R For EMI fine tune. R For EMI fine tune. U. U..U + U R For EMI fine tune.. U. PJP V_HV *SMKL--F_N U +.V_VP +.V_VP +.V_SUS R +.V_VP +.V_RUN +.V_RUN +V_HV_L Place caps close to V_XF For EMI fine tune. R *_N U. +.V_SUS Size ocument Number Rev FM ate: Monday, November, Sheet of

Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM restline (VSS) Sunday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM restline (VSS) Sunday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM restline (VSS) Sunday, November, VSS UJ LEGM-SLT-MM# VSS UJ LEGM-SLT-MM# VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ H VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ K VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ P VSS_ P VSS_ P VSS_ P VSS_ P VSS_ R VSS_ T VSS_ T VSS_ T VSS_ U VSS_ U VSS_ U VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ Y VSS_ Y VSS_ Y VSS_ V VSS_ V VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ P VSS_ T VSS_ T VSS_ T VSS_ R VSS_ VSS_ VSS_ VSS_ F VSS_ F VSS_ T VSS_ V VSS_ H VSS UI LEGM-SLT-MM# VSS UI LEGM-SLT-MM# VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_ E VSS_ E VSS_ F VSS_ F VSS_ F VSS_ F VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ K VSS_ K VSS_ K VSS_ K VSS_ L VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ P VSS_ P VSS_ P VSS_ R VSS_ R VSS_ R VSS_ R VSS_ R VSS_ R VSS_ T VSS_ T VSS_ T VSS_ T VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ F VSS_ F VSS_ F VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ K VSS_ K VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ V VSS_ V VSS_ W VSS_ W VSS_ K VSS_ K VSS_ K VSS_ L VSS_ L VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ K VSS_ K VSS_ L VSS_ L VSS_ L VSS_ L VSS_ VSS_ VSS_

.KHZ R M +RT_ELL +RT_ELL +.V_VP IH_RTX P W R.KHZ IH_RTX P R K/F IH_INTVRMEN R *_N R K/F IH_LN_SLP R *_N H_PRSTP# H_PSLP# H_FERR# THERMTRIP#_IH R *_N R *_N R R IH_Z_HMI_ITLK IH_Z_OE_ITLK IH_Z_HMI_SYN IH_Z_OE_SYN IH_Z_HMI_RST# IH_Z_OE_RST# IH_Z_HMI_SOUT IH_Z_OE_SOUT *P_N +RT_ELL ST_TX-_ ST_TX+_ ST_TX-_ ST_TX+_ IH_RTRST# IH_INTRUER# Z_IT_LK Z_SYN Z_RST# Z_SOUT Place all series terms close to IH except for SIN input lines,which should be close to source.placement of R, R, R & R should equal distance to the T split trace point as R, R, R & R respective. asically,keep the same distance from T for all series termination resistors. P P istance between the IH- M and cap on the "P" signal should be identical distance between the IH- M and cap on the "N" signal for same pair. P P R M R K U R R *P_N R R R R R R Reserved for Intel Nineveh T T design. T T T T +.V_SUS +.V_PIE_IH IH_Z_OE_SIN IH_Z_HMI_SIN T T +.V_SUS ST_T# ST_RX- ST_RX+ ST_TX- ST_TX+ ST_TX- ST_TX+ ST_RX- ST_RX+ T T T LK_PIE_ST# LK_PIE_ST Place within mils of IH ball R *K_N IHM Internal VR Enable Strap (Internal VR for VccSus., VccSus., VccL.) Low = Internal VR isabled IH_INTVRMEN High = Internal VR Enabled(efault) IH_RTX IH_RTX IH_RTRST# GLN_LK LN_RX LN_RX LN_RX LN_TX LN_TX LN_TX R./F GLN_OMP R R Z_IT_LK Z_SYN Z_RST# Z_SOUT ST_TX-_ ST_TX+_ ST_TX-_ ST_TX+_ R./F STIS U IHM LN SLP Strap (Internal VR for VccLN. and VccL.) Low = Internal VR isabled IH_LN_SLP High = Internal VR Enabled(efault) LP_L, LP_L, LP_L, LP_L, LP_LFRME#, SIO_GTE H_M# H_PRSTP#,, H_PSLP# H_FERR# H_PWRGOO H_IGNNE# H_INIT# H_INTR SIO_RIN# H_NMI H_SMI# H_STPLK# +.V_RUN SIO_GTE SIO_RIN# +.V_RUN +.V_RUN XOR hain Entrance Strap IH RSV H SOUT escription RSV Enter XOR hain Normal Operation (efault) Set PIE port config bit G RTX F RTX F IH_INTRUER# INTRUER# IH_INTVRMEN F IH_LN_SLP INTVRMEN LN_SLP GLN_LK LN_RSTSYN LN_RX LN_RX LN_RX LN_TX E LN_TX LN_TX H J H_IT_LK J H_SYN E H_RST# J H_SIN H H_SIN H H_SIN H_SIN E F RTRST# GLN_OK#/GPIO GLN_OMPI GLN_OMPO H_SOUT STLE# F STRXN F STRXP H STTXN H STTXP G STRXN G STRXP J STTXN J STTXP F STRXN F STRXP E STTXN E STTXP ST_LKN ST_LKP G STRIS# G STRIS RT LP LN / GLN IH *K_N E *K_N H_OK_EN#/GPIO G H_OK_RST#/GPIO ST NHHM-SLQ-MM# FWH/L E FWH/L F FWH/L G FWH/L F FWH/LFRME# LRQ# G T LRQ#/GPIO E T SIO_GTE GTE F M# G H_PRSTP# PRSTP# F H_PSLP# PSLP# E FERR# H_FERR# PUPWRG/GPIO G IGNNE# F INIT# E INTR RIN# H SIO_RIN# NMI SMI# G STPLK# THRMTRIP# E THERMTRIP#_IH TP T T V T U T V T T T V T T T T T T T T R T T T V T V T U T V T U T T T T S# Y T S# Y T IOR# W T IOW# W T K# Y IE_IRQ IEIRQ Y IE_IORY IORY Y REQ W T PU IE R.K R.K R K R K R *K_N Z_SOUT R *K_N IH_RSV QUNT OMPUTER IH-M (PU,IE,ST,LP,,LN) Size ocument Number Rev FM ate: Tuesday, November, Sheet of

Place TX blocking caps close IH. PIE_RX- PIE_RX+ PIE_TX- PIE_TX+ IH_SPI_S#_R PI_GNT# WWN Noise - IH improvements O# O# O# O# O# US_O_# US_O_# O# R *K_N.U.U.U.U.U.U.U.U.U.U R *K_N LP PI SPI *.U_N *.U_N *.U_N *.U_N *.U_N *.U_N *.U_N *.U_N oot IOS Strap GNT# No stuff No stuff Stuff PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ GLN_TXN_ GLN_TXP_ SPI_S# No stuff Stuff No stuff Non-iMT +.V_SUS O# US_O_# O# O# MiniWWN MiniWLN PIE_RX-/GLN_RX- PIE_RX+/GLN_RX+ Giga it LOM MiniWPN PIE_RX+ PIE_RX-/GLN_RX- PIE_RX+/GLN_RX+ PIE_TX-/GLN_TX- PIE_TX+/GLN_TX+ PIE_TX- PIE_TX+ PIE_TX- PIE_TX+ PIE_TX-/GLN_TX- PIE_TX+/GLN_TX+ PIE_TX- PIE_TX+ PIE_RX- PIE_RX+ PIE_RX- PIE_RX+ PIE_RX- PIE_RX+ US_O_# US_O_# Express ard T T T T RP KX PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ GLN_TXN_ GLN_TXP_ IH_SPI_S#_R US_O_# US_O_# O# O# O# O# O# O# +.V_SUS O# O# O# US_O_# U P PERN P PERP N PETN N PETP M PERN M PERP L PETN L PETP K PERN K PERP J PETN J PETP H PERN H PERP G PETN G PETP F PERN F PERP E PETN E PETP PI-Express irect Media Interface PERN/GLN_RXN PERP/GLN_RXP PETN/GLN_TXN PETP/GLN_TXP SPI_LK SPI_S# E SPI_S# SPI_MOSI F SPI_MISO J O# G O#/GPIO G O#/GPIO E O#/GPIO F O#/GPIO G O#/GPIO O#/GPIO J O#/GPIO O# H O# SPI US NHHM-SLQ-MM# MIRXN V MIRXP V MITXN U MITXP U MIRXN Y MIRXP Y MITXN W MITXP W MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MI_LKN T MI_LKP T MI_ZOMP Y MI_IROMP Y USPN G USPP G USPN H USPP H USPN H USPP H USPN J USPP J USPN K USPP K USPN K USPP K USPN L USPP L USPN M USPP M USPN M USPP M USPN N USPP N USRIS# F USRIS F MI_OMP USRIS Short F and F at the package and keep length to less than mils. Trace Impedance should be ohms +/- %. MI_MTX_IRX_N MI_MTX_IRX_P MI_MRX_ITX_N MI_MRX_ITX_P MI_MTX_IRX_N MI_MTX_IRX_P MI_MRX_ITX_N MI_MRX_ITX_P MI_MTX_IRX_N MI_MTX_IRX_P MI_MRX_ITX_N MI_MRX_ITX_P MI_MTX_IRX_N MI_MTX_IRX_P MI_MRX_ITX_N MI_MRX_ITX_P LK_PIE_IH# LK_PIE_IH R./F IH_USP- IH_USP+ IH_USP- IH_USP+ IH_USP- IH_USP+ IH_USP- IH_USP+ IH_USP- IH_USP+ IH_USP- IH_USP+ IH_USP- IH_USP+ IH_USP- IH_USP+ IH_USP- IH_USP+ IH_USP- IH_USP+ R./F PIE_RX+ PIE_RX+ PIE_RX- PIE_RX+ +.V_PIE_IH Place within mils of IH Side pair Top / left Side pair bottom / right Pair top / left Pair bottom / right amera Mini ard (WWN) Mini ard (WPN) Express ard For E test use ET ET ET ET ET ET ET ET ET Mini ard (WLN) iometric. PI Pullups PI_STOP# PI_EVSEL# PI_REQ# PI_PIRQ# +.V_RUN PI_REQ# PI_PLOK# PI_PERR# +.V_RUN RP.KX RP.KX +.V_RUN PI_FRME# IH_IRQH_GPIO PI_TRY# PI_SERR# +.V_RUN PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_IRY# PI_[..] T PI_PIRQ# PI_PIRQ# T PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# U E E G F E E E E PI REQ# GNT# REQ#/GPIO GNT#/GPIO REQ#/GPIO GNT#/GPIO REQ#/GPIO GNT#/GPIO /E# /E# /E# /E# IRY# PR PIRST# EVSEL# PERR# PLOK# SERR# STOP# TRY# FRME# PLTRST# PILK PME# Interrupt I/F F PIRQ# PIRQ# PIRQ# PIRQ# PIRQE#/GPIO PIRQF#/GPIO PIRQG#/GPIO PIRQH#/GPIO NHHM-SLQ-MM# PI_REQ# PI_GNT# E PI_REQ# PI_GNT# S_WWN_PIE_RST# F PI_GNT# S_LOM_PIE_RST# PI_GNT# E F E PI_IRY# G PI_RST#_G PI_EVSEL# PI_PERR# PI_PLOK# F PI_SERR# PI_STOP# PI_TRY# PI_FRME# G PI_PLTRST# LK_PI_IH G F S_WPN_PIE_RST# G S_WLN_PIE_RST# F S_N_PIE_RST# IH_IRQH_GPIO PI_REQ# PI_GNT# T T S_WWN_PIE_RST# T S_LOM_PIE_RST# T PI E# PI E# PI E# PI E# PI_IRY# PI_PR PI_EVSEL# PI_PERR# PI_PLOK# PI_SERR# PI_STOP# PI_TRY# PI_FRME# LK_PI_IH IH_PME#,. S_WPN_PIE_RST# S_WLN_PIE_RST# S_N_PIE_RST# T For E test use ET ET ET ET ET ET ET ET ET ET ET ET ET ET ET PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_IRY# PI_TRY# PI_FRME# PI_STOP# PI_EVSEL# PI_GNT# PI_REQ# PI_GNT# away override strap. Low = swap override enabled. S_N_PIE_RST# High = efault. R *K_N LK_PI_IH R *_N *.P_N Reserved for EMI.Place resister and cap close to IH. Non-iMT PI_RST#_G PI_PLTRST# S_WPN_PIE_RST# S_WWN_PIE_RST# S_WLN_PIE_RST# S_LOM_PIE_RST# S_N_PIE_RST# IOS should not enable the internal GPIO pull up resistor..u.u +.V_SUS U +.V_SUS QUNT OMPUTER IH-M (US,MI,PIE,PI) R R R R R dd uffers as needed for Loading and fanout concerns. TSZFU(TL,F,T) U TSZFU(TL,F,T) PI_RST# K K K K K PLTRST#,,,,,, Size ocument Number Rev FM ate: Tuesday, November, Sheet of

+.V_SUS RP Non-iMT IH_SMT IH_SMLK Place these close to IH. Non-iMT +.V_SUS IH_SMLK R IH_SMLINK IH_SMT R IH_SMLINK +.V_RUN +.V_RUN +.V_RUN R.K LKRUN# IH_SMLINK IH_SMLINK Option to " isable " clkrun. Pulling it down will keep the clks running. R.KX RP R R R R *KX_N R *_N R R SF. *.K_N IMVP_PWRG K K K US_MR_ET# US_MR_ET# PIE_MR_ET# PIE_MR_ET# PIE_MR_ET# R *K_N MH_IH_SYN#_R R K IRQ_SERIRQ R K THERM_LERT# +.V_SUS,, IH_SMLK,, IH_SMT T T T PM_MUSY# H_STP_PI# H_STP_PU#, LKRUN#,,, PIE_WKE#, IRQ_SERIRQ THERM_LERT#,, IMVP_PWRG MH_IH_SYN#. T ITP_RESET# US_MR_ET# SPKR IH_RSV +.V_RUN IH_SMLK IH_SMT RSV_IH_L_RST# IH_SMLINK IH_SMLINK IH_RI# RSV_LPP# LKRUN# PIE_WKE# IRQ_SERIRQ THERM_LERT# IMVP_PWRG SPKR SPKR No Reboot strap. Low = efault. SPKR High = No Reboot. Non-iMT R *K_N RSV_IH_L_RST# R R R K K K IH_RI# SIO_EXT_SI# PIE_WKE# T R R *K_N SMbus address These are for backdrive issue. +.V_RUN +.V_RUN LK_IH_M LK_IH_M IH_SUSLK IH_TLOW# RSV_IH_LN_RST# IH_RSMRST# IH_L_PWROK RSV_IH_L_LK RSV_IH_L_T L_VREF L_VREF RSV_GPIO RSV_GPIO RSV_WOL_EN,, IH_SMT MEM_ST Q NW--F +.V_RUN RP.KX Non-iMT LK_IH_M LK_IH_M SIO_SLP_S# T SIO_SLP_S# IH_PWRG, PRSLPVR, +.V_SUS SIO_PWRTN# IH_RSMRST# LK_PWRG IH_L_PWROK, L_LK T L_T T IH_L_RST# +.V_SUS UM Package:R- iscrete Package: R Non-iMT Non-iMT LK_IH_M LK_IH_M IH_PWRG PRSLPVR R R K K IH_RSMRST# R *K_N RSV_IH_LN_RST# R K IH_L_PWROK R M +.V_SUS RSV_GPIO R K +.V_RUN +.V_SUS L_VREF L_VREF +.V_SUS R R R K K K SIO_EXT_SMI# US_MR_ET# RSV_WOL_EN.,, IH_SMLK U J SMLK SMT G LINKLERT# SMLINK E SMLINK F F SUS_STT#/LPP# SYS_RESET# G MUSY#/GPIO US_MR_ET# G SMLERT#/GPIO E STP_PI#/GPIO G STP_PU#/GPIO H LKRUN#/GPIO E WKE# F SERIRQ THRM# J J J RI# VRMPWRG US_MR_ET# US_MR_ET# J US_MR_ET# TH/GPIO US_MR_ET# J TH/GPIO SIO_EXT_WKE# H SIO_EXT_SMI# TH/GPIO SIO_EXT_SMI# E SIO_EXT_SI# GPIO. SIO_EXT_SI# GPIO T G PIE_MR_ET# R TH/GPIO PIE_MR_ET# H PIE_MR_ET# GPIO PIE_MR_ET# E PIE_MR_ET# GPIO PIE_MR_ET# G SLOK/GPIO WLN_RIO_IS# H QRT_STTE/GPIO MER_L_ET# PLTRST_ELY# QRT_STTE/GPIO *K_N ST_LKREQ# G PLTRST_ELY# STLKREQ#/GPIO. T F SLO/GPIO WPN_RIO_IS_MINI# J STOUT/GPIO WWN_RIO_IS# STOUT/GPIO K K TP SPKR MH_IH_SYN#_R J MH_SYN# TP SM ST GPIO locks SYS GPIO Power MGT MIS GPIO ontroller Link NHHM-SLQ-MM# STGP/GPIO J STGP/GPIO J STGP/GPIO F STGP/GPIO G LK G LK G SUSLK SLP_S# G SLP_S# F SLP_S# S_STTE#/GPIO PWROK E IH_PWRG PRSLPVR PRSLPVR/GPIO J TLOW# PWRTN# LN_RST# RSMRST# K_PWRG LPWROK SLP_M# H E H G E E J L_LK F L_LK E L_T F L_T F L_VREF L_VREF H L_RST# J MEM_LE/GPIO J ME_E_LERT/GPIO J E_ME_LERT/GPIO F WOL_EN/GPIO G R.K T R.K R.K T T T T T T.U R.K/F R /F *.U_N R *_N *.P_N R *_N *.P_N R *.K/F_N R */F_N Q NW--F MEM_SLK QUNT OMPUTER IH-M (PM,GPIO,SM,L) Size ocument Number Rev FM ate: Wednesday, November, Sheet of

+IH_VREF_SUS +IH_VREF_RUN +.V_MIPLL TP_VSUS._ TP_VSUS._ TP_VSUS._ TP_VSUS._ +VSUS_[~] TP_VL. +VL_ +VSTPLL +VSTPLL_L +VSTPLL TP_VSUSLN TP_VSUSLN +.V_MIPLL_R +VSUS_[~] +.V_VP +.V_RUN +.V_SUS +.V_RUN +V_RUN +V_SUS +.V_SUS +RT_ELL +.V_RUN +.V_VP +.V_SUS +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_PIE_IH +.V_RUN +.V_RUN +.V_PIE_IH +.V_VP +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_VP Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM IH-M (POWER,GN) Sunday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM IH-M (POWER,GN) Sunday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM IH-M (POWER,GN) Sunday, November, uh+-%_m F_ohm+-%_mHz_._. ohm uh+-%_m Non-iMT Non-iMT Non-iMT Non-iMT Non-iMT WWN Noise - IH improvements WWN Noise - IH improvements Place,, close to /..U.U *.U_N *.U_N R R.U.U U U *U_N *U_N.U.U L uh L uh.u.u U U U U R R ORE VGP TX RX IE US ORE PI GLN POWER VP_ORE VPSUS VPUS UF NHHM-SLQ-MM# ORE VGP TX RX IE US ORE PI GLN POWER VP_ORE VPSUS VPUS UF NHHM-SLQ-MM# VREF[] VREF[] T VREF_SUS G V [] V [] V [] V [] V [] V [] V [] V [] V [] E V [] E V [] E V [] F V [] F V [] G V [] H V [] H V [] J V [] J V [] K V [] K V [] L V [] L V [] L V [] M V [] M V [] N V [] N V [] N V [] P V [] P V [] R V [] R V [] R V [] R V [] T V [] T V [] T V [] T V [] T V [] U V_[] F VMIPLL R V [] E V [] F V [] G V [] H V [] J VSTPLL J V_[] V [] V [] V [] V [] V [] VUSPLL VLN_[] F VLN_[] G V_[] V_[] V_[] V_[] V_[] V_[] E V_[] F V_[] G V_[] L V_[] L V_[] L V_[] L V_[] L V_[] L V_[] M V_[] M V_[] P V_[] P V_[] T V_[] T VLN_[] F VLN_[] G VH VSUSH V_PU_IO[] V_PU_IO[] V_[] V_[] U V_[] V V_[] W V_[] W V_[] W V_[] Y V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] E V_[] E V_[] F VRT VSUS_[] VSUS_[] VSUS_[] VSUS_[] G VSUS_[] H VSUS_[] P VSUS_[] P VSUS_[] VSUS_[] N VSUS_[] P VSUS_[] P VSUS_[] P VSUS_[] P VSUS_[] P VSUS_[] R VSUS_[] R VSUS_[] R V [] V [] V [] V [] V [] G V [] G VSUS_[] J VSUS_[] F V [] F V [] L V [] L V [] M V [] M VSUS_[] V_[] V [] W V_[] U V_[] V V_[] V V_[] V V_[] U V_[] V V_[] V V_[] V VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_ VGLNPLL V_[] F V_[] V_[] E V_[] VSUS_[] R V [] H VSUS_[] V [] V [] VSUS_[] J V_MI[] E V_MI[] E VL_ G VL_[] G VL_[] F VL_ V [] W V [] V V [] U V [] Y V [] V V [] V + U + U U U.U.U U U.U.U SMKL--F SMKL--F U U.U.U.U.U.U..U..U.U.U.U U U.U.U.U.U U. U. T T *.U_N *.U_N.U.U U U.U.U T T SMKL--F SMKL--F.U.U R R.U.U.U.U.U.U T T U U.U.U T T UE NHHM-SLQ-MM# UE NHHM-SLQ-MM# VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E VSS[] E VSS[] VSS[] E VSS[] E VSS[] E VSS[] E VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] F VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] J VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E VSS[] E VSS[] F VSS[] E VSS[] F VSS[] F VSS[] F VSS[] G VSS[] E VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] H VSS_NTF[] H VSS_NTF[] J VSS_NTF[] J VSS_NTF[] J VSS_NTF[] J VSS_NTF[] VSS_NTF[] VSS[] VSS[] VSS[] VSS[] VSS[] U VSS[] K VSS[] W.U.U *.U_N *.U_N T T/R T T/R.U.U T T.U.U.U.U L LMPGSN L LMPGSN R R.U.U *.U_N *.U_N.U.U T T.U.U R R L uh L uh.u.u U. U..U.U *.U_N *.U_N T T.U.U

R M R M R QS R QS# R M R M R M R R QS R R M R M R M R M R QS# R M R QS R S R WE# R M R M R M R S# R QS# R R M R R M R QS# R M R M R R R QS R R QS R R R R R QS# R QS R R R QS# R M_OT M_OT R S R QS# R QS R QS# R R RS# R R R R M R R QS R R R M R R R R R R M R M R M R S R QS R M R M R M R QS R QS R M R QS# M_OT R M R QS# R M R M R M_OT R QS# R QS# R R M R S R QS# R R M R QS R WE# R M R M R M R M R QS R RS# R M R QS# R R M R S R M R S R QS R R R QS# R R R QS R QS R M R R R S# R M R R QS# R M R M R R M R M MEM_SLK MEM_ST MEM_ST MEM_SLK PM_EXTTS# PM_EXTTS# R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R QS#[..] R [..] R M[..], R M[..] R QS[..] R_S_IMM#, R_S_IMM#, R QS#[..] R [..] R M[..], R S, R M[..] M_OT, M_LK_R R RS#, R QS[..] R_S_IMM#, R_S_IMM#, R S, R RS#, R_KE_IMM, R S, R_KE_IMM, R S, M_LK_R# M_LK_R PM_EXTTS# MEM_ST MEM_SLK R S#, R S, R WE#, R_KE_IMM, M_OT, R S#, R WE#, R S, R_KE_IMM, M_OT, M_LK_R# M_OT, M_LK_R M_LK_R# M_LK_R# M_LK_R PM_EXTTS# R M, R M, +.V_SUS V_R_MH_REF +.V_RUN +.V_SUS +.V_SUS V_R_MH_REF +.V_SUS +.V_RUN V_R_MH_REF V_R_MH_REF +.V_RUN +.V_SUS +.V_SUS +.V_SUS +.V_SUS +.V_RUN +.V_RUN Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM R SO-IMM (P) X Tuesday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM R SO-IMM (P) X Tuesday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM R SO-IMM (P) X Tuesday, November, LOK, LOK, SMbus address SMbus address KE, KE, Place these aps near So-imm. Place these aps near So-imm. TOP OT Place these aps near So-imm. Place these aps near So-imm. is required to route to Top SoIMM for MTto function. h. SOIMM needs to be populated for Intel MT support. Non-iMT Non-iMT Non-iMT Non-iMT Non-iMT R K R K.U..U. R K R K.U.U.U.U.U.U P R SRM SO-IMM (P) JIM P R_ P R SRM SO-IMM (P) JIM P R_ VREF VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS KE V N _ V V V /P WE# V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS Q Q VSS M VSS Q Q VSS Q Q VSS M VSS K K# VSS Q Q VSS VSS Q Q VSS N M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS KE V V V V RS# S# V OT V N VSS Q Q VSS M VSS Q Q VSS Q Q VSS VSS M VSS Q Q VSS Q Q VSS NTEST VSS QS# QS VSS Q Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS Q Q VSS Q Q VSS K K# VSS M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS S S VSS.U..U..U.U.U.U R K R K P R SRM SO-IMM (P) JIM R_IMM P R SRM SO-IMM (P) JIM R_IMM VREF VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS KE V N _ V V V /P WE# V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS Q Q VSS M VSS Q Q VSS Q Q VSS M VSS K K# VSS Q Q VSS VSS Q Q VSS N M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS KE V V V V RS# S# V OT V N VSS Q Q VSS M VSS Q Q VSS Q Q VSS VSS M VSS Q Q VSS Q Q VSS NTEST VSS QS# QS VSS Q Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS Q Q VSS Q Q VSS K K# VSS M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS S S VSS.U..U..U..U..U..U..U..U..U.U + *U_N. + *U_N..U..U..U.U.U..U..U.U.U.U.U..U..U..U..U.U.U..U. R K R K.U..U..U..U..U.U.U..U..U.U

+.V_R_VTT TOP Layout note: Place cap close to every R-pack terminated to SMR_VTERM..U.U.U.U.U.U.U.U.U.U.U.U.U.U +.V_R_VTT OT.U.U.U.U.U.U.U.U.U.U.U.U.U.U +.V_R_VTT, R M[..] R M[..], R M R M RP RP R M R M R M R M x RP x RP R M R M, R RS#, R S, M_OT, R S R RS# R S R M M_OT R S R M x RP x RP x RP x RP x RP x RP R RS# R S M_OT R M R M R M R RS#, R S, M_OT, Please these resistor closely IMM,all trace length< mil. R M R M R M R M x RP x RP x RP x RP R M R M R M R M Please these resistor closely IMM,all trace length< mil., R S, R S#, R WE# R M R S R S# R WE# R M R M x RP x RP x RP x RP x RP x RP R WE# R S R S# R M R M R M R WE#, R S, R S#,, M_OT, R_S_IMM#, R_S_IMM#, R_KE_IMM, R_KE_IMM, R M x R R M R R R R R R x R R R R R R R M_OT, R S, R_S_IMM#, R_S_IMM#, R_KE_IMM, R_KE_IMM, R M, QUNT OMPUTER R RES RRY Size ocument Number Rev FM ate: Tuesday, November, Sheet of

dd capacitor pads for improving WWN. P *P_N *P_N LK_IH_M LK_IH_M LK_PI_ *P_N LK_PI_PR *P_N LK_PI_IH LK_XTL_IN P ST_LKREQ# LK_GPLLREQ# LK_LP_EUG LK_PI_PR LK_PI_ LK_PI_IH LK_IH_M, PU_MH_SEL, PU_MH_SEL, PU_MH_SEL LK_IH_M LK_PWRG.MHz +.V_RUN L LMPGSN ohms@mhz.u L LMPGSN ohms@mhz Y LK_XTL_OUT.MHZ ST_LKREQ# LK_GPLLREQ# LK_LP_EUG LK_PI_PR LK_PI_ LK_PI_IH. R *_N R R R LK_IH_M R L R.K LMGSN R.K L R.K LMGSN LK_IH_M R.U R. R. R. P +K_V_MIN +K_V_PI +K_V_PLL +K_V_ R /F R /F.U.U.U +K_V_PI +K_V_PLL +K_V_ +K_V_SR +K_V_MIN ST_LKREQ#_ LK_GPLLREQ#_ PI_PR PI_SIO M_SEL PI_IH FS FS FS LK_XTL_OUT LK_XTL_IN LK_ST LK_SLK UM without imt.u.u.u..u.u *U_N. U V_PI V_REF V_PLL V_ V_SR V_PU V_IO V_IO V_IO V_IO V_IO V_IO GN GN GN GN GN GN GN GN GN R#_/PI- R_/PI- TME/PI- SR_EN/PI- M_SEL/PI- ITP_EN/PIF-# FS/US FS/TEST_MOE FS/TEST_SEL/REF RESET# K_PWRG/P# XOUT XIN ST SLK SLGSPV These are for backdrive issue.,, SMT K QFN LK_ITP_LK# LK_ITP_LK SMbus address SR-/PU_ITP SR-#/PU_ITP# SR-/OT SR-#/OT# SR-/SE SR-#/SE SR-/ST SR-#/ST# R#_/SR- R#_/SR-# +.V_RUN Q NW--F PU- PU-# PU- PU-# SR- SR-# PI_STOP#/SR- PU_STOP#/SR-# SR- SR-# R#_F/SR- R#_E/SR-# SR- SR-# SR- SR-# R#_H/SR- R#_G/SR-# +.V_RUN GN RP *x_n PU_LK PU_LK# MH_LK MH_LK# PIE_MINI PIE_MINI# OT_SS OT_SS# M_SS M_NSS PIE_ST PIE_ST# PIE_MINI PIE_MINI# MH_GPLL MH_GPLL# PIE_EXPR PIE_EXPR# MINILK_REQ#_ R_LK_REQ#_ PIE_MINI PIE_MINI# PIE_IH PIE_IH# PIE_LOM PIE_LOM# LK_ST PIE_MINI# PIE_MINI Non-iMT RP.KX PI_IH M_SEL RP x RP x RP x RP x R /F R /F RP x RP x RP x RP x RP x RP x RP x RP x +.V_RUN +.V_RUN MINILK_REQ# R_LK_REQ# R *K_N R *K_N R POP: For Internal pull-low. R POP: For internal pull-high. R *K_N M_SEL M_SEL (PIN) =UM = isc. GRFX down LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# LK_PIE_MINI LK_PIE_MINI# REF_SSLK REF_SSLK# MH_REFLK MH_REFLK# LK_PIE_ST LK_PIE_ST# LK_PIE_MINI LK_PIE_MINI# LK_MH_GPLL LK_MH_GPLL# H_STP_PI# H_STP_PU# LK_PIE_EXPR LK_PIE_EXPR# MINILK_REQ# R_LK_REQ# LK_PIE_MINI LK_PIE_MINI# LK_PIE_IH LK_PIE_IH# LK_PIE_LOM LK_PIE_LOM# OTT SRT LK_GPLLREQ# ST_LKREQ# R_LK_REQ# MINILK_REQ# PI_PR PI_SIO OT SR H_STP_PI# H_STP_PU# FS FS FS PU SR PI Silego need pull up but other? R *K_N R R R R R R R RSV PIN PIN PIN PIN / M_T Mout K K K K *K_N / M_ MSSout *K_N *K_N +.V_RUN +.V_RUN R. +K_V_SR.U,, SMLK Q NW--F LK_SLK R K QUNT OMPUTER LOK GENERTOR Size ocument Number Rev FM ate: Tuesday, November, Sheet of

+.V_RUN R.K R.K.. SVO_TRLLK SVO_TRLT HMI_LK+ HMI_TX+ HMI_TX+ HMI_TX+ R R R R HMI_LK_.U HMI_LK- HMI_TX_.U HMI_TX- HMI_TX_.U HMI_TX- HMI_TX_.U HMI_TX- HMI_TX+ HMI_TX- HMI_LK+ HMI_LK- HMI_TX+ HMI_TX- HMI_TX+ HMI_TX- HMI_ET R K HMI_ET_R HMI onnector +V_RUN R.K +V_RUN HMI_TX+_ HMI_TX-_ SMK--FHMI_TX+_ R.K F HMI_TX-_ HMI_TX+_ HMI_TX-_ HMI_LK+_ HMI_LK-_ HMI_SL HMI_S PJP SHORT HMI_ET_R N SHELL + Shield - + Shield - + Shield - K+ K Shield K- E Remote N LK T GN +V HP ET SHELL -HM--K. EXT_SWING R /FV *SMPTS_N HMI_TX+ HMI_TX- HMI_TX+ HMI_TX- SVO_INT+ SVO_INT- SVO_RE+ SVO_RE- SVO_GREEN+ SVO_GREEN- SVO_LUE+ SVO_LUE- SVO_LK+ SVO_LK-,,,,,, PLTRST# SVO_TRLLK SVO_TRLT L LWSNSQ R *_N R *_N L HMI_TX+_ HMI_TX-_ HMI_TX+_ HMI_TX-_.U.U R SVO_TRLLK SVO_TRLT R K S_INT+ S_INT- K EXT_RES HMI_ U TX+ TX- TX+ TX- SR+ SR- SI+ SI- SG+ SG- S+ S- S+ S- EXT_RES RESET# SSL SS HMI_S HMI_SL S SL SLROM SROM TEST HLK HV TX+ TX- TX+ TX- SiI HRST HSI HSYN SPIF/HSO LSL LS LINT# HTPLG EXT_SWING V V V V V GN GN V V GN GN GN OV PV PV V. RSV SV SV GN GN SGN SGN SPV SPGN GN SIINU V_PWR V OV PV PV VV V_PWR SV P SPV P P P P P P P P L LMS.U P U L LMS U U L LMS.U P U L LMS P U.U +.V_RUN +.V_RUN +.V_RUN +.V_RUN.U.U *.U_N L +.V_RUN LMPGSN U PV.U P PV.U P VV.U P L LMS U L LMS U +.V_RUN +.V_RUN. L LMS +.V_RUN U P LWSNSQ R *_N IH_Z_HMI_ITLK R.K +.V_RUN HMI_TX+ HMI_TX- R *_N L LWSNSQ R *_N R *_N HMI_TX+_ HMI_TX-_. HV.U L LMS +.V_RUN IH_Z_HMI_SOUT IH_Z_HMI_SYN IH_Z_HMI_SIN IH_Z_HMI_RST# HMI_LK+ HMI_LK- L LWSNSQ R *_N R *_N HMI_LK+_ HMI_LK-_ QUNT OMPUTER SiI Size ocument Number Rev FM ate: Wednesday, November, Sheet of

LNK PGE FOR PGE NUMER SME S ISRETE QUNT OMPUTER Size ocument Number Rev FM ate: Sunday, November, Sheet of

E LNK PGE FOR PGE NUMER SME S ISRETE QUNT OMPUTER Size ocument Number Rev FM ate: Sunday, November, Sheet of E

LNK PGE FOR PGE NUMER SME S ISRETE QUNT OMPUTER Size ocument Number Rev FM ate: Sunday, November, Sheet of

E LNK PGE FOR PGE NUMER SME S ISRETE QUNT OMPUTER Size ocument Number Rev FM ate: Sunday, November, Sheet of E

E QUNT OMPUTER FLSH, RT & K Size ocument Number Rev FM ate: Sunday, November, Sheet of E

attery Selector QUNT OMPUTER Size ocument Number Rev FM ate: Sunday, November, Sheet of

QUNT OMPUTER ocking Station ONN. Size ocument Number Rev FM ate: Sunday, November, Sheet of

Support the new imbeded diagnostics. ENV LV_TST_EN R *_N T T/R EN_LV +.V_RUN R *K_N +.V_SUS +V_LW +.V_RUN Q FN R K R K LV_ON Q TEU--F R *K_N Q NW--F.U R U +LV J FI-TS-LE L_LK-_ L_LK+_ L_- L_+ L_- L_+ L_- L_+ L_LK-_ L_LK+_ L_- L_+ L_- L_+ L_- L_+ L_LK L_T KLITEON L_- L_+ L_- L_+ L_- L_+ L_- L_+ L_- L_+ L_- L_+ L_LK L_T +.V_RUN +LV L_TST GFX_PWR_SR +LV *P_N +.V_RUN dress : H --ontrast H --acklight SMLK,, SMT,, INVERTER_L_ET# L_K# PWM_VJ L_L_ET# UM Populate R for PST implementation only. Populate R for platform without PST support. No Stuff for iscrete SPT support due to back up plan. I_PWM R +.V_RUN KLITEON Shunt capacitors on LVS for improving WWN. L_LK-_ L_LK+_ L_LK-_ L_- L_- L_- L_- L_- L_- *.P_N L_+ *.P_N L_+ *.P_N L_+ *.P_N L_+ *.P_N L_+ *.P_N L_+ *.P_N L_LK- L_LK+ L_LK- +PWR_SR mil mil GFX_PWR_SR.U Q NW--F.U.U *P_N.U.U R *K_N R *_N R R R R K.U R K Q FP.U L_LK+_ R *_N *.P_N R L_LK+,,,, RUN_ON Q NW--F QUNT OMPUTER L ONN & K-SS Size ocument Number Rev FM ate: Tuesday, November, Sheet of