Lecture 3: Transistor as an thermonic switch 2016-01-21 Lecture 3, High Speed Devices 2016 1
Lecture 3: Transistors as an thermionic switch Reading Guide: 54-57 in Jena Transistor metrics Reservoir equilibrium Thermionic switch basics of transistor operation FET/Bipolar Transistor FET Short channel effects 2016-01-21 Lecture 3, High Speed Devices 2016 2
N-type Field Effect Transistor Large Signal DC I ds =f(v gs,v ds ) +V DS Drain I DS +V gs Gate Source I DS 3
I D (ma/µm) g m (ms/µm) N-type Field Effect Transistor Metrics Output Characteristics Transfer Characteristics Transconductance R on V DS = V DS = g d On-resistancece R on = di dv DS 1 V DS 0V Output conductance di D g d = (ms/µm) dv DS VDS,V GS (Wµm) BV DS V T Threshold voltage V T when the current becomes small V GS g m = di D dv GS VDS,V GS A good FET has: Low R ON, low g d, large g m, V T >0V and a large BV DS Voltage gain requires g m >g d V GS (ms/µm) 4
I D (ma/µm) Log (I D ) N-type Field Effect Transistor Metrics (off-state) Output Characteristics Transfer Characteristics Transconductance V DS =0.8V V DS =0.8V SS V DS =50 mv V DS =50 mv BV DS V T Threshold voltage V GS V GS I D below V T :Sub threshold current Ideal inverse subthreshold slope: kt q log 10(e) 60 mv/decade Drain Induced barrier lowering DIBL (mv/v) A FET for digital applications has: SS ~60mV/decade Small DIBL (10-40mV/V) 5
Npn Bipolar transistor Large Signal DC I ds =f(v BE,V CE ) Collector I B I C V BE Base Emitter I E =I C +I B 6
Npn Bipolar transistor Metrics Collector current density: J C (ma/µm 2 ) g m follows from I C : g m = I C V t Output conductance:g d (ms/µm 2 ) HBTs are rarely operated at low V DS -> R on usually not important. Current gain: β F = δi C δi B A good HBT has: Very low g d, large J C, large b F large BV DS Voltage gain requires g m >g d 7
Ohmic contact - Reservoir Metal n ++ semiconductor Lightly doped semiconductor +V S E F Ideal ohmic contact Reservoir for electrons E C E v The applied bias sets the metal fermi level with respect to ground. (Electric potential <-> ) An ideal ohmic contact keeps the semiconductor in (Gibbs) equilibrium with the metal <-> Equal E F The n++ doping keeps the semiconductor bands flat for moderate current densities ( de f dx = J μ n n ) 8
n + - i n + Resistor: ballistic current n ++ Lightly doped semiconductor n ++ +0 V v X = ħk x m E Positive current: k x >0 Negative current: k x <0 k x E F,L E F,R If no scattering electrons flowing from left to right have positive k x electrons flowing from right to left have negative k x No current flows: +k x and -k x are equally occupied! 9
n + - i n + Resistor: ballistic current n ++ Lightly doped semiconductor n ++ +V D v X = ħk x m E Positive current: k x >0 Negative current: k x <0 k x E F,L qv D E F,R An applied bias lowers the drain reservoir by qv D +k x is populated by E F,L. k x is populated by E F,R. This leads to a net electron current from left to right E F,R = E F,L qv D 10
General Transistor Model Source Emitter V BE n ++ Channel/Base n ++ Drain Collector V DS V CE V GS Ideal transistor the potential energy of the channel is only controlled by the gate/base terminal. HBT direct control of E C,channel FET indirect control of E C,channel E F,L E F,R E C 11
General Transistor Model V GS =0.4V V DS =0V E C V GS =0.4V V DS =0.1V E C V GS =0.4V V DS =0.4V V GS =0.6V V DS =0.4V V GS =0.1V V DS =0.4V E C E C E C 12
Bipolar Transistor Realization V BE V CE n ++ p+ n ++ The base is a p+ region The base terminal is connected directly to the base No e-field Diffusion with recombination Recombination: base current This constitutes a reservoir for holes not for electrons V CE J E n n 0 τ J C E C +V CE V BE V BE 13
Field Effect Transistors - realization +V GS +V DS +V GS +V DS Insulator n ++ n ++ p Traditional Si-MOSFET +V GS +V DS Insulator/WB n ++ QW n ++ Wide Bandgap/insulator Quantum Well HEMT /SOI MOSFET/ Graphene FET +V GS +V DS n ++ Wide Bandgap n ++ Insulator/WB n ++ QW / Nanowire n ++ Small Bandgap (i) Insulator/WB Traditional HEMT +V GS FinFET / Nanowire FET / Carbon Nanotube FET 14
Field Effect Transistors indirect channel potential control x y Positive V GS NegativeV GS Positive V GS NegativeV GS y x 15
Field Effect Transistors indirect channel potential control Long channel FET diffusive: potential drop along the channel required. J drift = qμ n n x ε x = μ n n x de c dx Channel potential not 100% controlled by the gate complicates things. n(x) decreases -> pinch off. 16
Field Effect Transistors subthreshold current E 1 E FL When E 1 >> E F,L Exponential tail of Fermi-Dirac function: Current decreases exponentially with increasing E 1 This gives ideally a 60 mv / decade slope Theoretical limit for a thermionic switch F j E F E 1 kt e (E F E 1 )/kt 10 5 on-off ratio: at least 0.3 V GS 17
Field Effect Transistors indirect channel potential control Ballistic FET diffusive: No potential drop along the channel is required Ideal gate control sets the potential in the channel Source/Drain electrodes injects electrons Short channel effects large a drain potential can pull down E1 output conductance 18
Field Effect Transistors Short Channel Effects 1) We want the channel potential to be set by the gate voltage. 2) When the current through the transistor is small very little charge inside the channel. ρ 0 C/m 2. (For simplicity here) V S V G V D ε r ε 0 V = 0 3D Possion equation 3) Both drain, source and gate terminal can influence the potential inside the channel! 4) This is studied by solution to the 2D Possion Equation. ε r ε 0 V = 0 19
Analogue: Thermal Conduction x T=+25 C l 1 t 1 Possion Equation: ε r ε 0 V = 0 T=0 C y 2 T 2 x 2 T 2 y 0 T=0 C The linear differential equation for the steady state temperature field is equivalent to Possions equation! We want the temperature (potential) in the channel to be controlled by the temperature (potential) on the gate electrode and NOT by the drain electrode! This makes it very easy to intuivitely understand how to design an transistor! l 2 t 2 T=-25 C Thermal Conduction: λ T = 0 Temperature <-> Voltage Thermal Conductivity <-> Dielectric Constants 2016-01-21 Lecture 3, High Speed Devices 2016 20
1 minute intuition- geometry T=+25 C T=+25 C (a) t 1 (c) t 1 T=-25 C t 2 T=-25 C t 2 T=0 C T=0 C (b) t 1 t 2 T=+25 C Rank the structures in terms of highest temperature at T=-25 C 2016-01-21 Lecture 3, High Speed Devices 2016 21
1 minute intuition- thermal conductivity T=+25 C T=+25 C (a) l = small T=-25 C (b) l = small T=-25 C l = small l = large T=0 C T=+25 C T=0 C (c) l = large l = small l: thermal conductivity Rank the structures in terms of highest temperature at T=0 C 2016-01-21 Lecture 3, High Speed Devices 2016 22
Laplace s Equation is linear 0V -0.5V -0.5V 0.5V 0V 0V 0V 0V 0.5V 2 x 2 + 2 y 2 αφ = α 2 x 2 + 2 y 2 Φ = 0 The potential at a certain point: Φ x, y = α G (x, y)v G +α D (x, y)v D + α S (x, y)v S 0< α G, D, S < 1 x,y dependence from solution of Laplace s equation 2016-01-21 Lecture 3, High Speed Devices 2016 23
Potential Distribution V=-0.5 l l 2016-01-21 Lecture 12, High Speed Devices 2014 24
Potential Distribution Ground plane FET V=-0.5 V=0 V=0.0 Ground Plane V=0.0 2016-01-21 Lecture 12, High Speed Devices 2014 25
Potential Distribution Double gate FET V=-0.5 V=0 V=0 V=-0.5 2016-01-21 Lecture 12, High Speed Devices 2014 26
Potential Distribution Double gate FET V S V D t s t i ε r ε 0 V = 0 This can be solved easily with e.g. COMSOL. t i Analytical solution through separation of variables + Fourier series expansion. Analytic solution: V x V GS + V GS sinh π L x λ / sinh πl λ + (V DS + V GS ) sinh π L x λ / sinh πl λ λ t s + 2t i λ t s If eri=ers If eri>>ers Geometric Length Scale for the FET 2016-01-21 Lecture 3, High Speed Devices 2016 27
Short Channel Effects L=20 nm l=10 nm L=50 nm l=10 nm L=30 nm l=10 nm Double Gate λ t s + 2t i L > 2l Short gate lengths requires thin oxide and thin semiconductors λ GAA < λ DG < λ SG Gate All Around Single Gate FinFETs/Nanowire: thicker t i /t s for the same gate length 2016-01-21 Lecture 3, High Speed Devices 2016 28