Electromigration in Lead-free Solder Joints under High Frequency Pulse Current: an Experimental Study

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Electromigration in Lead-free Solder Joints under High Frequency Pulse Current: an Experimental Study Wei Yao 1 and Cemal Basaran 1* 1 Electronic Packaging Laboratory, University at Buffalo, The State University of New York, Buffalo, NY 14260 *Corresponding Author: cjb@buffalo.edu ABSTRACT The insatiable demand for miniaturization of consumer electronics has brought continuing challenges in the electronic packaging field. As a consequence, immense information processing duties, high current density and large joule heating are exerted on the package, which makes electromigration and thermomigration a serious reliability issue. In this study, high frequency pulse current electromigration degradation experiments were carried out on Sn96.5%Ag3.0%Cu0.5 (SAC305- by weight) solder joints. During the test, frequency, current density and duty factors are used as controlling parameters. The nominal current density varied from 1.0 10 5 A/cm 2 to 2.1 10 5 A/cm 2, PDC frequency ranged from 2 MHz to 10 MHz, and duty factor varied between 30% and 80% with a controlled ambient temperature at 70 C. It was observed that Mean Time to Failure (MTTF) was inversely proportional to the current density and duty factor. Higher frequency leads to a shorter lifetime within the frequency range we studied. SEM image shows that damage develops at both current crowding corners and the skin layer of solder joints. A mean time to failure relationship of lead-free solder joints under pulsed current loading is proposed based on the experimental data. [Keywords: PDC Electromigration, SEM, SAC Solder Joint, Mean Time to Failure, Solder Joint Resistance] 1

INTRODUCTION There always has been and will continue to be motivation to pack more electronic functionalities and better performance into a smaller volume of space. Due to this insatiable trend in microelectronic devices, Ultra-large-scale-integration (ULSI) interconnect and solder joint sizes reduces continuously to enable a higher degree of integration. As a result of transferring more data through reduced devices size, average current density carried by solder joints has increased from 10 3 A/cm 2 to 10 5 A/cm 2. Owing to the geometry of solder joint connections, significant current crowding exists at Al/Cu trace interconnecting solder bump areas. It induces more serious electromigration damage, and another byproduct, highly localized joule heating. Hot spots are thus induced and cause intense signal delay in high speed switching device, especially the complementary metal-oxide-silicon (CMOS) ICs. Both high current density and joule heating make electromigration (EM) and thermomigration a reliability issue for solder joints [1-7]. Mass diffusion mechanism of conductors under electric current loading has four driving forces: electric wind force, chemical potential, thermal gradient and stress gradient [8, 9]. When subjected to Direct Current (DC) loading, electric wind force drives ions to diffuse from the cathode side of conductors to the anode side; joule heating induced thermal gradient transports atoms from hot spots to their surrounding areas; chemical potential and stress gradient drive mass to diffuse in the opposite direction of the electron wind force. Net effect acting in this mass transport process moves ions from the cathode side toward the anode side of conductors [10, 11]. As a result, mass accumulation induces local compression on the anode side, which eventually squeezes mass out of the material surface to form protrusions or hillocks [12-14]. It causes a short- 2

circuit failure. While on the cathode side, voids growth causes increased local resistivity and current crowding, eventually open-circuit failure. Anode side short-circuit failure is effectively reduced due to polymer filling between conductors and minimum pitch specified in the electronic packaging process. The cathode side open-circuit becomes a major failure phenomenon that this study and the field of electronic packaging are concerned with [15]. Although most electronic applications, especially power switching and digital circuitry in chips, involve pulse rather than continuous signals, previous studies focused mainly on EM in direct current (DC) bias [16-33]. EM under pulse current loading is different in the sense that there exists a pulse-off time every loading period. Lifetime of solder joints is longer than those subjected to DC loading under otherwise the same conditions [34-39]. Mass transportation mechanism during pulse-on time is exactly the same as in DC loading. During pulse-off time, however, electron wind force vanishes. Under Pulsed Direct Current (PDC) stressing, the electron wind force causes a concentration gradient between the anode and the cathode side of conductors; and then, between current pulses, some of the atoms/vacancies stream back, obeying Fick s conventional law of diffusion. In other words, this self-healing effect during load-off period could relieve partially the damage caused during previous pulse-on period [40-42]. This mechanism is known as retroactive effect. Current crowding at Cu/Al line and the solder bump intersection causes highly localized joule heating in that region. Although direction of thermal driving force does not change during the pulse history, the amount of joule heating is reduced because of heat dissipation during load-off time. Thanks to retroactive effect and reduced joule heating, lifetime of conductors powered on the PDC 3

is usually longer. For deposited thin film connections, it is observed to be between 1/r [36, 43]and 1/r 2 [34, 44, 45] of DC lifetime at equal peak current densities, with r being the pulse duty cycle. Based on the principle of projecting load-on current to DC current loading at the same peak current density, Schoen [43] proposed a modified Black s time to failure model for thin films to account for the lifetime enhancement of conductors under pulsed current loading. Damage relaxation is found to be a temperature-dependent time constant. However, with the broad adoption of Ball Grid Array (BGA) and Column Grid Array (CGA) in the electronic packaging industry, there are no reported similar studies for solder joints in literature. Due to the obvious different degradation mechanism between metallic thin films and solder alloys, it is clear that accurate data about EM failure of lead-free solder joints under pulse current stressing are required to better predict reliability of electronics and accurate timing of signal transport. EXPERIMENTAL SETUP A. Test Vehicles Electromigration Mean Time to Failure (MTTF) of lead-free solder joints subjected to pulse current loading is investigated experimentally. The specially designed flip-chip package with a schematic cross sectional view of the solder joint is shown in Fig. 1. Lead-free Sn96.5%Ag3.0%Cu0.5 (SAC305- by weight) solder joints connect the chip to Printed Circuit (PC) board. The pitch between adjacent solder bumps is 270 μm. Diameter of solder bump is 112 μm with a 105 μm standoff height. Cu pad of the substrate is surface finished with electroless plated Ni/Au, for which the thickness of Ni is 5 μm while that of Au is 0.05 μm. Diameter of tri-layer Ti/Cu/Ni under bump 4

metallurgy (UBM) is 112 μm with the thickness of 3 μm. The Nitride passivation layer is 1.5 μm thick with a 90 μm opening. Deposited Al thin film connection of 65 μm widths and 1 μm thickness forms circuitry on the silicon die side. Copper trace of 65 μm width and 15 μm thickness of the PC board side contacts the bottom of solder joints. The substrate solder mask opening is 110 μm. Detailed dimension and material finish information of the test vehicle is listed in Table 1. B. Experimental Procedure The most common method used to evaluate EM failure of a solder joint has been to stress it under constant current loading and measure the time required for open-circuit failure to occur. This method is highly impractical in evaluation of damage of solder joints under pulse current loading and even worse when subjected to AC stressing. Awaited to material healing effect, extremely high current density and long loading time are required for open-circuit failure to happen under PDC or AC conditions. The use of resistometric techniques is thus developed for more practical testing [40, 45, 46]. In this technique, increase of conductor resistance is used to monitor in an attempt to detect the formation of mass diffusion damage. This theory is based on the fact that EM induces vacancy formation, which reduces the effective conducting area and results in a higher resistance. In this work, Time to Failure (TTF) is defined as 10% resistance change between minimum and maximum resistance happening during current loading history. The 10% resistance change is adopted because this amount resistance change creates an electrical signal distortion large enough to fail the designed function of most ICs [47]. Scheme of the experimental design is shown in Fig. 2. Pulse generator/power supply outputs signals at designed voltage, frequency and duty cycle. Two multi-meters 5

programmed by a computer server collect resistance reading every 5 seconds by fourwire method shown in Fig 3. Principle of four-wire scheme is: (1) a voltmeter parallel connected to the circuitry measures voltage reading on the conductor; (2) an amp-meter series connected to the circuitry measures current reading; (3) the multimeter then automatically divides voltage by the current reading, and gives the in-situ resistance. Flip-chip package used in this study is specially designed to exclude Cu/Al trace s EM noise from our test. As seen from Fig. 4, pulse current signal flows through two solder joints and one aluminum trace in R1, but only one solder joint and one aluminum trace in R2. To exclude Al/Cu trace s EM damage effect, R1 and R2 are measured at the same time, and the exact resistance of one solder bump is given by R1-R2. One thermometer is programmed to measure temperature on the silicon chip side and PC board side every 30 seconds. The test vehicle was put in a thermal chamber with an ambient temperature of 70 C, which is normal operating temperature of most consumer electronic IC devices. Time varying electric signals lead to a thermal transient in test vehicles. This transient can be substantial for high current densities that it actually affects the mass transport. Thermal relaxation time used to characterize this joule heating induced mass diffusion is in the μs range for SAC alloys. To exclude the thermal transient effect, PDC current stressing with frequencies of 2 MHz to 10 MHz was employed in the test vehicle. Duty factor defined as the time ratio of pulse-on period over one loading period varies from 0.3 to 1.0. Nominal current density, calculated at center cross section of the solder joint, varies from 1.0 10 5 A/cm 2 to 2.1 10 5 A/cm 2. However, the maximum current density is typically one order of magnitude larger. 6

RESULTS AND DISCUSSION Scanning Electron Microscope (SEM) experiments were conducted to investigate the vacancy accumulation and Intermetallic Compound (IMC) growth of our test vehicle. Fig. 5 (a) is an initial profile of the solder joint, while Fig. 5 (b) and (c) correspond to solder joint profiles after 50 hours and 140 hours of PDC current loading at 2 MHz respectively. It can be seen that PDC current loadings introduce vacancy growth in solder joints instead of metal films. Essential voids accumulation is observed at the current crowding corner, which fails the designed function of circuitry. The EM process in aluminum traces initiate at a current density about two orders higher than that of solder joints, which is one of the major reasons why Al instead of copper is used as deposited thin film interconnect in substrate manufacture. We are confident that the resistance comes from the lead-free solder bump instead of the deposited aluminum thin film. The SEM image also shows vacancy development at both current crowding corners and skin layer of the solder joint. This phenomenon is not observed in DC cases [47-50]. When conductors subjected to time varying electromagnetic field, secondary current flow is induced, which alleviates part of current flow at the center of conductors while strengthens it in the skin layer. The net current distributes with the highest value at the skin layer and decreases exponentially toward the center cross section. This phenomenon is referred as skin effect, and causes more damage to skin layer of solder joints than other parts. IMC thickening is observed to grow toward the center of solder joints. A. Effective Resistance Test 7

Instead of being constant, measured resistance is found to be function of current density, duty factor and pulse frequency as shown in Fig. 6. Resistance is observed to grow linearly with larger current density. This agrees with literature observation. Fig. 6 (b) is the frequency dependence of effective impedance. It can be seen that effective impedance is stable from 1 MHz to 10 MHz for tests shown in the figure. It goes down exponentially when we further increase the pulse frequency. Matthiessen s rule states that the total resistance of a sample is the sum of all the individual contributions. Nonlinear regression gives the following relationship between the effective resistance, current density and frequency with a confidence value of 92%, R = α j β f γ + R 0 (1) Where, α = 2.8 10 4 is current density parameter, j is current density in A/cm 2, β = 0.004 and γ = 1.8 are frequency parameters, f is frequency in MHz. As for the duty factor, the exact linear relationship is observed. Larger duty factor results in a higher resistance as showed in Fig. 6 (c). The relationship is given as, R = ε d + θ (2) Where, ε is duty factor parameter and d is the duty factor. Combing equation (1) and (2), resistance versus current density, pulse frequency and duty factor is defined as, R = α j + ε d β f γ + R 0 (3) 8

It can be seen that effective resistance linearly depends on current density and duty factor, but has an exponential relationship with pulse frequency. Parameters α, β, γ and ε are positive and depend on solder alloy material and construction. Due to the varied measured resistance, test data are normalized as R/R0 with respect to the stressing time for comparison purposes. R equals to R1-R2 as shown in Fig. 4, which is the resistance of one solder joint. R0 is the initial value of resistance at 70 C. B. Current Density Dependence of Electromigration MTTF EM is an electric current driving mass transport process. As a consequence, electron wind force is the main material degradation mechanism. Larger current density induces more EM damage, and also leads to an increased resistance [47]. Fig. 7 (a) is the initial temperature profile of solder bump under PDC. It can be seen that joule heating reaches a stable state after about 10 minutes of current loading. Temperature on the silicon chip temperature cycles from 73.5 to 72.8 in a period of 150 s for the rest of the loading history. The actual thermal transient is observed to lag far behind the current loadings, so we are confident that the material degradation results from electromigration rather than thermomigration. Fig. 7 (b)-(e) show resistance evolution in solder joints subjected to current density from 1.3 10 5 A/cm 2 up to 2.1 10 5 A/cm 2, at a constant duty factor of 0.5 and frequency of 4 MHz. Resistance is observed to change up and down continuously with the average value growing during the entire loading history. The reduction in resistance reflects damage healing effect during load-off period. It can be seen that larger current density shortens significantly the lifetime. At a current density of 1.3 10 5 A/cm 2, the solder joint lasts 49 hours before thresh-hold resistance is 9

reached; it lasts 23 hours when the current density is increased to 1.8 10 5 A/cm 2. At a current density of 2.1 10 5 A/cm 2, however, it only takes 0.8 hours for failure to happen. The reduced resistance after failure is due to temperature drop from 70 C to ambient temperature. It s also seen that, at high current density, resistance grows at an almost constant rate due to electromigration with no observable healing, which is typically found in the DC electromigration damage process. All test results are summarized in Table 2. The MTTF data is averaged from several tests with identical controlling parameters. MTTF vs. current density data is plotted in Fig. 8. To obtain a current density dependent MTTF, non-linear regression is performed at a constant duty factor and pulse frequency. With a confidence value of 83.5%, the following relationship is obtained, MTTF = 5.5 10 9 c 1.6 (4) Where MTTF is mean time to failure in hours, and c is the nominal current density in A/cm 2. Lifetime shortens seriously with increased current density at elevated frequency. C. Duty Factor Dependence of Electromigration MTTF Fig. 9 shows resistance evolution of solder joints under PDC loading with the duty factor varying from 30%-80% at a constant current density of 1.3 10 5 A/cm 2 and frequency of 4 MHz. Resistance is observed to fluctuate up and down during the whole loading history. Joule heating is responsible for the initial resistance change as discussed in the above section. After the thermal steady state is reached, EM induced mass transport contributes to the following resistance change. Effective resistance does not grow continuously during the current loading. As discussed above, chemical potential gradient 10

and stress gradient always retard electron wind force driven mass diffusion, and restore partially the mass transportation during load-on time. With a duty factor of 30%, the solder joint fails after 78 hours current loading; it lasts 43 hours when the duty factor is increased to 50%; and only 37 hours at duty factor of 60%. When we increase duty factor to 80%, however, solder joints failed in just 21 hours. It implies an obvious duty factor dependence of MTTF of solder joints. This is important since pulse signals in ICs are rarely symmetrical and within the generality of a design rule the possibility of arbitrary pulse current needs to be considered [45]. Owing to the uneven pulse signals, conductors may fail before their designed lifetime. Curve fitting results of MTTF Vs. duty factor are shown in Fig. 10. Higher duty factor results in a decreased MTTF. Non-linear regression gives the following duty factor dependence of electromigration MTTF of solder joints subjected to PDC with a 97.9% confidence value: MTTF = 18.6 r 1.2 (5) D. Frequency Dependence of electromigration MTTF Frequency dependence of resistance of lead-free solder joints is shown in Fig. 11, with a constant current density of 1.3 10 5 A/cm 2 and duty factor of 50%. The minimum frequency is set at 2 MHz to avoid thermal transient induced material damage. It is observed that higher frequency shortens the lifetime of solder joints. At 2 MHz the threshold resistance change happens after 192 hours of current loading. At 4 MHz, the same amount resistance change happens in 45 hours. It fails, however, in 3.3 hours at a frequency of 8 MHz and 1.7 hours at 10 MHz. This phenomenon can be credited to the 11

skin effect discussed above. High frequency generates a stronger eddy current that intensifies the current flow at the skin layer of conductors but alleviates it at the center cross section. It makes actual current density subjected by solder joints much larger than the nominal value. Non-linear regression curve fitting of MTTF vs. frequency is shown in Fig. 12. It is obvious that a quadratic relationship exists between MTTF and pulse frequency. With a 95.8% confidence value, the following relationship is obtained, MTTF = 626.3 f 1.8 (6) E. Electromigration MTTF equation of lead-free solder joints under PDC loadings From above discussion, we conclude that larger current density, higher duty factor and higher frequency lead to a shorter lifetime of solder joints. Combining equations (4), (5) and (6), we obtain the following MTTF equation of lead-free solder joints under PDC, which takes into account of frequency, duty factor and current density dependence. MTTF = α c 1.6 r 1.2 f 1.8 (7) After incorporating the Arrhenius temperature dependence term, we propose the MTTF equation of lead-free solder joints subjected to pulse current loadings as follow, MTTF = α c 1.6 r 1.2 f 1.8 e E/kT (8) Where MTTF is in hours, c is current density in A/cm 2, r is duty factor, f is frequency in MHz, E is vacancy activation energy in Kg μm 2 /(s 2 mol), and k is Boltzmann s 12

constant and T is temperature in Kelvin. It can be seen that, with an exponent of 1.8, the frequency term is the most serious contributing factor to EM damage of solder joints; current density comes as the second most serious damage factor. The duty factor term, which has an exponent of 1.2, is the least serious factor. We conclude that at a constant power output, higher duty factor and lower current density should be used to minimize the EM damage. CONCLUSIONS Electromigration damage of lead-free solder joints subjected to PDC current loading was investigated experimentally. Due to the material healing effect at load-off time, lifetime of solder joints subjected to PDC loading is considerably longer than those subjected to DC loading under otherwise the same conditions. SEM image shows that damage develops at both current crowding corners and the skin layer of solder joints instead of the whole cross section under DC loadings. It is found that higher current density, higher duty factor or higher frequency shortens lifetime of solder joints. With an exponent of 1.8, frequency of PDC loadings proves to be the most serious factor in EM damage, while current density and duty factor contribute less to the damage with exponent values of 1.6 and 1.2, respectively. A mean time to failure equation is proposed for lead-free solder joints subjected to pulse current loadings. At the same power output, EM damage could be alleviated by using a larger duty factor and smaller current density pulse signals. ACKNOWLEDGMENTS This research project has been sponsored by the US Navy, Office of Naval Research, Advanced Electrical Power Program under the direction of Terry Ericsen. We would like 13

to express our sincere appreciation to Dr. Yi-Shao Lai, director at ASE, for providing his support of the test vehicles for this program. Table 1 DIMENSION OF THE FLIP CHIP TEST VEHICLE PACKAGE [51] Features Dimension Package Size 27.3x27.3x1.14mm Die Size 7.62x7.62x0.74mm UBM Ti0.1µm/Cu0.5µm/Ni2µm UBM Diameter 112µm Passivation Opening 90µm Al Trace on Silicon 65µmx1µm Bump Size 112µm in diameter 105µm in standoff Bump Pitch 270µm Substrate Pad Finish Electroless Ni/Au on Cu Ni5µm/Au0.05µm/Cu5µm Substrate Pre-Solder Sn3%Ag0.5%Cu Substrate Cu Trace 65µmx15µm Substrate Solder Mask Opening 110µm Table 2 Experimental Results of MTTF of lead-free solder joints subjected to PDC current stressing at a constant temperature of 70 C Dependence Current Density Duty Factor Current Density (A/cm 2 ) Duty Factor (%) Frequency (MHz) MTTF PDC (hours) 1.0 10 5 50 4 49.2 1.3 10 5 50 4 44.7 1.6 10 5 50 4 32 1.8 10 5 50 4 23.5 2.1 10 5 50 4 0.83 1.3 10 5 30 4 78.1 1.3 10 5 50 4 44.7 1.3 10 5 60 4 37.5 1.3 10 5 80 4 19.5 14

Frequency 1.3 10 5 50 2 169.5 1.3 10 5 50 4 44.7 1.3 10 5 50 6 42 1.3 10 5 50 8 3.3 1.3 10 5 50 10 1.7 REFERENCE 1. Frankovic, R., G.H. Bernstein, and J.J. Clement, Pulsed-current duty cycle dependence of electromigration-induced stress generation in aluminum conductors. Electron Device Letters, IEEE, 1996. 17(5): p. 244-246. 2. Li, S., Sellers, Michael S., Basaran, Cemal, Schultz, Andrew J. and Kofke, David A., Lattice Strain Due to an Atomic Vacancy. Computational Materials Science. 6: p. 2798-2808. 3. Abdulhamid, M., C. Basaran, and Y. Lai, Thermomigration vs. Electromigration in Lead- Free Solder Alloys. IEEE Trans. on Advanced Packaging, 2009. (in press). 4. Campbell, D.R. and H.B. Huntington, Thermomigration and Electromigration in Zirconium. Physical Review, 1969. 179(3): p. 601-601. 5. Basaran, C., Shidong, Li, Hopkins, D. C. and Wei, Yao. Mean time to failure of SnAgCuNi solder joints under DC. in Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2012 13th IEEE Intersociety Conference on. 2012. 6. Yao, W. and B. Cemal. Skin effect and material degradation of lead-free solder joint under AC. in Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2012 13th IEEE Intersociety Conference on. 2012. 7. Basaran, C. and S. Nie, An Irreversible Thermodynamics Theory for Damage Mechanics of Solids. International Journal of Damage Mechanics, 2004. 13(3): p. 205-223. 8. Basaran, C., Lin, Minghui and Li, Shidong, Computational simulation of electromigration induced damage in copper interconnects. 2007. 9. Tang, H. and C. Basaran, Influence of microstructure coarsening on thermomechanical fatigue behavior of Pb/Sn eutectic solder joints. International Journal of Damage Mechanics, 2001. 10(3): p. 235-255. 10. Blech, I.A., Electromigration in thin aluminum films on titanium nitride. Journal of Applied Physics, 1976. 47(4): p. 1203-1208. 11. Blech, I.A. and C. Herring, Stress generation by electromigration. Applied Physics Letters, 1976. 29(3): p. 131-133. 12. Blech, I.A. and E. Kinsbron, Electromigration in thin gold films on molybdenum surfaces. Thin Solid Films, 1975. 25(2): p. 327-334. 13. Wei, Y. and C. Basaran. Damage of SAC405 solder joint under PDC. in Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2012 13th IEEE Intersociety Conference on. 2012. 14. Basaran, C., Hopkins, D. C., Frear, D. and Lin, J. K., Flip Chip Solder Joint Failure Modes. Advanced Packaging, 2005. 14(10): p. 14-19. 15. Yao, W. and C. Basaran, Electromigration analysis of solder joints under ac load: A mean time to failure model. Journal of Applied Physics, 2012. 111(6): p. 063703. 15

16. Basaran, C., L. Minghui, and Y. Hua. A thermodynamic model for electrical current induced damage. 2004. Piscataway, NJ, USA: IEEE. 17. Basaran, C. and S. Nie, A thermodynamics based damage mechanics model for particulate composites. International Journal of Solids and Structures, 2007. 44(3 4): p. 1099-1114. 18. Ye, H., Basaran, C. and Hopkins, Douglas C., Damage mechanics of microelectronics solder joints under high current densities. International Journal of Solids and Structures, 2003. 40(15): p. 4021-4032. 19. Ye, H., C. Basaran, and D. Hopkins, Thermomigration in Pb-Sn Solder Joints Under Joule Heating During Electric Current Stressing. Applied Physics Letters, 2003. 82(7): p. 1045-1047. 20. Ye, H., C. Basaran, and D.C. Hopkins, Experimental Damage Mechanics of Micro/Power Electronics Solder Joints under Electric Current Stresses. International Journal of Damage Mechanics, 2006. 15(1): p. 41-67. 21. Ye, H., C. Basaran, and D.C. Hopkins, Mechanical degradation of microelectronics solder joints under current stressing. International Journal of Solids and Structures, 2003. 40(26): p. 7269-7284. 22. Ye, H., C. Basaran, and D.C. Hopkins, Numerical simulation of stress evolution during electromigration in IC interconnect lines. Components and Packaging Technologies, IEEE Transactions on [see also Components, Packaging and Manufacturing Technology, Part A: Packaging Technologies, IEEE Transactions on], 2003. 26(3): p. 673-681. 23. Ye, H., C. Basaran, and D.C. Hopkins, Pb phase coarsening in eutectic Pb/Sn flip chip solder joints under electric current stressing. International Journal of Solids and Structures, 2004. 41(9-10): p. 2743-2755. 24. Ye, H., C. Basaran, and D.C. Hopkins, Experimental Damage Mechanics of Micro/Power Electronics of Solder Joints Under Electrical Current Stresses. International Journal of Damage Mechanics, 2008. 15: p. 28-28. 25. Ye, H., D.C. Hopkins, and C. Basaran, Measurement of high electrical current density effects in solder joints. Microelectronics Reliability, 2003. 43(12): p. 2021-2029. 26. Basaran, C. and M. Lin, Damage mechanics of electromigration induced failure. Mechanics of Materials, 2008. 40(1-2): p. 66-79. 27. Basaran, C. and M. Lin, Damage mechanics of electromigration in microelectronics copper interconnects. International Journal of Materials and Structural Integrity, 2007. 1: p. 16-39. 28. Basaran, C., M. Lin, and H. Ye, A thermodynamic model for electrical current induced damage. International Journal of Solids and Structures, 2003. 40(26): p. 7315-7327. 29. Lin, M., Basaran, C., Electromigration induced stress analysis using fully coupled mechanical-diffusion equations with nonlinear material properties. Computational Materials Science, 2005. 34(1): p. 82-98. 30. Li, S., M.F. Abdulhamid, and C. Basaran, Simulating Damage Mechanics of Electromigration and Thermomigration. SIMULATION, 2008. 84(8-9): p. 391-401. 31. Li, S., M.F. Abdulhamid, and C. Basaran, Damage Mechanics of Low Temperature Electromigration and Thermomigration. IEEE Transactions on Advanced Packaging, 2008. 32: p. 478-485. 32. Li, S. and C. Basaran, A computational damage mechanics model for thermomigration. Mechanics of Materials, 2009. 41(3): p. 271-278. 33. Basaran, C., S. Li, and M.F. Abdulhamid, Thermomigration induced degradation in solder alloys. Journal of Applied Physics, 2008. 103(12): p. 123520-9. 16

34. Brooke, L. Pulsed current electromigration failure model. 1987. New York, NY, USA: IEEE. 35. Tao, J.B.-K., Liew Chen, J. F. Cheung, N. W. Hu, C., Electromigration under time-varying current stress. Microelectronics Reliability, 1998. 38(Copyright 1998, IEE): p. 295-308. 36. English, A.T., K.L. Tai, and P.A. Turner, Electromigration in conductor stripes under pulsed dc powering. Applied Physics Letters, 1972. 21(8): p. 397-398. 37. Hatanaka, K., T. Noguchi, and K. Maeguchi. A generalized lifetime model for electromigration under pulsed DC/AC stress conditions. in 1989 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.89CH2694-8), 22-25 May 1989. 1989. Tokyo, Japan: Business Center for Acad. Soc. Japan. 38. Hu, C., et al. Modeling electromigration lifetime under pulsed and AC current stress. in Submicrometer Metallization: The Challenges, Opportunities and Limitations, 23-25 Sept. 1992. 1993. USA. 39. Liew, B.K., N.W. Cheung, and C. Hu. Electromigration interconnect lifetime under AC and pulse DC stress. in 27th Annual Proceedings. Reliability Physics 1989 (Cat. No.89CH2650-0), 11-13 April 1989. 1989. New York, NY, USA: IEEE. 40. Jiang, T., N.W. Cheung, and H. Chenming, An electromigration failure model for interconnects under pulsed and bidirectional current stressing. IEEE Transactions on Electron Devices, 1994. 41(4): p. 539-45. 41. Root, B.J. and S.J. Nagalingam. Electromigration failure on fine line conductors under pulse test conditions. 1985. New York, NY, USA: IEEE. 42. Shingubara, S., et al. Pulsed DC and AC electromigration studies of Cu dual damascene interconnects. in Stress-Induced Phenomena in Metallization. Seventh International Workshop on Stress-Induced Phenomena in Metallization, 14-16 June 2004. 2004. USA: AIP. 43. Schoen, J.M., A model of electromigration failure under pulsed condition. Journal of Applied Physics, 1980. 51(1): p. 508-12. 44. Towner, J.M. and E.P. van de Ven. Aluminum Electromigration Under Pulsed D.C. Conditions. in Reliability Physics Symposium, 1983. 21st Annual. 1983. 45. Maiz, J.A. Characterization of electromigration under bidirectional (BC) and pulsed unidirectional (PDC) currents. in Reliability Physics Symposium, 1989. 27th Annual Proceedings., International. 1989. 46. Hummel, R.E. and H.H. Hoang, On the electromigration failure under pulsed conditions. Journal of Applied Physics, 1989. 65(5): p. 1929-1931. 47. Basaran, C., et al., Electromigration time to failure of SnAgCuNi solder joints. Journal of Applied Physics, 2009. 106(1): p. 013707-013707-10. 48. Basaran, C., Ye, H., Hopkins, D. C., Frear, D. and Lin, J. K., Failure Modes of Flip Chip Solder Joints Under High Electric Current Density. Journal of Electronic Packaging, 2005. 127(2): p. 157-163. 49. Zhang, F., et al., Failure mechanism of lead-free solder joints in flip chip packages. Journal of Electronic Materials, 2002. 31(11): p. 1256-1263. 50. Brandenburg, S. and S. Yeh. Electromigration Studies of Flip Chip Bump Solder Joints. 1998. smta.org. 51. Peng Su, L.L., A Comparison Study of Electromigration Performance of Pb-free Flip Chip Solder Bumps 2009 59th Electronic Components and Technology Conference (May 2009), 2009: p. 903-908. 17

Fig. 1 Detailed profile of test vehicle used in the PDC electromigration experiments Fig. 2 Experimental scheme of PDC electromigration MTTF test of lead-free solder joints 18

Fig. 3 Four wire schemes to measure effective resistance of solder joints under PDC loadings Fig. 4 Current flow scheme and resistances measured (a) (b) 19

(c) Fig. 5 Scan Electron Microscope image of test vehicle after PDC current loadings: (a) initial profile of solder joint; (b) PDC induced damage after 50 hours of current loading at 2 MHz; (c) PDC induced damage after 140 hours of current loading at 2 MHz (a) 20

(b) Fig. 6 Measured resistance of lead-free solder joint subjected to PDC stressing at ambient temperature of 70 C: (a) current density dependence, (b) frequency dependence, (c) duty factor dependence (c) 21

(a) Fig. 7 Current density dependence of MTTF of lead-free solder joints subjected to PDC stressing at duty factor of 0.5, frequency of 4 MHz and ambient temperature of 70 C: (a) measured temperature at silicon chip, (b) resistance evolution history for varied current densities (b) 22

Fig. 8 Curve fitting results of MTTF of lead-free solder joints Vs. PDC stressing current density at duty factor of 0.5, frequency of 4 MHz and ambient temperature of 70 C Fig. 9 Duty factor dependence of MTTF of lead-free solder joints subjected to PDC stressing at current density of 1.3 10 5 A/cm 2, frequency of 4 MHz and ambient temperature of 70 C 23

Fig. 10 Curve fitting results of MTTF of lead-free solder joints Vs. PDC stressing duty factor at current density of 1.3 10 5 A/cm 2, frequency of 4 MHz and ambient temperature of 70 C Fig. 11 Frequency dependence of MTTF of lead-free solder joints subjected to PDC stressing at current density of 1.3 10 5 A/cm 2, duty factor of 0.5 and ambient temperature of 70 C 24

Fig. 12 Curve fitting results of MTTF of lead-free solder joints vs. PDC stressing frequency at current density of 1.3 10 5 A/cm 2, duty factor of 0.5 and ambient temperature of 70 C 25