Menxi Xie,*, CanYan Zhu, BingWei Shi 2, Yong Yang 2 J. Electrical Systems 3-2 (207): 332-347 Regular aer Power Based Phase-Locked Loo Under Adverse Conditions with Moving Average Filter for Single-Phase System JES Journal of Electrical Systems High erformance synchronization methord is citical for grid connected ower converter. For single-hase system, ower based hase-locked loo(pll) uses a multilier as hase detector(pd). As single-hase grid voltage is distorted, the hase error information contains ac disturbances oscillating at integer multiles of fundamental frequency which lead to detection error. This aer resents a new scheme based on moving average filter(maf) alied in-loo of PLL. The signal characteristic of hase error is dissussed in detail. A redictive rule is adoted to comensate the delay induced by MAF, thus achieving fast dynamic resonse. In the case of frequency deviate from nomimal, estimated frequency is fed back to adjust the filter window length of MAF and buffer size of redictive rule. Simulation and exerimental results show that roosed PLL achieves good erformance under adverse grid conditions. Keywords: Phase-locked loo;fictitious Power;Moving Average Filter;Frequency Adative; Digital Signal Processor. Article history: Received 2 March 205, Acceted March 207. Introduction Grid connected ower converters requires recise detection of the voltage hase angle for synchronization. Among different techniques, Phase-Locked Loo (PLL) is widely used in industry []. Essentially, PLL is a closed-loo control system and consists of three major arts, as shown in Fig.. The first art is the Phase Detector (PD),which detects the hase error between the inut signal u i and the outut signal u o. Secondly, Loo Filter (LF) eliminates the high-frequency comonents of the hase error. The hase angle is acquired by Voltage-Controlled Oscillator (VCO). Since continuous closed-loo adjustment, the outut u o tracks the inut u i till the hase error maintains to zero. ui uo * Corresonding author: Menxi Xie, Institute of Intelligent Structure and Systems, Soochow University, Suzhou, China, E-mail: xiemenxi@suda.edu.cn Institute of Intelligent Structure and Systems, Soochow University, Suzhou, 253, China 2 School of Urban Rail Transortation, Soochow University, Suzhou, 253, China Coyright JES 207 on-line : journal/esrgrous.org/jes Fig.. Tyical structure of PLL The most oular PLL scheme is Synchronous Reference Frame Phase-Locked Loo (SRF-PLL) [2], which uses Park transform as PD for three-hase system. For single-hase system, the known signal is the grid voltage. If a signal quadrature with the grid voltage is constructed, the SRF-PLL can be easily alied to single-hase system. Hence, the
J. Electrical Systems 3-2 (207): 332-347 quadrature signal generator (QSG) is the key unit [3] [7]. As the single-hase voltage is clean, SRF-PLL with QSG works well not only with zero steady hase error but also with fast dynamic resonse. In fact, ower utility always suffers all kinds of faults and disturbances. As a result, single-hase voltage may be harmonic distorted, sag/swell, notch, noise, frequency deviation and other tyes of abnormal state. Under such conditions, the aim of the synchronization is to track the hase angle of the fundamental comonent. Thus, additional filter should be set in front of PD to extract the fundamental [8]. The comutational burden of these re-filter methods is high, which is comlicated to realize. Power based PLL uses fictitious ower as PD. Phase error information is gotten by a multilier [9]. As the single-hase voltage is distorted, the multilier based PD contains disturbances. It causes hase error information inaccurate, leading hase detection error. The filter laces within the closed control loo to conceal these disturbances, always before the LF. Notch filter has been roosed to cancel the second-order disturbance aeared in PD high efficiently when grid voltage is clean [0]. However, it is not suitable for the serious distorted condition. The high order low-ass filter can attenuate most disturbances in PD, but the time constant is larger. Because of longer time delay introduced inevitable, the bandwidth of PLL should be tuned as high as ossible. Moving Average Filter (MAF) is an attractive solution []- [3]. It is efficient to conceal the in-loo disturbances while single-hase grid voltage is distorted seriously. More secifically, MAF is a low-ass filter with multi-oint notch attenuation that blocking disturbances comletely only leaving dc comonent as fundamental hase error signal. This aer rovides a detailed analysis and digital imlementation of MAF alied inloo of PLL. The scheme obtains zero detected error under adverse grid conditions. It is organized as follows. The signal characteristic of hase error under adverse conditions by PLL is exlained firstly. The basis theory of the roosed MAF-PLL is resented, including the delay analysis, frequency adative technique, small signal model and guidelines for key arameter design. Finally, simulation results are shown and exerimental results based on TMS320F28377s are obtained to verify the effectiveness. 2. Power Based Phase Error Detector Under Distorted Condition A single-hase system grid voltage with the dc offset and harmonics distorted can be exressed as u = U + U cos( ω t + φ ) + U cos( nω t + φ ) dc n n n= 2 = U + U cos( θ ) + f (2 ω,3 ω,4 ω L) dc where U dc reresents the amlitude of grid voltage dc comonents in V, U n reresents the amlitude of nth harmonic in V, ω =2πf =2π50 rad/s is the fundamental frequency, φn reresents the initial hase angle of nth harmonic in rad, and θ reresents the hase angle of fundamental comonent in rad. A feedback signal denotes i as i = sin ˆ = sin( ˆ t + ˆ ) (2) θ ω φ where ˆ θ reresents the detected value of θ, A fictitious ower can be defined as ˆω reresents the detected value of ω. () 333
Menxi Xie et al: Power Based Phase-Locked Loo Under Adverse Conditions... = ui = [ U + U cos( ω t + φ ) + f (2 ω,3 ω, 4 ω L)] sin( ˆ ω t + ˆ φ ) dc = U ˆ ˆ ˆ ˆ ˆ ˆ dc sin( ωt + φ ) + U cos( ωt + φ )sin( ωt + φ ) + f (2 ω,3 ω, 4 ωl)sin( ωt + φ ). (3) = U sin( ˆ ω t + ˆ φ ) dc + U{sin[( ωt + φ ˆ ˆ ˆ ˆ ) + ( ωt + φ )] sin[( ωt + φ ) ( ωt + φ )]} 2 + f (2 ω,3 ω, 4 ω L)sin( ˆ ω t + ˆ φ ) Suoseωˆ ω, then we have = U ˆ ˆ ˆ ˆ ˆ ˆ dc sin( ωt + φ ) + U[sin(2 ωt + φ + φ ) sin( θ θ)] + f (2 ω,3 ω,4 ωl)sin( ωt + φ) 2. (4) It is clear from (4) that nth harmonic of inut voltage aears (n±)th ac comonent in. Secifically, the fundamental comonent of inut voltage aears a dc term and a doublefrequency oscillating disturbance in. Hence, the hase error information of fundamental is reflected by the dc term in. Taking fictitious ower as PD, the dc term should be ket whereas all the other ac disturbances should be filtered out, as shown below = U sin( θ ˆ ˆ θ) U( θ θ) (5) 2 2. Based on classic closed loo PLL, the block diagram of ower based PLL is shown in Fig.2. The filter unit should block all of the high order disturbances in (4). * = 0 + ω ff + + ˆω i u Fig. 2. Block diagram of PLL 3. Moving Average Filter Moving Average Filter is considered as follows [2] t x ( t) = x( τ ) dτ T w t T w where T w is the filter window length, x(t) is the signal to be filtered, and x( t ) is the outut. The transfer function of (6) is given by Tws x( s) e GMAF ( s) = =. (7) x( s) T s w The Bode of (7) is shown in Fig. 3, and T w =0.02s. It can be imlied that MAF is a lowass filter with multi-oint notch attenuation at frequencies f d = n/t w (n =, 2, 3...) in Hz. MAF blocks these disturbances while with unity gain for dc comonent. If roer filter window length is selected, the notch adjusts to integer multiles of fundamental frequency. (6) 334
J. Electrical Systems 3-2 (207): 332-347 Fig. 3. Frequency resonse of MAF In ractical alications, digital imlementation of MAF can be derived as ( ) = N x k x( k i) N (8) i= 0 where x(k) is the current samle of x(t), x( k) is the digital outut and the samle time is T s. Equation (8) shows that MAF is a Finite Imulse Resonse filter with linear hase, thus the steady state delay could be comensated for real time control. To meet ac disturbances in (4), T w should be selected as Tw = NTs (9) Tw N = = T T f (0) s s d where f d is the fundamental frequency of disturbances in (4), always 50Hz. In consideration of T s is fixed, T w can be adjusted by changing N according to the grid frequency. Considering the comutation accuracy, the equation (8) can be rewritten as t x( t) = x( τ ) dτ = x( k) Tw t Tw () Nr Ts { x( k i) + [( ) x( k Nr ) + x( k Nr )]} T where w i= 0 T N T = w r s T (2) s Tw Nr = int( ) = int( ) Ts Ts f (3) d N r is round down of (3). It has been roved in [2] that the linear interolation method () can imrove MAF erformance dramatically. The method is deicted in Fig.4. As exlained, the time constant of MAF is 335
Menxi Xie et al: Power Based Phase-Locked Loo Under Adverse Conditions... τ = 2 (4) d Tw Fig.5 illustrates ste resonse of MAF. In order to comensate the delay, a redictive method has been resented in [0]. To exlain the method, the PD outut in Fig.2 is always a linear value in steady state. Fig. 4. Linear interolation method 0.8 0.6 0.4 0.2 ste inut MAF outut 0 0 0.005 0.0 0.05 0.02 0.025 0.03 t(s) Fig. 5. Ste resonse of MAF with delay The dc term of PD can be exressed ( k + ) = ( k) + mt s = ( k) + m f s where ( k) reresents current samle of ( t ), f s reresents the samle frequency, m reresents the sloe of ( t ). In the same way (5) 336
J. Electrical Systems 3-2 (207): 332-347 ( k + 2) = ( k + ) + mt s = ( k + ) + m (6) f s. A redictive equation can be derived from (6) and (7) ( k + 2) = 2 ( k + ) ( k ). (7) As mentioned before, the delay time of MAF can be digitalized ' N = Tw / Ts = N 2 2 (8). Alying (8) to (7), got ' ' ' ( k + N ) = 2 ( k + N ) ( k + N 2) ' ' (9) = ( N + ) ( k ) N ( k ). Equation (9) is a redictive rule, imling that the future outut of N can be redicted by current outut ( k ) and revious outut ( k ). Fig.6 desites sloe resonse of MAF with delay comensation (9). It should be note that the steady state delay was comensated comletely. 4. MAF-PLL Fig. 6. Sloe resonse of MAF with delay comensation As aforementioned, MAF can be alied to filter out the ac disturbances of PD, esecially effective for distorted grid voltage. MAF-PLL block diagram is shown in Fig.7. 337
Menxi Xie et al: Power Based Phase-Locked Loo Under Adverse Conditions... * = 0 + + ω ff + ˆω u i Fig. 7. Power based PLL with MAF In the case of grid voltage frequency deviation, the ac disturbances fundamental frequency of PD varies. In view of this fact, the detected frequency is fed back to udate the MAF filter window length T w and N in (9) online. An aroximate small signal linear control model of MAF-PLL is available in Fig. 8. The amlitude of fundamental U is a gain in forward ath. The dynamic resonse of PLL will be affected by U. This drawback can be eliminated by normalized inut voltage. θ + + U / 2 + Disturbances G ( ) MAF s K f ( s) s Fig. 8. Small-signal linear control model The LF using PI regulator as follow k K ( ) = + i f s k s where k P reresents roortion gain, k i reresents integral gain. The transfer function of MAF can be aroximate with following Tws / 2 Tws e + Tws / 2 GMAF ( s) = = Tws Tws + Tws / 2. Then, the oen-loo transfer function of Fig.8 can be given by U ki Hol ( s) = k + GMAF ( s) 2 s s U k s + ki = 2 s + Tws / 2 s U 2 / T ( + ) w k s ki = 2 2 s ( s + 2 / Tw ). Equation (22) is a tyical second order system, where (20) (2) (22) 338
J. Electrical Systems 3-2 (207): 332-347 ω = ωc / b k = 2 ωc / U 2 ki = 2 ωc / bu. (23) b is a constant which is a tradeoff between dynamic and steady state characteristics. ω c = 2 / Twb k = 4 / UT wb = 2 3 ki 8 / UT wb. (24) In general symmetrical otimum method [2],[4],[5], LF arameters can be determined as follows + k = 4 / V Twb = + 2 3 (25) ki 8 / V Tw b where T w =0.02s, U =, and b can be set to 2.4, to make a tradeoff between raidly and stability. 5. Simulation Results To demonstrate the effectiveness of the MAF-PLL, this method was simulated by Matlab/Simulink. The results are shown in Figs.9-5 for different scenarios. Each test scenarios resents four grahics (from to to bottom) inut voltage(u i ), detected hase angle( ˆ θ ), detected frequency( ˆf ), and hase error( θ ˆ -θ ). A. Amlitude Ste Fig.9 shows the simulation results of inut voltage amlitude ste. The amlitude of inut voltage stes down from u to 0.4u at 0.25s. At 0.4s, it returns to nominal. At 0.5s, it stes u to.6u and then back to nominal at 0.6s. It can be observed that the steady-state error of both hase angle and frequency are zero. The overshoot of hase angle is no more than 0 degrees, while eak frequency error is less than 5 Hz. As mentioned earlier, the amlitude of inut voltage is a gain in the forward ath. Since the amlitude of hase is small, the dynamic resonse becomes slower. This oint can be imlied from first transition rocess of hase error rofile. The rocess is longer than other three. 339
Menxi Xie et al: Power Based Phase-Locked Loo Under Adverse Conditions... B. Phase Jum Fig. 9. Simulation results of a sag or ste u of 60% in inut voltage Phase jum is a common erturbation in ower suly grid. Fig. 0 dislays the simulation results of this condition. At 0.25s, Phase angle jum is occurring with 60 degrees. At 0.4s, Phase angle jums 5 degrees, and 90 degrees at 0.55s. The MAF-PLL tracks hase angle correctly since the steady-state error for both the hase angle and frequency are zero. Fig. 0. Simulation results of hase jum in inut voltage 340
J. Electrical Systems 3-2 (207): 332-347 C. Distorted Simulation results are resented in Fig. when the inut voltage is distorted. From 0.25s to 0.4s, 0.3u of 3rd harmonic is injected base on the fundamental comonent. At 0.4s, 0.2u of 5th harmonic is added. At 0.6s, 0.3u of 7th harmonic is added yet. The PLL exhibits zero steady-state error for all kind of harmonics. The overshoot of hase angle is no more than degree. MAF-PLL is very suitable for distorted inut as shown. D. Frequency deviation Fig.. Simulation results of distortion inut voltage Fig.2 illustrates the simulation results of frequency deviation in inut voltage with frequency adative technique. The frequency stes u from 50Hz to 55Hz at 0.03s, and back to 50Hz at 0.35s. At 0.55s, the frequency stes down to 45Hz. Because the filter window length of MAF is adjusting online with resect to the inut, the disturbances of PD were totally filtered out. Thus, the steady-state error of both the detected hase angle and frequency are zero. As it can be seen, without the frequency adative technique, the comarison results are illustrated in Fig.3. Both the detected hase error and frequency show steady-state riles. Comarison diagram of hase error is dislayed in Fig.4 between 0.65s and 0.7s. Notice that the eak-to-eak hase error without frequency adative technique is about degree. 34
Menxi Xie et al: Power Based Phase-Locked Loo Under Adverse Conditions... Fig. 2. Simulation results of frequency deviation in inut voltage Fig. 3. Simulation results of frequency deviation in inut voltage without frequency adative technique Fig. 4. Comarison of steady hase error with or without frequency adative technique E. DC Offset Fig.5 shows the simulation results of inut voltage with dc offset. Secifically, the inut voltage amlitude exeriences a ste of 0.u dc offset at 0.255s. Then, it returns to nominal at 0.4s. Finally, it exeriences another ste of 0.3u dc offset at 0.5s. The steady-state error of both the detected hase angle and frequency are zero. The overshoot of hase angle error is no more than 0 degrees, while frequency overshoot is less than 5 Hz. 342
J. Electrical Systems 3-2 (207): 332-347 6. Exerimental Results Fig. 5. Simulation results of dc offset in inut voltage An exerimental latform has been set u with floating oint digital signal rocessor TMS320F28377S. The inut voltage signal is generated by DSP software internal. The onchi 2 bits AD module catures the inut as voltage signal. The samle frequency is 0 KHz, and the MAF-PLL algorithm is executed every 0.000s in an interrut routine. For trigonometric comutation, the routine calls TI's otimized floating oint library directly. In order to minimize high-seed accumulated comuting error, the integration is imlemented by discrete back Euler method, and PI regulator uses incremental structure. The interesting internal variables were sent to the on chi digital-to-analog module for oscilloscoe dislay. The exerimental tests are set to agree with simulation scenarios. Fig.6 dislays exerimental results of amlitude ste, where it can be seen that the resonse is fast. Fig.7 deicts exerimental results of hase angle jum, and the transition rocess only takes 2 cycles. 343
Menxi Xie et al: Power Based Phase-Locked Loo Under Adverse Conditions... u π ˆf 50Hz θ - ˆ θ Fig. 6 Exerimental results of amlitude ste in inut voltage u π ˆf 50Hz θ - ˆ θ Fig. 7 Exerimental results of hase angle jum in inut voltage 344
J. Electrical Systems 3-2 (207): 332-347 u π 50Hz θ - ˆ θ ˆf Fig. 8 Exerimental results of frequency ste from 50 to 55 Hz in inut voltage with frequency adative technique u π 50Hz θ - ˆ θ ˆf Fig. 9 Exerimental results of frequency ste from 50 to 55 Hz in inut voltage without frequency adative technique The comarison results obtained with or without MAF frequency adative technique under the frequency ste are shown, in Fig.8 and Fig.9 resectively. The detected frequency error exists clearly in Fig.9, which is oscillated at double of inut frequency without frequency adative technique. Fig. 20 illustrates exerimental results for the scenario with harmonic distortion in inut voltage, and the harmonic contents are as same as the simulation. The measured riles for 345
Menxi Xie et al: Power Based Phase-Locked Loo Under Adverse Conditions... both the frequency and hase error are zero, which are in agreement with the simulation results. u π ˆf 50Hz θ - ˆ θ Fig. 20 Exerimental results of harmonic distorted in inut voltage Fig.2 deicts the exerimental results for the scenario with DC offset in the inut voltage. It shows that the dynamic resonse is rather fast. Furthermore, the DC rejection ability by setting MAF window 0.02s brings zero hase error. u π ˆf 50Hz θ - ˆ θ Fig. 2 Exerimental results of dc offset in inut voltage 346
J. Electrical Systems 3-2 (207): 332-347 7. Conclusion Synchronization is of great imortance for grid-connected ower converter since recise hase angle information of the converter control. This aer resents a detailed research for MAF-PLL of for single-hase system. The method can be realized easily in digital form, and the comuting burden is small. The simulation and exerimental results verify the effectiveness of the method, and it exhibits excellent erformance under adverse conditions. 8. Acknowledgement This work is suorted by the National Natural Science Foundation of China (under Grant No. 53073 and 540724), the Natural Science Foundation of Jiangsu Province (under Grant No. BK2030307). References [] F. M. Gardner, Phase lock techniques. New York: Wiley, 979. [2] Se-Kyo Chung. A hase tracking system for three hase utility interface inverters, IEEE Trans. Power Electron., vol. 5, no.3,.43-438,may.2000. [3] Mihai Ciobotaru, Remus Teodorescu and Frede Blaabjerg. A new single-hase PLL structure based on second order generalized integrator, in Proc. IEEE PESC, Jeju, South Korea, Jun. 2006,. -6. [4] Y. Han, M. Luo, X. Zhao, J. M. Guerrero and L. Xu, Comarative erformance evaluation of orthogonalsignal-generators-based single-hase PLL algorithms a survey, IEEE Trans on Power Electron., vol.3, no. 5,. 3932-3944, May 206. [5] Q. Guan, Y. Zhang, Y. Kang, and J. Guerrero, Single-hase hase locked loo based on derivative elements, IEEE Trans. Power Electron., vol. 32, no. 6,. 44-4420, June. 207. [6] Y. Yang, K. Zhou, and F. Blaabjerg, Virtual unit delay for digital frequency adative t/4 delay hase-locked loo system, in Proc. IPEMC-ECCE Asia, Hefei, China, May. 206,. 290-296. [7] L. Xiong, F. Zhuo, F. Wang, X. Liu, and M. Zhu, A fast orthogonal signal-generation algorithm characterized by noise immunity and high accuracy for single-hase grid, IEEE Trans. Power Electron., vol. 3, no. 8,. 847-85, Mar.206. [8] S. Golestan; J. Guerrero; J. Vasquez, Three-hase PLLs: a review of recent advances, IEEE Trans. Power Electron., vol. 32, no. 3,. 894-907, Mar. 207. [9] R. M. Santos Filho, P. F. Seixas, P. C. Cortizo, L. A. B. Torres, and A. F. Souza, Comarison of three singlehase PLL algorithms for UPS alications, IEEE Trans. Ind. Electron., vol. 55, no. 8,. 2923 2932, Aug. 2008. [0] F. D. Freijedo, J. Doval-Gandoy, O. Loez, and E.Acha, Tuning of hase locked loos for ower converters under distorted utility conditions, IEEE Trans. Ind. Al., vol. 45, no. 6,. 2039 2047, Dec. 2009. [] L.Wang, Q. Jiang, L. Hong, C. Zhang, and Y.Wei, A novel hase-locked loo based on frequency detector and initial hase angle detector, IEEE Trans. Power Electron., vol. 28, no. 0,. 4538 4549, Oct. 203. [2] Saeed Golestan, Malek Ramezani, Jose M. Guerrero, Francisco D. Freijedo, and Mohammad Monfared, Moving average filter based hase-locked loos: erformance analysis and design guidelines, IEEE Trans. Power Electron., vol. 29, no. 6,. 2750 2763, June. 204. [3] I. Carugati, P. Donato, S. Maestri, D. Carrica, and M. Benedetti, Frequency adative PLL for olluted singlehase grids, IEEE Trans. Power Electron., vol. 27, no. 5,. 2396 2404, May 202. [4] Saeed. Golestan, M. Monfared, F. D. Freijedo, and J. M. Guerrero, Performance imrovement of a refiltered synchronous reference frame PLL by using a PID tye loo filter, IEEE Trans. Ind. Electron., vol. 6, no. 7,. 3469 3479, Jul. 204. [5] S. Golestan, M. Monfared, F. D. Freijedo, and J. M. Guerrero, Design and tuning of a modified ower-based PLL for single-hase grid connected ower conditioning systems, IEEE Trans. Power Electron., vol. 27, no. 8,. 3639 3650, Aug. 202. 347