ECE 545 Digital System Design with VHDL Lecture Digital Logic Refresher Part A Combinational Logic Building Blocks
Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Law Combinational Logic Building Blocks Multiplexers Decoders, Demultiplexers Encoders, Priority Encoders Arithmetic circuits ROM. Implementing combinational logic using ROM. Tri-state buffers. 2
Textbook References Combinational Logic Review Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2 nd or 3 rd Edition Chapter 2 Introduction to Logic Circuits (2.-2.8 only) Chapter 6 Combinational-Circuit Building Blocks (6.-6.5 only) OR your undergraduate digital logic textbook (chapters on combinational logic) 3
Basic Logic Review some slides modified from: S. Dandamudi, Fundamentals of Computer Organization and Design 4
Basic Logic Gates (2-input versions) 5
Basic Logic Gates Generalized Simple logic gates AND à if one or more inputs is OR à if one or more inputs is NAND = AND + NOT if one or more inputs is NOR = OR + NOT if one or more input is XOR à if an odd number of inputs is XNOR à if an even number of inputs is NAND and NOR gates require fewer transistors than AND and OR in standard CMOS Functionality can be expressed by a truth table A truth table lists output for each possible input combination 6
Number of Functions Number of functions With N logical variables, we can define 2 2N functions Some of them are useful AND, NAND, NOR, XOR, Some are not useful: Output is always Output is always Number of functions definition is useful in proving completeness property 7
Complete Set of Gates Complete sets A set of gates is complete if we can implement any logic function using only the type of gates in the set Some example complete sets {AND, OR, NOT} {AND, NOT} {OR, NOT} {NAND} {NOR} Minimal complete set A complete set with no redundant elements. Not a minimal complete set 8
NAND as a Complete Set Proving NAND gate is universal 9
Logic Functions Logic functions can be expressed in several ways: Truth table Logical expressions Graphical schematic form HDL code Example: Majority function Output is one whenever majority of inputs is We use 3-input majority function
Alternative Representations of Logic Function Truth table A B C F HDL code: Logical expression form F = A B + B C + A C Graphical schematic form F <= (A AND B) OR (B AND C) OR (A AND C) ;
Boolean Algebra Boolean identities Name AND version OR version Identity x. = x x + = x Complement x. x = x + x = Commutative x. y = y. x x + y = y + x Distribution x. (y+z) = xy+xz x + (y. z) = (x+y) (x+z) Idempotent x. x = x x + x = x Null x. = x + = 2
Boolean Algebra (cont d) Boolean identities (cont d) Name AND version OR version Involution x = (x ) --- Absorption x. (x+y) = x x + (x. y) = x Associative x. (y. z) = (x. y). z x + (y + z) = (x + y) + z de Morgan (x. y) = x + y (x + y) = x. y (de Morgan s law in particular is very useful) 3
Alternative symbols for NAND and NOR 4
Majority Function Using Other Gates Using NAND gates Get an equivalent expression A B + C D = (A B + C D) Using de Morgan s law A B + C D = ( (A B). (C D) ) Can be generalized Example: Majority function A B + B C + AC = ((A B). (B C). (AC) ) 5
Majority Function Using Other Gates (cont'd) Majority function 6
Combinational Logic Building Blocks Some slides modified from: S. Dandamudi, Fundamentals of Computer Organization and Design S. Brown and Z. Vranesic, "Fundamentals of Digital Logic" 7
Multiplexers log 2 n selection inputs n inputs output multiplexer n binary inputs (binary input = -bit input) log 2 n binary selection inputs binary output Function: one of n inputs is placed onto output Called n-to- multiplexer 8
2-to- Multiplexer s s f w w f w w (a) Graphical symbol (b) Truth table w w s f s w w f (c) Sum-of-products circuit (d) Circuit with transmission gates Source: Brown and Vranesic 9
4-to- Multiplexer s s s s f w w w 2 w 3 f w w w 2 w 3 (a) Graphic symbol (b) Truth table s s w w f w 2 w 3 Source: Brown and Vranesic (c) Circuit 2
Multi-bit 4-to- Multiplexer s s s s f w w w 2 w 3 8 8 f w w w 2 w 3 (a) Graphic symbol (b) Truth table When drawing schematics, can draw multi-bit multiplexers Example: 8-bit 4-to- multiplexer 4 inputs (each 8 bits) output (8 bits) 2 selection bits Can also have multi-bit 2-to- muxes, 6-to- muxes, etc. 2
8-bit 4-to- Multiplexer s s w (7) w (7) w 2 (7) w 3 (7) f(7) s s w w w 2 w 3 8 f = 8 s s w (6) w (6) w 2 (6) w 3 (6) f(6) An 8-bit 4-to- multiplexer is composed of eight [-bit] 4-to- multiplexers s s w () w () w 2 () w 3 () f() 22
Decoders n inputs w y 2 n w n- 2 n outputs Enable En y Decoder n binary inputs 2 n binary outputs Function: decode encoded information If enable=, one output is asserted high, the other outputs are asserted low If enable=, all outputs asserted low Often, enable pin is not needed (i.e. the decoder is always enabled) Called n-to-2 n decoder Can consider n binary inputs as a single n-bit input Can consider 2 n binary outputs as a single 2 n -bit output Decoders are often used for RAM/ROM addressing 23
2-to-4 Decoder En w w y 3 y 2 y y - - w En y 3 w y 2 y y (a) Truth table (b) Graphical symbol w y w y y 2 y 3 Source: Brown and Vranesic En (c) Logic circuit 24
Demultiplexers log 2 n selection inputs input n outputs Demultiplexer binary input n binary outputs log 2 n binary selection inputs Function: places input onto one of n outputs, with the remaining outputs asserted low Called -to-n demultiplexer Closely related to decoder Can build -to-n demultiplexer from log 2 n-to-n decoder by using the decoder's enable signal as the demultiplexer's input signal, and using decoder's input signals as the demultiplexer's selection input signals. 25
-to-4 Demultiplexer 26
Encoders 2 n inputs w 2 n w y y n n outputs Encoder 2 n binary inputs n binary outputs Function: encodes information into an n-bit code Called 2 n -to-n encoder Can consider 2 n binary inputs as a single 2 n -bit input Can consider n binary output as a single n-bit output Encoders only work when exactly one binary input is equal to 27
4-to-2 Encoder w 3 w 2 w w y y (a) Truth table w w y w 2 w 3 y (b) Circuit 28
Priority Encoders 2 n inputs w 2 n w y n n outputs y z "valid" output Priority Encoder 2 n binary inputs n binary outputs binary "valid" output Function: encodes information into an n-bit code based on priority of inputs Called 2 n -to-n priority encoder Priority encoder allows for multiple inputs to have a value of '', as it encodes the input with the highest priority (MSB = highest priority, LSB = lowest priority) "valid" output indicates when priority encoder output is valid Priority encoder is more common than an encoder 29
3 4-to-2 MSB Priority Encoder - w y - y z - - - w - - w 2 - w 3
Single-Bit Adders Half-adder Adds two binary (i.e. -bit) inputs A and B Produces a sum and carryout Problem: Cannot use it alone to build larger adders Full-adder Adds three binary (i.e. -bit) inputs A, B, and carryin Like half-adder, produces a sum and carryout Allows building M-bit adders (M > ) Simple technique Connect C out of one adder to C in of the next These are called ripple-carry adders 3
Half-Adder c x 2 s HA x + y = ( c s ) 2 y x y c s 32
33 Full-Adder x y c out s FA x + y + c in = ( c out s ) 2 2 x y c out s c in c in x y c in s c out
6-bit Unsigned Adder 6 6 Cout X + S Y Cin 6 34
Multi-Bit Ripple-Carry Adder A 6-bit ripple-carry adder is composed of 6 (-bit) full adders Inputs: 6-bit A, 6-bit B, -bit carry in (set to zero in the figure below) Outputs: 6-bit sum S, -bit carry out Other multi-bit adder structures can be studied in ECE 645 Computer Arithmetic Called a ripple-carry adder because carry ripples from one full-adder to the next. Critical path is 6 full-adders. 35
Comparator Used two compare two M-bit numbers and produce a flag (M >) Inputs: M-bit input A, M-bit input B Output: -bit output flag indicates condition is met indicates condition is not met Can compare: >, >=, <, <=, =, etc. A B M M A > B? if A > B if A <= B 36
Example: 4-bit comparator (A = B) A B 4 4 A = B? if A = B if A!= B 37
4x4-bit Unsigned Multiplier 4 4 a * c b U 8 38
4x4-bit Signed Multiplier 4 4 a * c b S 8 39
Unsigned vs. Signed Multiplication Unsigned Signed 5 - x x 5 x x - 225 4
Quotient and remainder Given integers a and n, n>! q, r Z such that a = q n + r and r < n q quotient r remainder (of a divided by n) q = a n = a div n r = a - q n = a = a mod n a n n = 4
Rules of addition, subtraction and multiplication modulo n a + b mod n = ((a mod n) + (b mod n)) mod n a - b mod n = ((a mod n) - (b mod n)) mod n a b mod n = ((a mod n) (b mod n)) mod n 42
Logical Shift Right 4 A >> C 4 L A(3) A(2) A() A() A(3) A(2) A() A C 43
Arithmetic Shift Right 4 A >> C 4 A A(3) A(2) A() A() A C A(3) A(3) A(2) A() 44
Fixed Rotation 4 A <<< C 4 A(3) A(2) A() A() A(2) A() A() A(3) A C 45
8-bit Variable Rotator Left A 8 3 B A <<< B C 8 46
Read Only Memory (ROM) m ADDR ROM DOUT n 47
Implementing Arbitrary Combinational Logic Using ROM X 5 X 4 X 3 X 2 X Y ADDR DOUT 5 ROM 48
Tri-state Buffer e x f e = (a) A tri-state buffer x f e x f Z Z x e = (b) Equivalent circuit f (c) Truth table 49
Four types of Tri-state Buffers e e x f x f (a) (b) e e x f x f (c) (d) 5