EECS 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization

EECS 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Discrete Systems Lecture: Automata, State machines, Circuits Stavros Tripakis University of California, Berkeley Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 1 / 36

Discrete Systems Automata, state machines, transition systems,... States Transitions: discrete moves from state to state Logical time: order of transitions As opposed to quantitative, real-time models that we will see later Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 2 / 36

AUTOMATA, STATE MACHINES, DIGITAL CIRCUITS Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 3 / 36

Deterministic Finite Automata A DFA is a tuple (Σ, S, s 0, δ, F ) Σ: finite set of symbols, letters (the alphabet) S: finite set of states s 0 S: (unique) initial state δ: transition function (usually total but could also be partial) δ : S Σ S F S: set of final/accepting states Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 4 / 36

Example: Automaton a s 0 b s 1 c s 2 a Define the tuple: (Σ, S, s 0, δ, F ) Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 5 / 36

DFA as Systems DFA states = system states DFA transitions = system dynamics What about inputs and outputs? Viewing the DFA as an acceptor: Σ = set of inputs. Viewing the DFA as a generator: Σ = set of outputs. Accepting states can be seen as a boolean output: 0 if the current state s F ; 1 otherwise. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 6 / 36

DFA as Language Acceptors Theory of formal languages and grammars Major contributions by linguists Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 7 / 36

DFA as Language Acceptors Theory of formal languages and grammars Major contributions by linguists Since then, innumerable applications. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 7 / 36

Important application: verification Source Design Monitor Source: an automaton, viewed as generator. Generates all possible valid input sequences. Monitor: an automaton, viewed as an acceptor. Models the property we want to check. E.g., property holds iff there is no accepting behavior. Design: the system we want to verify. It has inputs and outputs, usually captured as state machine. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 8 / 36

Important application: verification Environment Design Monitor Environment: a state machine. There is often feedback between the system and its environment. I.e., the values that the environment provides to the system depend on what it receives from the system. Monitor: an automaton, viewed as an acceptor. Models the property we want to check. E.g., property holds iff there is no accepting behavior. Design: the system we want to verify. It has inputs and outputs, usually captured as state machine. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 9 / 36

Finite State Machines An FSM is a tuple (I, O, S, s 0, δ, λ) I: set of inputs O: set of outputs S: set of states s 0 S: initial state δ : S I S: transition function λ: output function If the FSM is of type Moore: If the FSM is of type Mealy: Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 10 / 36

Finite State Machines An FSM is a tuple (I, O, S, s 0, δ, λ) I: set of inputs O: set of outputs S: set of states s 0 S: initial state δ : S I S: transition function λ: output function If the FSM is of type Moore: λ : S O If the FSM is of type Mealy: Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 10 / 36

Finite State Machines An FSM is a tuple (I, O, S, s 0, δ, λ) I: set of inputs O: set of outputs S: set of states s 0 S: initial state δ : S I S: transition function λ: output function If the FSM is of type Moore: λ : S O If the FSM is of type Mealy: λ : S I O Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 10 / 36

Example: Moore Machine structure: tick (implicit) counter modulo 4 MSB {0, 1} LSB {0, 1} behavior: s 0 00 s 1 01 s 2 10 s 3 11 Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 11 / 36

Example: Mealy Machine structure: in1 {0, 1} in2 {0, 1} arbiter out {0, 1, 2} behavior: 01/1 00/0 00/0 11/1 01/1 10/2 11/2 10/2 Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 12 / 36

Example: Mealy Machine original: in1 {0, 1} in2 {0, 1} arbiter out {0, 1, 2} 01/1 10/2 00/0 00/0 11/1 01/1 11/2 10/2 alternative drawing: 00 00 01 10 out := case in1 in2 00 : 0; 01 : 1; 10 : 2; 11 : 1; end 11 11 out := case in1 in2 00 : 0; 01 : 1; 10 : 2; 11 : 2; end 01 10 Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 13 / 36

Synchronous Circuits Generic structural view: Combinational logic part: a network of logical gates (AND, OR, NOT, XOR,...). Memory/state of the circuit: some type of digital memory element (e.g., D-type flip-flop). Synchronous: clock arriving conceptually synchronously (simultaneously) at all flip-flops. Circuit: a network of connected gates and flip-flops ( netlist ). Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 14 / 36

Memory element: D flip-flop D (input) clock output Behavior (simplified): 1 Clock input defines a set of times t 1, t 2, t 3,... (e.g., up-edges of a periodic pulse). The value of output remains constant during the interval [t k, t k+1 ) and equal to the value of the input D at t k. Door-window metaphor (on white board). 1 More accurate description of timing behavior in timing analysis lecture. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 15 / 36

Memory element: D flip-flop D (input) clock output Behavior (simplified): 1 Clock input defines a set of times t 1, t 2, t 3,... (e.g., up-edges of a periodic pulse). The value of output remains constant during the interval [t k, t k+1 ) and equal to the value of the input D at t k. Door-window metaphor (on white board). Memory elements often have more inputs (e.g., resets to initialize state). 1 More accurate description of timing behavior in timing analysis lecture. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 15 / 36

Combinational logic gates Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 16 / 36

Digital Circuits: Networks of Flip-Flops and Logic Gates For now, we consider acyclic circuits: any feedback loops are broken by flip-flops: Dynamics determined by the sequence of clock pulses. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 17 / 36

From Circuits to State Machines Is this a state machine? Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 18 / 36

From Circuits to State Machines Is this a state machine? Is it a Mealy or Moore machine? How are (I, O, S, s 0, δ, λ) defined? Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 19 / 36

From Circuits to State Machines Is this a state machine? Is it a Mealy or Moore machine? How are (I, O, S, s 0, δ, λ) defined? What would a Moore Machine look like? Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 19 / 36

State Machines and Synchronous Circuits Why this is not a good drawing: 01/1 00/0 00/0 11/1 01/1 10/2 11/2 10/2 Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 20 / 36

From FSMs to Circuits Brute-force implementation: Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 21 / 36

From FSMs to Circuits Brute-force implementation: log n flip-flops, where n = S = number of states of the FSM. log k input wires, where k = I = number of input symbols. log m output wires, where m = O = number of output symbols. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 21 / 36

From FSMs to Circuits Brute-force implementation: log n flip-flops, where n = S = number of states of the FSM. log k input wires, where k = I = number of input symbols. log m output wires, where m = O = number of output symbols. Multiplexers to implement transition and output functions. More efficient implementations: logic synthesis lecture. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 21 / 36

An Elegant Notation for State Machines: Lustre A program in the synchronous language Lustre [Halbwachs et al., 1991]: node Edge (X : bool) returns (E : bool); let E = false -> X and not pre X ; tel Can you guess its meaning? Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 22 / 36

An Elegant Notation for State Machines: Lustre A program in the synchronous language Lustre [Halbwachs et al., 1991]: node Edge (X : bool) returns (E : bool); let E = false -> X and not pre X ; tel Can you guess its meaning? E 0 = false E k+1 = X k+1 X k Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 22 / 36

An Elegant Notation for State Machines: Lustre A program in the synchronous language Lustre [Halbwachs et al., 1991]: node Edge (X : bool) returns (E : bool); let E = false -> X and not pre X ; tel Can you guess its meaning? E 0 = false E k+1 = X k+1 X k Quiz: write a counter in Lustre. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 22 / 36

Non-Deterministic Finite Automata An NFA is a tuple (Σ, S, S 0,, F ) Σ: alphabet S: finite set of states S 0 S: set of initial states : transition relation S Σ S or S Σ {ɛ} S F S: set of final/accepting states Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 23 / 36

Non-Determinism: Why? Uncertainty, e.g.: user input unknown weather patterns unknown... Abstraction: don t want to model some details (e.g., how message corruption occurs) Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 24 / 36

Non-Determinism: Why? Uncertainty, e.g.: user input unknown weather patterns unknown... Abstraction: don t want to model some details (e.g., how message corruption occurs) Can DFA always be viewed as deterministic? Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 24 / 36

Non-Determinism: Why? Uncertainty, e.g.: user input unknown weather patterns unknown... Abstraction: don t want to model some details (e.g., how message corruption occurs) Can DFA always be viewed as deterministic? What if they are generators? Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 24 / 36

(Linear) Runs, Behaviors,... A run of a NFA (Σ, S, S 0,, F ) is a (finite or infinite) sequence of states and transitions: a s 1 a 0 2 a s1 3 s2 such that s 0 S 0 i : (s i, a i+1, s i+1 ) Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 25 / 36

(Linear) Runs, Behaviors,... A run of a NFA (Σ, S, S 0,, F ) is a (finite or infinite) sequence of states and transitions: a s 1 a 0 2 a s1 3 s2 such that s 0 S 0 i : (s i, a i+1, s i+1 ) A behavior is the corresponding sequence of labels: a 1 a 2 a 3 Accepting run (and corresponding accepted behaviors): if run is finite: ending in a state in F. if run is infinite: infinitely often visiting a state in F (Büchi condition), or other conditions (Rabin, Street,...). Language: set of behaviors accepted by the automaton. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 25 / 36

(Linear) Runs, Behaviors,... = Semantics! Syntax vs. Semantics: Syntax: the program, the automaton, the model,... Semantics: the set of runs/behaviors of the program, automaton, model,... What is this? a b c A graph (syntax). What is its semantics? Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 26 / 36

(Linear) Runs, Behaviors,... = Semantics! Syntax vs. Semantics: Syntax: the program, the automaton, the model,... Semantics: the set of runs/behaviors of the program, automaton, model,... What is this? a b c A graph (syntax). What is its semantics? It could be an automaton... Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 26 / 36

(Linear) Runs, Behaviors,... = Semantics! Syntax vs. Semantics: Syntax: the program, the automaton, the model,... Semantics: the set of runs/behaviors of the program, automaton, model,... What is this? a b c A graph (syntax). What is its semantics? It could be an automaton...... or a network of actors... Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 26 / 36

(Linear) Runs, Behaviors,... = Semantics! Syntax vs. Semantics: Syntax: the program, the automaton, the model,... Semantics: the set of runs/behaviors of the program, automaton, model,... What is this? a b c A graph (syntax). What is its semantics? It could be an automaton...... or a network of actors...... or a dependency relation...... or... Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 26 / 36

Syntax vs. Semantics Different models could have the same semantics, e.g.: different automata may accept the same language. 0,1 0 1 1 NFA: s 1 0 s 1 DFA: q 0 q 1 0 Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 27 / 36

Syntax vs. Semantics Different models could have the same semantics, e.g.: different automata may accept the same language. 0,1 s 1 NFA: 0 s 1 0 1 DFA: q 0 q 1 different models that mean the same thing, e.g., FSM vs. Lustre program. A single model may be assigned many different semantics, e.g.: linear vs. branching-time semantics (we will look at these later) operational vs. denotational semantics... 1 0 Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 27 / 36

Operational and Denotational Semantics for FSMs A run of a Mealy machine (I, O, S, s 0, δ, λ) is a (finite or infinite) sequence of states / transitions: such that i : x i I, y i O i : s i+1 = δ(s i, x i ) i : y i = λ(s i, x i ) x 0/y 0 x 1/y 1 x 2/y 2 s 0 s1 s2 The observable I/O behavior corresponding to the above run is (x 0, y 0 ) (x 1, y 1 ) (x 2, y 2 ) I can also look at a Mealy machine as a function M : I ω O ω which to every infinite input sequence x 0 x 1 assigns an infinite output sequence y 0 y 1 = M(x 0 x 1 ) defined as above. Quiz: why is this a function? is it a total function? Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 28 / 36

Types of semantics operational runs, trees, transition systems,... denotational sets (e.g., of behaviors), functions (on values, streams, signals,...), relations,... Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 29 / 36

Expressiveness How powerful is a modeling language? What kind of systems can it express? Mathematically: which types of sets, functions,... can it express? Can we compare modeling languages? When are two systems similar? equivalent? When are two formalisms equivalent? i.e., for any system expressed in formalism A, there exists an equivalent/similar system expressed in formalism B. Many notions of equivalence different notions of expressiveness: language containement, language equivalence, simulations, bisimulations,... Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 30 / 36

Expressiveness E.g., Chomsky hierarchy: Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 31 / 36

Expressiveness E.g., Chomsky hierarchy: Not much work in comparing heterogeneous modeling languages (e.g., discrete, continuous, dataflow,...). Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 31 / 36

Expressiveness E.g., Chomsky hierarchy: Not much work in comparing heterogeneous modeling languages (e.g., discrete, continuous, dataflow,...). Homework: are Moore and Mealy machines equivalent? almost equivalent? In what sense? (be precise) Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 31 / 36

Input-completeness Input-completeness (also called input-enabledness): system is able to accept any input at any given time. Formally: transition / output functions of automata/fsms are total. Together with non-determinism, interesting generic propery of systems, with different meanings and usages. Example: a s b 0 s c 1 s 2 This DFA has a partial transition function δ. Can it be made total? a Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 32 / 36

Input-completeness This DFA has a partial transition function δ. Can it be made total? a s 0 b s 1 c s 2 a Answer: it depends. If the automaton is to be used as an acceptor, yes. How? If the automaton is to be used as a generator, probably not useful. 2 Why? 2 The term input-complete is not very appropriate here, since generators have only outputs. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 33 / 36

Input-completeness Different meanings and usages of partial inputs: Requirements: I require that the environment never provides this input (at that time). This can be useful for contract-based design. More about this when we talk about composition. Example: read() init() write() Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 34 / 36

Input-completeness Different meanings and usages of partial inputs: Requirements: I require that the environment never provides this input (at that time). This can be useful for contract-based design. More about this when we talk about composition. Example: read() init() write() Assumptions: I know that the environment will never provide this input (at that time). Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 34 / 36

Don t cares In the assumptions case, missing inputs can be interpreted as don t cares. They can be used for instance to optimize implementations. Example: Two boolean inputs, x, y. One output z: must be 0 if x = y, 1 otherwise. Assumption: x and y cannot be both 1. Suppose our library only has OR, NOT gates. Given the assumption, I only need an OR gate. Ignoring the assumption, I would have to implement a XOR. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 35 / 36

Don t cares In the assumptions case, missing inputs can be interpreted as don t cares. They can be used for instance to optimize implementations. Example: Two boolean inputs, x, y. One output z: must be 0 if x = y, 1 otherwise. Assumption: x and y cannot be both 1. Suppose our library only has OR, NOT gates. Given the assumption, I only need an OR gate. Ignoring the assumption, I would have to implement a XOR. More on this on logic synthesis. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 35 / 36

Bibliography Halbwachs, N., Caspi, P., Raymond, P., and Pilaud, D. (1991). The synchronous dataflow programming language Lustre. Proceedings of the IEEE, 79(9):1305 1320. Hopcroft, J. E. and Ullman, J. D. (1990). Introduction To Automata Theory, Languages, And Computation. Addison-Wesley. Kohavi, Z. (1978). Switching and finite automata theory, 2nd ed. McGraw-Hill. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 36 / 36