Digital Itegrated Circuits YuZhuo Fu cotact:fuyuzhuo@ic.sjtu.edu.c Office locatio:417 room WeiDiaZi buildig,no 800 DogChua road,mihag Camus Itroductio
outlie CMOS at a glace CMOS static behavior CMOS dyamic behavior Power, Eergy, ad Eergy Delay Persective tech. /48
A trasistor Activity 1) If the width icreases, the curret will icrease decrease ot chage ) If the legth icreases, the curret will icrease decrease ot chage 3) If the suly voltage icreases, the maximum trasistor curret will icrease decrease ot chage 4) If the width icreases, its gate caacitace will icrease decrease ot chage 5) If the legth icreases, its gate caacitace will icrease decrease ot chage 6) If the suly voltage, the gate caacitace of each trasistor will icrease decrease ot chage 3/48
A trasistor Activity 1) If the width icreases, the curret will icrease decrease ot chage ) If the legth icreases, the curret will icrease decrease ot chage 3) If the suly voltage icreases, the maximum trasistor curret will icrease decrease ot chage 4) If the width icreases, its gate caacitace will icrease decrease ot chage 5) If the legth icreases, its gate caacitace will icrease decrease ot chage 6) If the suly voltage, the gate caacitace of each trasistor will icrease decrease ot chage 4/48
CMOS Iverter DD N Well DD I PMOS Out PMOS l Cotacts NMOS Polysilico I Out Metal 1 NMOS GND 5/48
A First Glace of CMOS A switch with ifiite off-resistace ad a fiite oresistace Whe gs < t,mos is off whe gs > t,mos is o just like a resistace R o whe i =dd,mos o,mos off Whe i =0,MOS off,mos o GS R o GS < T GS > T 6
CMOS Iverter First-Order DC Aalysis DD DD out R out OL = 0 OH = DD M = f(r, R ) R i = DD i = 0 7/48
CMOS Iverter: Trasiet Resose DD DD R t HL = f(r o.c L ) = 0.69 R o C L out out C L C L R i = 0 (a) Low-to-high i = DD (b) High-to-low 8/48
DC Resose DD Whe i = 0 => out = DD Whe i = DD => out = 0 I betwee, out deeds o trasistor size ad curret By KCL, must settle such that I ds = I ds We could solve equatios,but grahical solutio gives more isight i I ds I ds out 9/48
Trasistor Oeratio For what i ad out are MOS ad MOS i Cutoff? Liear? Saturatio? 10/48
MOS Oeratio Cutoff Liear Saturated gs < gs > ds < gs > ds > DD i I ds I ds out 11/48
MOS Oeratio Cutoff Liear Saturated gs < t gs > t ds < gs t gs > t ds > gs t DD i I ds I ds out 1/48
MOS Oeratio Cutoff Liear Saturated gs < t gs > t gs > t ds < gs t ds > gs t DD gs = i i I ds out ds = out I ds 13/48
MOS Oeratio Cutoff Liear Saturated gs < t i < t gs > t i > t ds < gs t out < i - t gs > t i > t ds > gs t out > i - t DD gs = i i I ds out ds = out I ds 14/48
MOS Oeratio Cutoff Liear Saturated gs > gs < ds > gs < ds < DD i I ds I ds out 15/48
MOS Oeratio Cutoff Liear Saturated gs > t gs < t ds > gs t gs < t ds < gs t DD i I ds I ds out 16/48
MOS Oeratio Cutoff Liear Saturated gs > t gs < t ds > gs t gs < t ds < gs t DD gs = i - DD t < 0 ds = out - DD i I ds I ds out 17/48
MOS Oeratio Cutoff Liear Saturated gs > t i > DD + t gs < t i < DD + t ds > gs t out > i - t gs < t i < DD + t ds < gs t out < i - t gs = i - DD ds = out - DD t < 0 i DD I ds out I ds 18/48
CMOS roerties High oise margis, the voltage swig is equal to the suly voltage Ratioless circuit structure Low outut imedace High iut resistace Low ower 19/48
PMOS Load Lies i = DD + GS I D = - I D out = DD + DS I D out I D i =0 I D I D i =0 i =1.5 i =1.5 GS =-1 DS DS out GS =-.5 i = DD + GS I D = - I D out = DD + DS 0/48
CMOS Iverter Load Characteristics I D i = 0 i =.5 PMOS i = 0.5 i = NMOS i = 1 i = 1.5 i = 1.5 i = 1 i = i = 1.5 i = 1 i = 0.5 i =.5 i = 0 out 1/48
CMOS Iverter TC Summary of CMOS iverter oeratio Regio Coditio P-device N-device outut A [0,t] liear cutoff DD B [t,dd/] liear saturated DD/ C =DD/ saturated saturated X dro D [DD/,DD- TP ] saturated liear <DD/ E [DD- TP, DD] cutoff liear 0 /48
TTL NAND 3/48
Other iverters 4/48
outlie CMOS at a glace CMOS static behavior CMOS dyamic behavior Power, Eergy, ad Eergy Delay Persective tech. 5/48
CMOS static behavior CMOS threshold voltage CMOS oise margi CMOS gai DC robust 6/48
I D Switchig Threshold as a fuctio of k C M M ox Trasistor Ratio ( M T ) k ( ) M DD T ( W ( L T GS r 1 r DD ) ) r( DD 1 r SAT cl GT T Lv T ( W ( W ) L ) L k ) ' v k r ' sat C k k ( ox W DD GS M v v sat sat T T W W ( M T ) ) 0 7
Switchig threshold of CMOS iverter Assumig W /W =8, calculatig M =? r k k ' ' W W L L 30*( 1) *8 3.3 115*0.63 ( r T ) ( DD T ) M 1 r 0.63 0.4 (0.43 ) 3.3(.5 0.4 ) 0.75 3.3*1.9 1 3.3 1 3.3 1.63 8/48
Switchig threshold of CMOS iverter ( W ( W ) L ) L ' k k ' ( ( DD M M ) T T ) 6 0.63 11510 0.63(1.5 0.43 ) 6 3010 1(1.5 0.4 1 ) 3.5 This rate let M = dd /! 9/48
Switchig Threshold as a fuctio of Trasistor Ratio M 1.8 1.7 1.6 1.5 1.4 1.3 1. 1.1 1 M is relatively isesitive to variatios i the device ratio Icreasig the width of the PMOS or NMOS moves M toward DD or GND (3, 1.) (.5, 1.18) (, 1.13) 0.9 0.8 10 0 10 1 W/W 30/48
CMOS static behavior CMOS threshold voltage CMOS oise margi CMOS gai DC robust 31/48
Noise Margi NM L The differece i maximum LOW iut voltage recogized by the receivig gate ad the maximum LOW outut voltage roduced by the drivig gate NM L = IL - OL NM H The differece i miimum HIGH iut voltage recogized by the receivig gate ad the miimum HIGH outut voltage roduced by the drivig gate NM H = OH - IH 3/48
Noise Margi IH=miimum HIGH iut voltage IL=maximum LOW iut voltage OH=miimum HIGH outut voltage OL=maximum LOW outut voltage Logical High Outut Rage Outut Characteristics DD OH NM H Iut Characteristics Logical High Iut Rage IH IL Idetermiate Regio Logical Low Outut Rage OL NM L GND Logical Low Iut Rage 33/48
Determiig IH ad IL 34/48
Determiig IH ad IL out A simlified aroach! OH IH IL ( OH g OL ) g DD M IH M g M, IL M DD g M NM H DD IH, NM L IL i OL IL IH 35/48
Determiig IH ad IL i out OH t M out OL IL IH i t 36/48
Examle g=-30, dd =.5, M =1.0 Please estimate NM H ad NM L IH = M - M /G=1.0*(1+1/30)=1.03 IL =( DD - M )/G+ M =-1.5/30+1.0=0.95 NM H = OH - IH =.5-1.03=1.47 NM L = IL - OL =0.95 37/48
CMOS static behavior CMOS threshold voltage CMOS oise margi CMOS gai DC robust 38/48
0 0.5 1 1.5.5-18 -16-14 -1-10 -8-6 -4-0 i () gai Iverter Gai ) )( ( 1 ) ( 1 ) ( ) ( ) (1 ) (1 T M T M T DD i T i DD out out i out M i k k k k k k k d d g l l l l l l l l l 39/48 0 )) ( ()1 ( ) ()1 ( out DD T DD i out T i k k l l
A examle Assume a iverter i the geeric 0.5um CMOS techology desiged with a PMOS-to-NMOS ratio of 3.4 ad with the NMOS trasistor miimum size (W=0.375um, L=0.5um,W/L=1.5),Please give the gai of M, ad IL, IH,NM L,NM H, TC curve 40/48
A examle:iverter Gai ID(M ) k (M T )(1 l ) out 6 0.375 11510 0.63(1.5 0.43 0.63 ) (1 0.061.5) 5910 0.5 1 k k g I ( ) l l D 1 5910 M 6 11510 6 0.375 0.63 3010 0.5 0.06 0.1 6 6 A 3.40.375 1.0 0.5 7.5 The gai is almost urely determied by techology arameters! 41/48
A examle : oise margi G=-M/(IH-M) IH=M-M/G=1.5*(1+1/7.5)=1.3 G=-(DD-M)/(M-IL) IL=(DD-M)/G+M=-1.5/7.5+1.5=1. NMH=OH-IH=.5-1.3=1. NML=IL-OL=1. Simulated valued IL=1.03 IH=1.45 out OH M Gai is overestimated Liear aroximatio of TC OL IL IH i 4/48
CMOS static behavior CMOS threshold voltage CMOS oise margi CMOS gai DC robust 43/48
Imact of Process ariatios out ().5 1.5 1 Good NMOS Bad PMOS The variatios of device maily cause a shift i the switchig threshold, this robust behavior esures fuctioality of the gate over a wide rage of coditios Nomial Good PMOS Bad NMOS 0.5 0 0 0.5 1 1.5.5 i () 44/48
Trasfer characteristics of skewed iverter uskewed HI-Skewed LOW-Skewed 45/48
Gai as a fuctio of DD.5 kt DD ~ 4 ~ 4 5m mi q 0. out () g 1.5 1 0.5 10% 17% 0 0 0.5 1 1.5.5 () i ( M T 1 )( l l ) out () 0.15 0.1 0.05 Gai=-1 0 0 0.05 0.1 0.15 0. () i Low ower voltage is useful! But ot too low 46/48