Combinational Logic. Mantıksal Tasarım BBM231. section instructor: Ufuk Çelikcan

Combinational Logic Mantıksal Tasarım BBM23 section instructor: Ufuk Çelikcan

Classification. Combinational no memory outputs depends on only the present inputs expressed by Boolean functions 2. Sequential storage elements + logic gates the content of the storage elements define the state of the circuit outputs are functions of both input and current state state is a function of previous inputs outputs not only depend the present inputs but also the past inputs 2

Combinational Circuits n binary inputs Combinational circuit (logic gates) m binary outputs 3 n input bits 2 n possible binary input combinations For each possible input combination, there is one possible output value truth table Boolean functions (with n input variables) Examples: adders, subtractors, comparators, decoders, encoders, multiplexers.

Analysis & Design of Combinational Logic Analysis: to find out the function that a given circuit implements We are given a logic circuit and we are expected to find out. Boolean function(s) 2. Truth table 3. A possible explanation of the circuit operation (i.e. what it does) 4

Analysis of Combinational Logic First, make sure that the given circuit is, indeed, combinational. Verifying the circuit is combinational No memory elements No feedback paths (connections) Second, obtain a Boolean function for each output or the truth table Finally, interpret the operation of the circuit from the derived Boolean functions or truth table What is it the circuit doing? Addition, subtraction, multiplication, comparison etc. 5

Example Obtaining Boolean Function a b c T F a b c T 2 T 4 a b T 3 a c F 2 b c 6

Example: Obtaining Boolean Function Boolean expressions for named wires T = abc T 2 = a + b + c F 2 = T 3 = T 4 = T 3 T 2 F = T + T 4 = = = = 7

Example: Obtaining Boolean Function Boolean expressions for named wires T = abc T 2 = a + b + c F 2 = ab + ac + bc T 3 = F 2 = (ab + ac + bc) T 4 = T 3 T 2 = (ab + ac + bc) (a + b + c) F = T + T 4 = abc + (ab + ac + bc) (a + b + c) = abc + ((a + b )(a + c )(b + c )) (a + b + c) = abc + ( (a + a c + a b + b c )(b + c ) ) (a + b + c) = abc + (a b + a c + a b c + b c ) (a + b + c) = abc + (a b + a c + b c ) (a + b + c) 8

Example: Obtaining Boolean Function Boolean expressions for outputs F 2 = ab + ac + bc F = F = F = F = 9

Example: Obtaining Boolean Function Boolean expressions for outputs F 2 = ab + ac + bc F = abc + (a b + a c + b c ) (a + b + c) F = abc + a b c + a bc + ab c F = a(bc + b c ) + a (b c + bc ) F = a(b c) + a (b c) F = ( a b c ) : Odd Function

Example: Obtaining Truth Table F = a b c F 2 = ab + ac + bc carry sum a b c T T 2 T 3 T 4 F 2 F

Example: Obtaining Truth Table F = a b c F 2 = ab + ac + bc carry sum a b c T T 2 T 3 T 4 F 2 F This is what we call full-adder (FA) 2

3 Design of Combinational Logic Design Procedure: We start with the verbal specification about what the resulting circuit will do for us (i.e. which function it will implement) Specifications are often verbal, and very likely incomplete and ambiguous (if not even faulty) Wrong interpretations can result in incorrect circuit We are expected to find. First, Boolean function(s) (or truth table) to realize the desired functionality 2. Logic circuit implementing the Boolean function(s) (or the truth table)

Possible Design Steps. Find out the number of inputs and outputs 2. Derive the truth table that defines the required relationship between inputs and outputs 3. Obtain a simplified Boolean function for each output 4. Draw the logic diagram (enter your design into CAD) 5. Verify the correctness of the design 4

Design Constraints From the truth table, we can obtain a variety of simplified expressions, all realizing the same function. Question: which one to choose? The design constraints may help in the selection process Constraints: number of gates propagation time of the signal all the way from the inputs to the outputs number of inputs to a gate number of interconnections power consumption driving capability of each gate 5

Example: Design Process BCD-to-242 Converter Verbal specification: Given a BCD digit (i.e. {,,, 9}), the circuit computes 242 code equivalent of the decimal number Step : how many inputs and how many outputs? four inputs and four outputs Step 2: Obtain the truth table etc. 6

BCD-to-242 Converter Truth Table Inputs Outputs A B C D x y z t 7

Binary coded decimal (BCD) is a system of writing numerals that assigns a fourdigit binary code to each digit through 9 in a decimal (base-) numeral. The fourbit BCD code for any particular single base- digit is its representation in binary notation, as follows: = = 2 = 3 = 4 = 5 = 6 = 7 = 8 = 9 = Numbers larger than 9, having two or more digits in the decimal system, are expressed digit by digit. For example, the BCD rendition of the base- number 895 is

242 Code a weighted code. The weights assigned to the four digits are 2, 4, 2, and. The 242 code is the same as that in BCD from to 4; however, it varies from 5 to 9. For example, in this case the bit combination represents decimal 4; whereas the bit combination is interpreted as the decimal 7, as obtained from 2 + 4 + 2 + = 7. This is also a self-complementarycode, that is, the 9 s complement of the decimal number is obtained by changing the s to s and s to s.

BCD-to-242 Converter Truth Table Inputs Outputs A B C D x y z t 2

BCD-to-242 Converter Truth Table Inputs Outputs A B C D x y z t 2

BCD-to-242 Converter Step 3: Obtain simplified Boolean expression for each output Output x: AB CD A B C D x The rest X x = 22

BCD-to-242 Converter Step 3: Obtain simplified Boolean expression for each output Output x: AB CD x x x x x x A B C D x The rest X 23

BCD-to-242 Converter Step 3: Obtain simplified Boolean expression for each output Output x: AB CD x x x x x x A B C D x The rest X x = BD + BC + A 24

CD 25 Boolean Expressions for Outputs AB CD AB Output y: Output z: A B C D y z y = z = The rest X X

CD 26 Boolean Expressions for Outputs AB X X X X X X CD Output y: Output z: AB X X X X X X A B C D y z y = z = The rest X X

CD 27 Boolean Expressions for Outputs AB X X X X X X CD Output y: Output z: AB X X X X X X A B C D y z The rest X X y = A + BD + BC z = A + B C + BC D

Boolean Expressions for Outputs CD Output t: AB A B C D T t = The rest X

Boolean Expressions for Outputs CD Output t: AB X X X X X X t = A B C D T Step 4: Draw the logic diagram x = BC + BD + A y = A + BD + BC z = A + B C + BC D The rest X 29

Boolean Expressions for Outputs CD Output t: AB X X X X X X t = D A B C D T Step 4: Draw the logic diagram x = BC + BD + A y = A + BD + BC z = A + B C + BC D The rest X 3

Example: Logic Diagram A B C D x = BC + BD + A y = A + BD + BC z = A + B C + BC D 3 t = D

Example: Verification Step 5: Check the functional correctness of the logic circuit Apply all possible input combinations And check if the circuit generates the correct outputs for each input combinations For large circuits with many input combinations, this may not be feasible. Statistical techniques may be used to verify the correctness of large circuits with many input combinations 32

Binary Adder/Subtractor (Arithmetic) Addition of two binary digits + =, + =, + =, and + = The result has two components the sum (S) the carry (C) (Arithmetic) Addition of three binary digits 33 + + = + + = + + = + + = + + = + + = + + = + + =

Half Adder Truth table x y C S S = x y + xy = x y C = xy x y S HA C 34

Full Adder /2 A circuit that performs the arithmetic sum of three bits Three inputs the range of output is [, 3] Two binary outputs 35 x y z C S

Karnaugh Maps Full Adder 2/2 yz x yz x S =? C =? Two level implementation st level: three AND gates 2 nd level: One OR gate 36

Karnaugh Maps Full Adder 2/2 yz x yz x S = xy z + x y z + xyz + x yz =... =... = x y z C = xy + xz + yz = xyz + xyz + xy z + x yz Two level implementation st level: three AND gates 2 nd level: One OR gate 37

Full Adder: Hierarchical Realization Sum S = x y z = (x y) z Carry C = xyz + xyz + xy z + x yz = xy + (xy + x y) z = xy + (x y) z This allows us to implement a full-adder using two half adders. x y HA S C HA S C x y z = S C z 39

Full Adder Using Half Adders x y HA HA S z C 4

Integer Addition /2 Binary adder: A digital circuit that produces the arithmetic sum of two binary numbers A = (a n-, a n-2,, a, a ) B = (b n-, b n-2,, b, b ) A simple case: 4-bit binary adder a 3 b 3 a 2 b 2 a b a b C 4 C x FA S y z C 3 C x FA S y z C 2 C x FA S y z C C x HA S y S 3 S 2 S S 4

Integer Addition 2/2 a 3 b 3 a 2 b 2 a b a b C 4 C x FA S y z C 3 C x FA S y z C 2 C x FA S y z C C x FA S y z C = S 3 S 2 S S Ripple-carry adder 42

Hierarchical Design Methodology The design methodology we used to build carry-ripple adder is what is referred as hierarchical design. In classical design, we have: 9 inputs including C. 5 outputs Truth tables with 2 9 = 52 entries We have to optimize five Boolean functions with 9 variables each. Hierarchical design we divide our design into smaller functional blocks connect functional units to produce the big functionality 43

44 Full Adder in Xilinx

45 Two-bit Adder in Xilinx

Subtractor Recall how we do subtraction (2 s complement) X Y = X + (2 n Y) = X + ~Y + x 3 y 3 x 2 y 2 x y x y logic- a 3 b 3 a 2 b 2 a b a b C 4 4-bit adder circuit C S 3 S 2 S S C 4 46 S 3 S 2 S S

Carry Propagation a 3 b 3 a 2 b 2 a b a b C 4 C x FA S y z C 3 C x FA S y z C 2 C x FA S y z C C x FA S y z C = S 3 S 2 S S Ripple-carry adder What is the total propagation time of 4-bit ripple-carry adder? FA : propagation time of a single full adder. We have four full adders connected in cascaded fashion Total propagation time:?? 47

Carry Propagation Propagation time of a full adder XOR 2 AND = 2 OR FA 2 XOR a i P i b i S i G i C i+ C i 48 carry-propagate: carry-generate:

Carry Propagation a 3 b 3 a 2 b 2 a b a b C C 3 P P 3 C 2 2 C P P C 4 S3 C 3 S2 C 2 S C S Carry-lookahead design 49

Carry Propagation a 3 b 3 a 2 b 2 a b a b C C 3 P P 3 C 2 2 C P P C 4 S3 C 3 Delays P, P, P 2, P 3 : XOR 2 AND S2 C 2 S C S 5 C (S ): 2 AND C 2 (S ): 4 AND C 3 (S 2 ): 6 AND C 4 (S 3 ): 8 AND + 2 AND 4 AND + 2 AND 6 AND + 2 AND 8 AND + 2 AND AND

4-bit Carry Lookahead Adder a 3 b 3 P 3 C 4 C 4 G 3 a 2 b 2 P 2 C 3 P 3 S 3 a b G 2 P Carry Lookahead circuit C 2 P 2 P S S 2 G 2 C a b P G C P S C C 5

Decoders A binary code of n bits capable of representing 2 n distinct elements of coded information A decoder is a combinational circuit that converts binary information from n binary inputs to a maximum of 2 n unique output lines x y 2x4 decoder d d d 2 d 3 x y d d d 2 d 3 d = d = d 2 = d 3 = 52

Decoder with Enable Input x y 2x4 decoder d d d 2 d 3 e e x y d d d 2 d 3 X X 53

Demultiplexer A demultiplexer is a combinational circuit it receives information from a single input line and directs it one of 2 n output lines It has n selection lines as to which output will get the input x y 2x4 decoder d d d 2 d 3 x, y e d d d 2 d 3 e d = e when x = and y = d = e when x = and y = d 2 = e when x = and y = d 3 = e when x = and y = 56

Demultiplexer e x x 57

Demultiplexer e x2 x x 58

Demultiplexer x 59

Combining Decoders y z x 2x4 decoder e d d d 2 d 3 x y z active output 2x4 decoder e d 4 d 5 d 6 d 7 Decoders with enable inputs can be connected together to form a larger decoder circuit. Figure shows two 2-to-4-line decoders with enable inputs connected to form a 3-to-8-line decoder. When x=, the top decoder is enabled and the other is disabled. The bottom decoder outputs are all s, and the top four outputs generate minterms to. When x=, the enable conditions are reversed: The bottom decoder outputs generate minterms to, while the outputs of the top decoder are all s. This example demonstrates the usefulness of enable inputs in decoders

Combining Decoders x x n- nx2 n Decoder- e d d d 2 n - nx2 n Decoder-2 e nx2 n Decoder-2 p e d 2 n+p- - x n x n+p- px2 p Decoder 6

Decoder as a Building Block A decoder provides the 2 n minterms of n input variable x y 2x4 decoder d = x y d = x y d 2 = xy d 3 = xy We can use a decoder and OR gates to realize any Boolean function expressed as sum of minterms Any combinational circuit with n inputs and m outputs can be realized using an n-to-2 n line decoder and m OR gates. 62

Decoder as a Building Block-ROM x y z 3x8 decoder d = x y z d = x y z d 2 = x yz d 3 = x yz d 4 = xy z d 5 = xy z d 6 = xyz d 7 = xyz F 2 F F 63

Decoder as a Building Block-ROM x y z 3x8 decoder F 2 F F 64

Example: Decoder as a Building Block Full adder C = xy + xz + yz S = x y z x y z 3x8 decoder 2 3 4 5 6 7 C S 65

Encoders An encoder is a combinational circuit that performs the inverse operation of a decoder number of inputs: 2 n number of outputs: n the output lines generate the binary code corresponding to the input value Example: n = 2 d d d 2 d 3 x y 66

Priority Encoder Problem with a regular encoder: only one input can be active at any given time the output is undefined for the case when more than one input is active simultaneously. Priority encoder: there is a priority among the inputs d d d 2 d 3 a b V X X X X X X X X 67

Priority Encoder if two or more inputs are equal to at the same time, the input having the highest priority will take precedence. In addition to the two outputs a and b, the circuit has a third output designated by V ; this is a valid bit indicator that is set to when one or more inputs are equal to. If all inputs are, there is no valid input and V is equal to. The other two outputs are not inspected when V equals and are specified as don t-care conditions. Priority encoder: d d d 2 d 3 a b V X X X X X X X X 68

4-bit Priority Encoder In the truth table X for input variables represents both and. Good for condensing the truth table Example: X (, ) This means d has priority over d d 3 has the highest priority d 2 has the next d has the lowest priority 69 V =? The condition for output V is an OR function of all the input variables.

Maps for 4-bit Priority Encoder d 2 d 3 d d a = d 2 d 3 d d b = 7

Maps for 4-bit Priority Encoder d 2 d 3 d d X a = d 2 d 3 d d X b = 7

4-bit Priority Encoder: Circuit a = d 2 + d 3 b = d d 2 + d 3 V = d + d + d 2 + d 3 d 3 b d 2 d a d V 72

Multiplexers A combinational circuit It selects binary information from one of the many input lines and directs it to a single output line. Many inputs m One output line n selection lines n =? Example: 2-to--line multiplexer 2 input lines I, I output line Y select line S Y =? S Y I I Function Table 73

2-to--Line Multiplexer Y = S I + SI I S Y I Special Symbol I I MUX Y 74 S

4-to--Line Multiplexer 4 input lines: I, I, I 2, I 3 output line: Y 2 select lines: S, S. S S Y Y =? Interpretation: In case S = and S =, Y selects I In case S = and S =, Y selects I In case S = and S =, Y selects I 2 In case S = and S =, Y selects I 3 75

4-to--Line Multiplexer: Circuit I I Y = S S I + S S I + S S I 2 + S S I 3 Y I 2 I I 3 I MUX Y I 2 2 I 3 3 S S 76 S S

Multiplexer with Enable Input To select a certain building block we use enable inputs E E S Y A B C D MUX 2 3 Y XX A B C D S S 77

Multiple-Bit Selection Logic /2 A multiplexer is also referred as a data selector A multiple-bit selection logic selects a group of bits E A B 2 2 MUX 2 Y A = B = Y = S 78

Multiple-bit Selection Logic 2/2 E E S Y a X all s b MUX y A B S E a A 2 MUX 2 Y MUX y B 2 b 79 S

Design with Multiplexers /2 Reminder: design with decoders Half adder C = xy = (3) S = x y = x y + xy = (, 2) x y 2x4 decoder 2 3 S C A closer look will reveal that a multiplexer is nothing but a decoder with OR gates 8

Design with Multiplexers 2/2 4-to--line multiplexer I I MUX Y I 2 I 3 2 3 S S S x S y S S = x y, S S = x y, S S = xy, S S = xy Y = S S I + S S I + S S I 2 + S S I 3 Y = x y I + x y I + xy I 2 + xyi 3 Y = 8

Example: Design with Multiplexers Example: S = (, 2) = I = I MUX Y = = I 2 I 3 2 3 S x y S 82

Example: Design with Multiplexers Example: S = (, 2) = I = = I 2 I MUX Y 2 = I 3 3 S x y S 83

Design with Multiplexers Efficiently More efficient way to implement an n- variable Boolean function. Use a multiplexer with n- selection inputs 2. First (n-) variables are connected to the selection inputs 3. The remaining variable is connected to data inputs Example: Y = (, 2) = I MUX Y = S I + S I = I Y = x I + x I 84 x

Design with Multiplexers Efficiently More efficient way to implement an n- variable Boolean function. Use a multiplexer with n- selection inputs 2. First (n-) variables are connected to the selection inputs 3. The remaining variable is connected to data inputs Example: Y = (, 2) y = I MUX Y = S I + S I y' = I Y = x I + x I 85 x

Design with Multiplexers General procedure for n-variable Boolean function F(x, x 2,..., x n ). The Boolean function is expressed in a truth table 2. The first (n-) variables are applied to the selection inputs of the multiplexer (x, x 2,..., x n- ) 3. For each combination of these (n-) variables, evaluate the value of the output as a function of the last variable, x n.,, x n, x n 4. These values are applied to the data inputs in the proper order. 86

Example: Design with Multiplexers F(x, y, z) = (, 2, 6, 7) F = x y z + x yz + xyz + xyz Y = S S I + S S I + S S I 2 + S S I 3 I = I = I 2 = I 3 = x y z F F = F = F = 87 F =

Example: Design with Multiplexers F(x, y, z) = (, 2, 6, 7) F = x y z + x yz + xyz + xyz Y = S S I + S S I + S S I 2 + S S I 3 I = z I = z I 2 = I 3 = x y z F F =z F =z F = 88 F =

Example: Design with Multiplexers F = x y z + x yz + xyz + xyz F = z when x = and y = F = z when x = and y = F = when x = and y = F = when x = and y = z z' MUX 2 3 F = x y z + x yz + xy x y 89

Design with Multiplexers I I I 2 MUX 2 F x y (I ) + x y(i ) + xy (I 2 ) + xy(i 3 ) I 3 3 x y F=x y () + x y() + xy () + xy() F=x y (z) + x y(z ) + xy () + xy() F=x y (P(z,t,q,w)) + x y(q(z,t,q,w)) + xy (R(z,t,q,w)) + xy(s(z,t,q,w)) 9

Design with Multiplexers z I t q Combinational Circuit I I 2 MUX 2 F w I 3 3 x y F=x y (P(z,t,q,w)) + x y(q(z,t,q,w)) + xy (R(z,t,q,w)) + xy(s(z,t,q,w)) 9

Combining Multiplexers MUX 2 3 S 2 S MUX MUX 2 S 3 92 S 2 S

Example C C MUX X C2 MUX X MUX C MUX 3 X X C 4 C5 X 2 MUX X 2 X MUX C 6 X 2 X C 7 MUX X 2 X X 93

Example- 2 Level ROM x x x n- p x2 n ROM z z z p- p x2 n ROM z z z p- p x2 n ROM 2 k - z z z p- x n X n+ X n+k- 2 k - 2 k - 2 k - MUX MUX MUX z z z p- 94

Example- 2 Level ROM x x x n- p x2 n ROM z z z p- p x2 n ROM z z z p- p x2 n ROM 2 k - z z z p- x n X n+ X n+k- 2 k - 2 k - 2 k - MUX MUX MUX z z z p- 95

Example- 2 Level ROM x x x n- p x2 n ROM z z z p- p x2 n ROM z z z p- p x2 n ROM 2 k - z z z p- x n X n+ X n+k- 2 k - 2 k - 2 k - MUX MUX MUX z z z p- 96

Example- 2 Level ROM x x x n- p x2 n ROM z z z p- p x2 n ROM z z z p- p x2 n ROM 2 k - z z z p- X n X n+ X n+k- 2 k - 2 k - 2 k - MUX MUX MUX z z z p- 97

Example- 2 Level ROM x x x n- p x2 n ROM z z z p- p x2 n ROM z z z p- p x2 n ROM 2 k - z z z p- x n X n+ X n+k- 2 k - 2 k - 2 k - MUX MUX MUX z z z p- 98

Example- 2 Level ROM x x x n- p x2 n ROM z z z p- p x2 n ROM z z z p- p x2 n ROM 2 k - z z z p- x n X n+ X n+k- 2 k - 2 k - 2 k - MUX MUX MUX z z z p- 99

Three-State Buffers A different type of logic element Instead of two states (i.e., ), it exhibits three states (,, Z) Z (Hi-Z) is called high-impedance When in Hi-Z state the circuit behaves like an open circuit (the output appears to be disconnected, and the circuit has no logic significance) input control input A C Y = A if C = Y = Hi-Z if C =

3-State Buffers Remember that we cannot connect the outputs of other logic gates. We can connect the outputs of three-state buffers provided that no two three-state buffers drive the same wire to opposite and values at the same time. C A Y X Hi-Z

Example- 3 State MUX x x x n- n x2 n Decoder z z z 2 n - y y Y y 2 n - 2

3 Multiplexing with 3-State Buffers A S B T A T B Y Z X Z X Z X Z X Y T B T A B A S It is, in fact, a 2-to--line MUX

4 Two Active Outputs - A C B T A T B Y C What will happen if C = C =? Y B A C C Z X X X X X X

Design Principle with 3-State Buffers Designer must be sure that only one control input must be active at a time. Otherwise the circuit may be destroyed by the large amount of current flowing from the buffer output at logic- to the buffer output at logic-. x w S S E 2x4 decoder y z t 5

k x2 k ROM Example- 3 State Buffer & ROM x x x n- p x2 n ROM z z z p- p x2 n ROM 2 z z z p- p x2 n ROM 2 k z z z p- x n x n+ x n+k- 6 z z z p-

Busses with 3-State Buffers There are important uses of three-state buffers CPU Memory I/O Device 7

Gate Level Design Design with Verilog module decoder_2x4_gates(d, A, B, e); output [:3] D; input A, B, e; wire A_n, B_n; D = ea B D = ea B D 2 = eab D 3 = eab not G(A_n, A); not G2 (B_n, B); e B_n A_n and G3(D[], e, A_n, B_n); A G G3 D and G4(D[], e, A_n, B); B G2 G4 D and G5(D[2], e, A, B_n); and G6(D[3], e, A, B); G5 D 2 endmodule; G6 D 3 8

Dataflow Modeling Dataflow modeling uses a number of operators that act on operands About 3 different operators D = ea B D = ea B D 2 = eab D 3 = eab module decoder_2x4_dataflow( output [:3] D, input A, B, e); e A G G3 D assign D[] = e & ~A & ~B; assign D[] = e & ~A & B; B G2 G4 D assign D[2] = e & A & ~B; assign D[3] = e & A & B; G5 D 2 endmodule; G6 D 3 9

Dataflow Modeling Data type net Represents a physical connection between circuit elements e.g., wire, output, input. Continuous assignment assign A statement that assigns a value to a net e.g., assign D[] = e & ~A & ~B; e.g., assign A_lt_B = A < B; Bus type wire [:3] T; T[], T[3], T[..2];

Behavioral Modeling Represents digital circuits at a functional and algorithmic level Mostly used to describe sequential circuits Can also be used to describe combinational circuits module mux_2x_beh(m, A, B, S); output m; input A, B, S; reg m; always @(A or B or S); endmodule; if(s == ) m = A; else m = B;

Behavioral Modeling Output must be declared as reg data type always block Procedural assignment statements are executed every time there is a change in any of the variables listed after the @ symbol (i.e., sensitivity list). 2 module mux_4x_beh(output reg m, input I, I, I2, I3; input [:] S); always @(I or I or I2 or I3 or S); case (S) 2 b: m = I; 2 b: m = I; 2 b: m = I2; 2 b: m = I3; endcase endmodule;