Siusoidal stimulus Si i Si at every ode! We are goig to aalyze circuits for a sigle siusoid at a time which we are goig to write: vi ( t i si( t + φ But we are goig to use expoetial otatio v ( t si( t + φ ( e i v ( t ( e i vi ( t [ ie i φ t i e φ ] e e t + C. C. e t+ φ i φ t i e t+ φ / / Complex cojugate (same as first term, but with (j (-j wherever it occurs It is especially iterestig because ay voltage or curret i our circuit, if this is the oly iput, must also be siusoidal with the same frequecy, ad so ca also be writte i this form. vay ( t [ aye j iay ( t [ Iaye φ ( φ ] e ] e t t + C. C + C. C Because our equatios will be liear, the same thigs will happe to the complex cojugate terms as happe to the first terms, so they will just tag alog Phasors Each of the voltages betwee odes, ad each of the currets, ca the be represeted by a sigle complex umber (remember, this is for a sigle frequecy iput of a particular phase ad amplitude φ t vay ( t [ aye ] e + C. C ˆ ay { You ca ot use phasor otatio (without added precautios if you eed to multiply voltages ad currets (such as i a power calculatio, because that is ot liear! However, you must ot take the real part (or add the complex cojugate before you put back i the time depedece e -jt ˆay i ay ( t [ I e ] e φ ay { t + C. C Iˆ ay Î ay
Complex Trasfer Fuctio Impedaces of resistors, capacitors, iductors Z r ( r Z c ( C( j Z ( ( j To fid the equivalet impedace for a etwork, Use series or parallel coectios, Thevei equivalets. Or as a last resort Kerchoff s laws ad algebra Excite a system with a iput voltage v i Defie the output voltage v ay to be ay ode voltage (brach curret For a complex expoetial iput, the trasfer fuctio from iput to output( or ay voltage or curret ca the be writte: H ( + j + 3( j + d + d j + d ( j + 3 ( just multiply top ad bottom by e jt sufficiet times Impedace Admittace Suppose that the iput is defied as the voltage of a termial pair (port ad the output is defied as the curret ito the port: v (t i (t + jt t+ φv v( t e e Arbitrary TI jt t+ φi Circuit i( t Ie I e The impedace Z is defied as the ratio of the phasor voltage to phasor curret ( self trasfer fuctio φv φi Z( H ( e I I Suppose that the iput is defied as the curret of a termial pair (port ad the output is defied as the voltage ito the port: v (t i (t + jt t+ φv v( t e e Arbitrary TI jt t+ φi Circuit i( t Ie I e The admittace Z is defied as the ratio of the phasor curret to phasor voltage ( self trasfer fuctio I I φi φv Y ( H ( e
oltage ad Curret Gai Trasimpedace/admittace The voltage (curret gai is just the voltage (curret trasfer fuctio from oe port to aother port: I I φ φ Gi ( e I I If G >, the circuit has voltage (curret gai If G <, the circuit has loss or atteuatio v ( i ( t t + Arbitrary TI Circuit Gv ( e + φ φ i ( t v ( t Curret/voltage gai are uitless quatities Sometimes we are iterested i the trasfer of voltage to curret or vice versa v ( or i ( t t + J ( I Arbitrary liear Circuit I I K( e I e φ φ φ φ + i ( t or [ Ω] [ S] v ( t Direct Calculatio of H (o DEs To directly calculate the trasfer fuctio (impedace, trasimpedace, etc we ca geeralize the circuit aalysis cocept from the real domai to the phasor domai With the cocept of impedace (admittace, we ca ow directly aalyze a circuit without explicitly writig dow ay differetial equatios Use K, KC, mesh aalysis, loop aalysis, or ode aalysis where iductors ad capacitors are treated as complex resistors Bigger Example (o problem! Cosider a more complicated example: o H ( Z s eff ZC + Z C Z H ( R + R Z C C Z eff Z eff + Z C R + R Z C 3
Fidig the Magitude (quickly Fidig the Phase The magitude of the respose ca be calculated quickly by usig the property of the mag operator: H ( G ( j K ( jτ z( jτ z ( jτ ( jτ K jτ z jτ z G jτ jτ The magitude at DC depeds o G ad the umber of poles/zeros at DC. If K >, gai is zero. If K <, DC gai is ifiite. Otherwise if K, the gai is simply G p p p p the phase ca be computed quickly with the followig formula: K ( jτ z( jτ z p H ( p G ( j ( jτ ( jτ K p G + p ( j + p ( jτ z + p ( jτ z + p ( jτ p ( jτ p Now the secod term is simple to calculate for positive frequecies: π p ( j K K Iterpret this as sayig that multiplicatio by j is equivalet to rotatio by 9 degrees p p p Fid the Trasfer Fuctio Bode Plot Overview Excite a system with a iput voltage v i Defie the output voltage v ay to be ay ode voltage (brach curret For a complex expoetial iput, the trasfer fuctio from iput to output( or ay voltage or curret ca the be writte: H ( + j + 3( j + d + d j + d ( j + 3 This is foud by usig phasor otatio to chage circuits ito etworks of complex resistors, the applyig Kirchoff s laws repeatedly The put the trasfer fuctio ito stadard form: ( + j ( + j ( + j K z z z3 H ( G ( j ( + j ( + j ( + j p p p3 Each of the frequecies: i correspod to τ i time costats which are features of the circuit, ad are called break frequecies. Those that appear i the umerator are called zeros, ad those that appear i the deomiator are called poles. 4
Breakpoits Example Sice the trasfer fuctio will always result i a real voltage, the followig features ca appear: Real zeros Real poles Cojugate pairs of zeros Cojugate pairs of holes Each of these ca appear i multiple orders (two poles at the same frequecy, for example Additioal features of the fuctio are the costat G, ad the order of the overall term K Cosider the followig trasfer fuctio 5 j( + jτ H ( j ( + jτ ( + jτ 3 τ s τ s τ ps Break frequecies: ivert time costats Mrad/s Mrad/s 3 Grad/s j ( + j 5 H ( j ( + j ( + j 3 3 Magitude Phase Recall log of products is sum of logs Sice a b a + b H ( j db j ( + j 5 log ( + j ( + j j log + log+ j 5 log+ j log+ j 3 Plot each factor separately ad add them graphically 3 5 j( + jτ H ( j ( + jτ ( + jτ j H ( j { } + { + j } 5 { + j } { + j } Plot each factor separately ad add them graphically 3 3 5
Secod Order Circuit Bode Plot Bode Plot: Damped Case Quadratic poles or zeros have the followig form: j + ( j ζ + ( The roots ca be parameterized i terms of the dampig ratio: ζ ( j + ( j + ( + j dampig ratio Two equal poles ζ > ( j + ( jζ + ( + jτ( + jτ j ζ ± ζ Two real poles The case of ζ > ad ζ is a simple geeralizatio of simple poles (zeros. I the case that ζ >, the poles (zeros are at distict frequecies. For ζ, the poles are at the same real frequecy: ζ ( j τ + ( jτ + ( + jτ ( + j τ + jτ log+ j τ 4log+ jτ ( + jτ + ( + jτ ( jτ ( + j τ + Asymptotic Phase Shift is 8 Asymptotic Slope is 4 db/dec Uderdamped Case Uderdamped Mag Plot For ζ <, the poles are complex cojugates: ( j + ( j ζ + j ζ ± For / <<, this quadratic is egligible (db For / >>, we ca simplify: log ( j + ( j ζ + log ( j 4log I the trasitio regio / ~, thigs are tricky! ζ ζ ± j ζ ζ. ζ. ζ. ζ.4 ζ.6 ζ.8 ζ 6
Bode Plot Guidelies Physical Iterpretatio of Q-Factor I the trasitio regio, ote that at the breakpoit: ( j + ( j ζ + ( j + ( jζ + ζ Q From this you ca estimate the peakiess i the magitude respose Example: for ζ., the Bode magitude plot peaks by log(5 ~4 db The phase is much more difficult. Note for ζ, the phase respose is a step fuctio For ζ, the phase is two real poles at a fixed frequecy For <ζ<, the plot should go somewhere i betwee! For the series resoat circuit we have related the Q factor to very fudametal properties of the tak: w Q π w The tak quality factor relates how much eergy is stored i a tak to how much eergy loss is occurrig. If Q >>, the the tak pretty much rus itself eve if you tur off the source, the tak will cotiue to oscillate for several cycles (o the order of Q cycles Mechaical resoators ca be fabricated with extremely high Q S D Features of biliear trasfer fuctios Feature by Feature: For biliear trasfer fuctios, we ca put them ito the form: q ( j + z( j + z( j + z3 H ( j K ( j ( j + ( j + ( j + p Where the roots i the umerator are called zeros, ad the roots of the deomiator are called poles. Sice the roots come from a real polyomial (i j, they are either real, or come i complex cojugate pairs. We ca write those that come i pairs: q ( j + z ( j + ζ z z + z H ( j K ( j ( j + p ( ( j + ζ p p + p p p3 Overall factor K DC poles or Zeros Overall decade for decade shift with frequecy Each pole cotributes: far below its corer frequecy At the corer frequecy, the respose is dow by 3db /j far above its corer frequecy (-9 phase shift Each zero cotributes: below its corer frequecy At the corer frequecy, the respose is up 3 db j above its corer frequecy(9 phase shift 7
Feature by Feature: Thermal Equilibrium Each complex cojugate pair of poles cotribute: far below their corer frequecy /(j far above their corer frequecy (-8 phase shift At the resoace, the respose peaks up by a factor Q ( r ( og H j log ζ ζ Each complex cojugate pair of zeros cotribute: below their corer frequecy (j far above their corer frequecy (8 phase shift At the resoace, the respose dips dow by a factor Q og H j + log ζ ζ ( r ( ζ Q Balace betwee geeratio ad recombiatio determies o p o Geeratio is a fuctio of temperature G(T, but recombiatio oly depeds o the umber of electros ad holes (r,t p(r,t, because electros ad holes are rare. G G ( T + th G opt R k( p Electro ad Hole desities aw of Mass Actio But at thermal equilibrium, geeratio ad recombiatio must be equal: G R k( p G ( T p G ( T / k This holds true for doped as well as itrisic silico, ad we kow: i ( T th th cm 3 ( T i at 3 K This is called the law of Mass actio (the ame is borrowed from a similar thermal equilibrium law from chemistry p G ( / th T k i ( T This would t be of much use, except for the fact that we ca vary the umber of electros ad holes by addig fixed charges to the crystal by addig uclei which have a extra proto, or oe fewer that silico. I thermal equilibrium, if we icrease the umber of electros, the umber of holes goes dow, ad visa versa 8
Periodic Table of Elemets Compesatio (cot. Extra proto, ad therefore extra electro More doors tha acceptors: N d > N a i o Nd Na >> i po N N More acceptors tha doors: N a > N d d a p N N >> o a d i i o N N a d Mobility vs. Dopig i Silico at 3 o K Speed imit: elocity Saturatio c 3 m / s Thermal elocity 4 4 cm 4 cm cm µm µm default values: µ 4 µ p The field stregth to cause velocity saturatio may seem very large but it s oly a few volts i a moder trasistor! 9
Drift Curret Desity (Holes Drift Curret Desity (Electros Hole case: drift velocity is i same directio as E The hole drift curret desity is: J p dr hole drift curret desity J p dr v dp E x q p µ p E Electro case: drift velocity is i opposite directio as E electro drift curret desity J dr v d E x dr J ( q µ E qµ E The electro drift curret desity is: J dr (-q v d uits: Ccm - s - Acm - dr dr J J p + J ( qpµ p + qµ E Resistivity Electrostatics summary Bulk silico: uiform dopig cocetratio, away from surfaces -type example: i equilibrium, o N d Whe we apply a electric field, N d J qµ E qµ N Resistivity d E Coductivity σ qµ Nd, eff qµ ( Nd Na ρ Ω cm σ q µ Nd, eff I oe dimesio, the electrostatics equatios reduce to the E field growig or dimiishig depedig o the et charge: x ρ( x' E( x E( x + dx' ε x Which ca also be writte as a differetial equatio for the potetial (voltage. d φ ( x ρ( x dx ε
Net Charge Charge ersus Bias (depletio The et charge desity i a semicoductor is calculated from the umber of charge carriers ad fixed charges i a locatio: ρ( x q p( x ( x + N ( x N ( x ( If a regio does ot have the right umber of electros or holes to cacel the amout of charge from the dopats, the fixed charge of the dopats will ifluece the electric fields. d a As we icrease the reverse bias, the depletio regio grows to accommodate more charge D QJ ( D qn ax p ( D qn a φ Charge is ot a liear fuctio of voltage This is a o-liear capacitor We ca defie a small sigal capacitace for small sigals by breakig up the charge ito two terms Q J ( D + vd QJ ( D + q( vd bi Charge distributio i a MOS structure Reverse Bias ------------------------------------------- Oxide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Depletio + + + + + + regio + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Semicoductor ( type ------------------------------------------- Oxide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Depletio + + + + + + regio + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Semicoductor ( type At equilibrium, there is a depletio regio ito the semicoductor, but sice the metal has a OT of carriers per uit volume, it has little or o depletio depth ito it, ad ay charge o it is at its surface Uder a reverse bias, there is t much differece betwee a PN diode ad a MOS stack, the isulator just blocks the miority carriers, so there is zero curret istead of very little curret
Forward Bias Accumulatio ------------------------------------------- Oxide Depletio regio + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Oxide +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -------------------------------------------------------------------------------------------- Semicoductor ( type Semicoductor ( type Uder a forward bias, the isulatig layer blocks diffusio, so the depletio layer arrows, but there is still o vertical curret. Uder a higher forward bias, the mobile carriers get pushed up agaist the barrier, ad start to pile up i a thi layer there, the accumulatio layer The bias where accumulatio starts is called flat bad Iversio Bad edge diagram: accumulatio ------------------------------------------- Oxide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Depletio regio + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Semicoductor ( type Isulator ots of electros N type semicoductor Uder a strog reverse bias, the potetial at the surface of the semicoductor, ext to the oxide, ca get high eough so that holes start to accumulate i a thi layer, the iversio layer
Bad edge diagram: Flat bad Bad edge diagram: forward bias Isulator N type semicoductor Isulator N type semicoductor Bad edge diagram: equilibrium Bad edge diagram: reverse bias Isulator N type semicoductor Isulator N type semicoductor 3
Bad edge diagram: iversio Bad edge diagram: more iversio Isulator N type semicoductor Isulator N type semicoductor holes lots of holes P type body NMOS If the semicoductor is p type, rather tha type: The depletio has a egative fixed charge A iversio layer is a accumulatio of electros The same thig happes with NMOS, but the wells are type, so oly whe a iversio layer with electros appears above threshold will curret start to flow 4
NMOS, below threshold NMOS, ear threshold N+ semicoductor N+ semicoductor Electros Isulator P type semicoductor Isulator P type semicoductor B S G D B S G D p+ + + x j p+ + + x j p-type substrate p-type substrate NMOS NMOS NMOS, above threshold ariable resistor N+ semicoductor Isulator Electros B p+ P type semicoductor S G + + p-type substrate D x j If the Source ad Drai voltages are about the same, the the iversio charge is about the same at differet positios alog the gate. The amout of charge uder the gate is that which was calculated for the MOS capacitor The curret from the source to the drai is give by the amout of charge, the mobility of the carriers, ad the compoet of the electric field from the source to the drai NMOS 5
Width ad egth Drift elocity ad Drai Curret The gate legth of a MOS FET is the distace from the of the source to the drai Notice that the width is ofte much wider tha the legth Sice the fields ad charge are uchaged at differet poits alog the width of the trasistor, the curret is proportioal to the width B S G D W og-chael assumptio: use mobility to fid v µ DS vy ( µ Ey ( µ ( / y Ad ow the curret is just charge per area, times velocity, times the width: DS DS ID WvQN Wµ Cox( T W DS I D Cox( T DS µ Iverted Parabolas, I is proportioal to the square of the drai-source voltage Square-aw Characteristics The Saturatio Regio TRIODE REGION Boudary: what is I D,SAT? Whe DS > T, there is t ay iversio charge at the drai accordig to our simplistic model SATURATION REGION Why do curves flatte out? 6
Square-aw Curret i Saturatio Curret stays at maximum (where DS T DS,SAT W DS I C ( µ D ox T DS W T I DS, sat Cox( T ( T µ W µ Cox IDS, sat ( T Measuremet: I D icreases slightly with icreasig DS model with liear fudge factor W µ C I ox DS, sat ( T ( +λ DS Depletio Regio Pichig the MOS Trasistors p+ NMOS > T S G + + T p-type Pich-Off Poit Whe DS > DS,sat, the chael is piched off at drai ed (hece the ame pich-off regio Drai mobile charge goes to zero (regio is depleted, the remaiig elecric field is dropped across this high-field depletio regio As the drai voltage is icreases further, the pich off poit moves back towards source Chael egth Modulatio: The effective chael legth is thus reduced higher I DS D DS liear MOSFET Model Chael (iversio charge: eglect reductio at drai elocity saturatio defies DS,SAT E sat costat -v sat / µ Drai curret: I WvQ W ( v [ C ( D, SAT N sat ox T E sat 4 /cm,. µm DS,SAT.! I v WC ( ( + λ D, SAT sat ox T DS ], Cutoff < < TN TP I D iear TN TP,, DS DS Saturatio < > Review TN TP I D W µ Cox [( ] TN, DS TN W I D Cox T TP, DS TP Note: if SB, eed to calculate T T DS DS ( ( µ + λ DS 7
NMOS PMOS i DS T Slope due to Chael legth modulatio Steps Slope due to Chael legth modulatio DS T Combiig terms: Small-Sigal Model Capacitaces We ow have three small sigal cotributios to the curret ito the drai termial for our FET, from chages i gs, bs, ad ds While adequate for some purposes, the model so far implies that the curret ito the gate is zero. This is a good approximatio for low frequecies, for high frequecies we eed to accout for the curret ecessary to charge up the gate to supply the field across the oxide. There are also stray capacitaces to the drai ad source cotacts. i g v + g v + v r ds m gs mb bs ds o Notice that the chage i the small sigal curret ito the drai from A small sigal chage i ds ca be modeled as a resistor. 8
MOSFET Capacitaces i Saturatio Gate-Source Capacitace C gs The gate-drai capacitace is oly the frige capacitace whe i saturatio, because it is piched off from the charge i the chael. Gate-source capacitace: There is frigig charge betwee the edge of the gate ad the source, but also to the chael Wedge-shaped charge i saturatio effective area is (/3W (see H&S 4.5.4 for details C (/3 WC + C gs Overlap capacitace alog source edge of gate C ov D WC ox ox ov (This is a uderestimate, frigig fields will make The overlap capacitace larger Gate-Drai Capacitace C gd Juctio Capacitaces There is o cotributio due to chage i iversio charge i chael, just overlap capacitace betwee drai ad source The source, gate, ad drai will also have capacitaces betwee them ad the well or substrate. Capacitaces to the drai ad source will be juctio capacitaces, ad sice SB ad DB SB + DS reverse biases are differet, the capacitaces will be differet 9
Seekig perfectio Juctio Capacitaces Remember that all of the capacitaces, resistaces ad trasimpedaces will chage as the operatig poit chages There is o such thig as a perfect small sigal model, use the simplest oe that is sufficiet. Sometimes a small sigal model is used well outside of where it is accurate, because it is the mai way we ca deal ituitively with these devices! Drai ad source diffusios have (differet juctio capacitaces sice SB ad DB SB + DS are t the same Complete model P-Chael MOSFET Square-aw PMOS Characteristics Measuremet of I Dp versus SD, with SG as a parameter:
Small-Sigal PMOS Model