CMPE12 - Notes chapter 2. Digital Logic. (Textbook Chapters and 2.1)"

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Transcription:

CMPE12 - Notes chapter 2 Digital Logic (Textbook Chapters 3.1-3.5 and 2.1)"

Truth table" The most basic representation of a logic function." Brute force representation listing the output for all possible input combinations." CMPE12 Fall 2011 J. Ferguson" 2-2"

Truth table example" Input" Output" A B" A or B" F F" F" F T" T" T F" T" T T" T" 2 #inputs F -> 0 T -> 1 Input" Output" A B" A+B" 0 0" 0" 0 1" 1" 1 0" 1" 1 1" 1" CMPE12 Fall 2011 J. Ferguson" 2-3"

More truth tables" Input" Output" Input" Output" A B" A and B" A B" A nand B" 0 0" 0" 0 0" 1" 0 1" 0" 0 1" 1" 1 0" 0" 1 0" 1" 1 1" 1" 1 1" 0" Input Outputs Input" Output" A B X Y A" not A" 0 " 1" 1" 0" CMPE12 Fall 2011 J. Ferguson" 2-4"

Basic logic gates" CMPE12 Fall 2011 J. Ferguson" 2-5"

Transistor: Building Block of Computers (and logic gates)" Microprocessors contain LOTS of transistors! Intel Montecito (2005): 1.72 billion" Intel Pentium 4 (2000): 48 million" IBM PowerPC 750FX (2002): 38 million" IBM/Apple PowerPC G5 (2003): 58 million" Intel 4004 (1971): 2500" CMPE12 Fall 2011 J. Ferguson" 2-6"

Mooreʼs Law" The number of active components per chip will double every 18 months " CMPE12 Fall 2011 J. Ferguson" 2-7"

New architectures grow even faster!" CMPE12 Fall 2011 J. Ferguson" 2-8"

Transistors = switches" Logically, each transistor is used as a switch" Combined to implement logic functions " AND, OR, NOT" Combined to build higher-level structures" Adder, multiplexer, decoder, register, " Combined to build processor" LC-3" CMPE12 Fall 2011 J. Ferguson" 2-9"

Metal-Oxide-Semiconductor (MOS) transistor" CMPE12 Fall 2011 J. Ferguson" 2-10"

Metal-Oxide-Semiconductor (MOS) transistor" CMPE12 Fall 2011 J. Ferguson" 2-11"

Transistor opens and closes path for electricity" CMPE12 Fall 2011 J. Ferguson" 2-12"

n-type MOS transistor" n-type MOS (nmos)! when Gate has positive voltage, short circuit between #1 and #2 (switch closed)" when Gate has zero voltage, open circuit between #1 and #2 (switch open)" Gate = 1 Terminal #2 must be connected to GND (0V). Gate = 0 CMPE12 Fall 2011 J. Ferguson" 2-13"

p-type MOS transistor" p-type is complementary to n-type" when Gate has positive voltage, open circuit between #1 and #2 (switch open)" when Gate has zero voltage, short circuit between #1 and #2 (switch closed)" Gate = 1 Terminal #1 must be connected to +2.9V in this example. Gate = 0 CMPE12 Fall 2011 J. Ferguson" 2-14"

Logic gates" Use switch behavior of MOS transistors to implement logical functions: AND, OR, NOT." Digital symbols:" recall that we assign a range of analog voltages to each digital (logic) symbol" assignment of voltage ranges depends on electrical properties of transistors being used" typical values for "1": +5V, +3.3V, +2.9V. +1.8V, +1.2V, 1 V" from now on we'll use 1 volt" CMPE12 Fall 2011 J. Ferguson" 2-15"

CMOS circuit" Complementary MOS" Uses both n-type and p-type MOS transistors" p-type" Attached to + voltage" Pulls output voltage UP when input is zero" n-type" Attached to GND" Pulls output voltage DOWN when input is one! CMPE12 Fall 2011 J. Ferguson" 2-16"

Inverter (NOT gate)" 1 volt 0 volts In Out In Out 0 V 1 V 0 1 1 V 0 V 1 0 Truth Table CMPE12 Fall 2011 J. Ferguson" 2-17"

CMOS vs. TTL inverter" CMOS (modern)! TTL (1960ʼs 80ʼs)! CMPE12 Fall 2011 J. Ferguson" 2-18"

NAND gate (NOT-AND)" Note: Parallel structure on top, serial on bottom. A" B" C" 0" 0" 1" 0" 1" 1" 1" 0" 1" 1" 1" 0" CMPE12 Fall 2011 J. Ferguson" 2-19"

AND gate (nand-not)" A" B" C" 0 0 0 0 1 0 1 0 0 1 1 1 Add an inverter to a NAND. (All Primitive Gates are inverting!) CMPE12 Fall 2011 J. Ferguson" 2-20"

Primitive AND gate - NO!" A B C A" B C 0 0 0 0 1 0 1 0 0 1 1 1 What is wrong with this picture? CMPE12 Fall 2011 J. Ferguson" 2-21"

NOR gate" Note: Serial structure on top, parallel on bottom. A B CMPE12 Fall 2011 J. Ferguson" 2-22" C 0 0 1 0 1 0 1 0 0 1 1 0

OR gate" A B C 0 0 0 0 1 1 1 0 1 1 1 1 Add an inverter to a NOR gate. CMPE12 Fall 2011 J. Ferguson" 2-23"

More than 2 inputs?" AND/OR can take any number of inputs." AND = 1 if all inputs are 1." OR = 1 if any input is 1." Similar for NAND/NOR" Can implement with multiple two-input gates, or with single CMOS circuit if NAND or NOR." CMPE12 Fall 2011 J. Ferguson" 2-24"

Sum of products" Standard way of synthesizing simple circuits. Ex:" A B Z 0 0 0 0 1 1 1 0 1 1 1 0 CMPE12 Fall 2011 J. Ferguson" 2-25"

Building functions from logic gates" Combinational Logic Circuit! output depends only on the current inputs" Stateless" (what we are talking about now)" Sequential Logic Circuit! output depends on the sequence of inputs (past and present)" stores information (state) from past inputs" (we will talk about this later)" CMPE12 Fall 2011 J. Ferguson" 2-26"

What is the most confusing subject so far?" A. Chapter 1" B. Truth Tables / Sum of Products" C. FETs to build CMOS gate" D. Everything is easy (yawn!)" E. Nothing makes sense." CMPE12 Fall 2011 J. Ferguson" 2-27"

Multiplexer" 2-way multiplexer: the output is equal to one of the two inputs, based on a selector" S A B Z 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 What is the formula for the MUX? Z =? Z = SʼABʼ + SʼAB + SAʼB + SAB! Z = SʼA + SB! CMPE12 Fall 2011 J. Ferguson" 2-28"

About the little circle" For both inputs and outputs" The little circle represents an inverter." " " "-or-" The little circle changes the meaning of what a logic 1 (0) is." CMPE12 Fall 2011 J. Ferguson" 2-29"

4-way multiplexer" n-bit selector and 2 n inputs, one output" output equals one of the inputs, depending on S inputs" 0 1 2 3 4-to-1 MUX CMPE12 Fall 2011 J. Ferguson" 2-30"

More about FETs (Field Effect Transistors)" SoP formula for MUX: sa +s B = 12 transistors if Nand/Nand Need only 2 transistors with pass-transistor logic, but must have immediate restoring gate. CMPE12 Fall 2011 J. Ferguson" 2-31"

n inputs, 2 n outputs" Decoder" exactly one output is 1 for each possible input pattern" 2-to-4 decoder CMPE12 Fall 2011 J. Ferguson" 2-32"

Student T-shirt" There are 10 kinds of people: those that understand binary, and those that don t. CMPE12 Fall 2011 J. Ferguson" 2-33"

How to represent numbers: Unary, or marks:" Number Systems" " "/////// = 7" " "/////// + ////// = /////////////" Grouping lead to Roman Numerals:" " "VII + V = VVII = XII" Better: Arabic Numerals:" " "7 + 5 = 12 = 1 x 10 + 2" CMPE12 Fall 2011 J. Ferguson" 2-34"

Positional Number System" The value represented by a digit depends on its position in the number." Ex: 1832 = 1*10 3 + 8*10 2 + 3*10 1 + 2*10 0 " CMPE12 Fall 2011 J. Ferguson" 2-35"

Positional Number System" Select a number as the base, b, ex:" Define an alphabet of b-1 symbols plus a symbol for zero to represent all numbers " Use an ordered sequence of digits to represent numbers " The represented number is the sum of all digits, each multiplied by b to the power of the digitʼs position p! Positional number systems are great for arithmetic" 1832 = 1*10 3 + 8*10 2 + 3*10 1 + 2*10 0 " CMPE12 Fall 2011 J. Ferguson" 2-36"

Base two numbers" 101 b is 1*b 2 + 0*b 1 + 1*b 0" 101 10 is 1*10 2 + 0*10 1 + 1*10 0" 101 2 is 1*2 2 + 0*2 1 + 1*2 0 =?" 10 2 is 1*2 1 + 0*2 0 =?" CMPE12 Fall 2011 J. Ferguson" 2-37"

Binary addition" 0 + 0 = 0" 0 + 1 = 1" 1 + 0 = 1" 1 + 1 = 0 with a carry of 1*2 1 " CMPE12 Fall 2011 J. Ferguson" 2-38"

Half Adder" Add two bits, produce one-bit sum and carry-out." A" B" S (C)" C out (D)" 0" 0" 0" 0" 0" 1" 1" 0" 1" 0" 1" 0" 1" 1" 0" 1" CMPE12 Fall 2011 J. Ferguson" 2-39"

Full Adder" Add two bits and carry-in, produce one-bit sum and carry-out." A" B" C in" S" C out" 0" 0" 0" 0" 0" 0" 0" 1" 1" 0" 0" 1" 0" 1" 0" 0" 1" 1" 0" 1" 1" 0" 0" 1" 0" 1" 0" 1" 0" 1" 1" 1" 0" 0" 1" 1" 1" 1" 1" 1" CMPE12 Fall 2011 J. Ferguson" 2-40"

Four-bit Adder" A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 C out S 3 S 2 S 1 S 0 CMPE12 Fall 2011 J. Ferguson" 2-41"

Logical completeness" Can implement ANY truth table with AND, OR, NOT." A" B" C" D" 0! 0! 0! 0! 0! 0! 1! 0! 0! 1! 0! 1! 0! 1! 1! 0! 1! 0! 0! 0! 1! 0! 1! 1! 1! 1! 0! 0! 1! 1! 1! 0! 1. AND combinations that yield a "1" in the truth table." 2. OR the results of the AND gates." CMPE12 Fall 2011 J. Ferguson" 2-42"

Formalisms in Boolean Algebra" Warning! Math ahead. CMPE12 Fall 2011 J. Ferguson" 2-43"

Axioms of Boolean algebra" a. 0 * 0 = 0" b. 1 + 1 = 1 " c. 1 * 1 = 1" d. 0 + 0 = 0" e. 0 * 1 = 1 * 0 = 0" f. 1 + 0 = 0 + 1 = 1" g. if x = 0 then xʼ = 1" h. if x = 1 then xʼ = 0" CMPE12 Fall 2011 J. Ferguson" 2-44"

Single-variable theorems" x * 0 =" x + 1 = " x * 1 =" x + 0 =" x * x =" x + x =" x * xʼ =" x + xʼ = " (xʼ)ʼ = " CMPE12 Fall 2011 J. Ferguson" 2-45"

Commutative: " x * y = y * x" x + y = y + x" Associative" x * (y * z) = (x * y) * z" x + (y + z) = (x + y) + z" Distributive" Properties "" x * (y + z ) = (x * y) + (x * z) = (x * y) + (x * z)" x + (y * z) = (x + y) * (x + z)" CMPE12 Fall 2011 J. Ferguson" 2-46"

More properties" Absorption:" x + x y = x" x(x + y) = x" Combining" x y + x yʼ = x" (x + y) (x + yʼ) = x" De Morganʼs" (x y)ʼ = xʼ + yʼ" (x + y)ʼ = xʼ yʼ" Other: x + (x y) = x + y x (x + y) = x y CMPE12 Fall 2011 J. Ferguson" 2-47"

Example:" Logic minimization" A B C Y 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 0 Y = AʼBCʼ+AʼBC+ABʼCʼ+ABCʼ! = AʼB + ACʼ! combining! CMPE12 Fall 2011 J. Ferguson" 2-48"

DeMorgan's Law" (A + B)ʼ = AʼBʼ conversely (AB)ʼ = Aʼ + Bʼ! A B AB (AB) A B A +B 0 0 0 1 1 1 1 0 1 0 1 1 0 1 1 0 1 1 CMPE12 Fall 2011 J. Ferguson" 2-49"

DeMorganʼs Law and logic gates" (A + B)ʼ = AʼBʼ! A+B = (AʼBʼ)ʼ! (JK + LM)ʼ = (JK)ʼ (LM)ʼ! JK + LM = ( (JK)ʼ (LM)ʼ )ʼ J K L M J K L M Same Function! CMPE12 Fall 2011 J. Ferguson" 2-50"

DeMorganʼs Law: And-Or Nand-Nand" J K J K L M L M SoP And/Or Nand/Nand" CMPE12 Fall 2011 J. Ferguson" 2-51"

DeMorganʼs Law: Or-And Nor-Nor" J K J K L M L M CMPE12 Fall 2011 J. Ferguson" 2-52"

Homework and Recommended exercises on combinational circuits (ignore for this class) Finish reading thru Chapter 3.5 and 2.1" Ex 3.5, 3.6, 3.7, 3.8, 3.9" Ex 3.11, 3.18" Ex 3.20 gate level circuit only, 3.22 ignore truth table, 3.23, 3.24a" Ex 3.30a,b; Ex 3.44" CMPE12 Fall 2011 J. Ferguson" 2-53"

Combinational vs. Sequential" Combinational circuit" always gives the same output for a given set of inputs" ex: adder always generates sum and carry, regardless of previous inputs" CMPE12 Fall 2011 J. Ferguson" 2-54"

Sequential circuit" stores information" output depends on stored information (state) plus input" so a given input might produce different outputs, depending on the stored information" example: ticket counter" advances when you push the button" output depends on previous state" useful for building memory elements and state machines " CMPE12 Fall 2011 J. Ferguson" 2-55"

Building Memory Units: Latches Flip-Flops Registers Memories, etc. CMPE12 Fall 2011 J. Ferguson" 2-56"

Set-Reset Latch" Two inputs: Set and Reset" Start with both inputs at 1 (memory)" Set to 0 one of the two inputs at a time to store a value" The transition 00 -> 11 generates an undefined output" NAND" A" B" C" 0" 0" 1" 0" 1" 1" 1" 0" 1" 1" 1" 0" CMPE12 Fall 2011 J. Ferguson" 2-57"

Gated SR-Latch = D-Latch" Two inputs: D (data) and WE (write enable)" when WE = 0, latch holds previous/current value" Sʼ = Rʼ = 1" when WE = 1, latch is set to value of D" S = NOT(D), R = D" CMPE12 Fall 2011 J. Ferguson" 2-58"

WE D Q 1 0 1 0 1 0 time time time CMPE12 Fall 2011 J. Ferguson" 2-59"

D-Latch: Timing" It is possible to change the state only when the WE line is active. Sometimes called level-sensitive latch. D WE D Q E Q WE 1 0 time D 1 0 time Q 1 0 time CMPE12 Fall 2011 J. Ferguson" 2-60"

Register" A register stores a multi-bit value." We use a collection of D-latches, all controlled by a common WE." When WE=1, n-bit value D is written to register." CMPE12 Fall 2011 J. Ferguson" 2-61"

Memory" Now that we know how to store bits, we can build a memory a logical k m array of stored bits." Address Space: number of locations (usually a power of 2) Addressability: number of bits per location (e.g., byte-addressable) k = 2 n locations m bits CMPE12 Fall 2011 J. Ferguson" 2-62"

State Machines" CMPE12 Fall 2011 J. Ferguson" 2-63"

State Machine" The basic type of sequential circuit" Combines combinational logic with storage" Remembers state, and changes output (and state) based on inputs and current state" State Machine Inputs Combinational Logic Circuit Outputs Storage Elements CMPE12 Fall 2011 J. Ferguson" 2-64"

Combinational vs. Sequential" Two types of combination locks" 4 1 8 4 25 20 30 15 5 10 Combinational Success depends only on the values, not the order in which they are set. Sequential Success depends on the sequence of values (e.g, R-13, L-22, R-3). CMPE12 Fall 2011 J. Ferguson" 2-65"

Two D-latches = One D Flip-Flop" Use a clock signal and connect it to the WE latch input. " Connect one latch to the inverted clock" CMPE12 Fall 2011 J. Ferguson" 2-66"

D-Flip Flop: Timing diagram" Ck 1 0 time D WE Ck D Q E Q WE 1 0 time D 1 0 time Q 1 0 time Edge-triggered flip-flop CMPE12 Fall 2011 J. Ferguson" 2-67"

Probable Recommended exercises What can you tell me about the values of A and B if S and R are both 1for Figure 3.18 in your text?" When are S and R both 1 in Figure 3.19 and what function is the circuit providing with this input?" Next: read chapter 4 CMPE12 Fall 2011 J. Ferguson" 2-68"

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