TECHNICAL DATA Stepping Motor Driver IC IK6502 Generl Description IK6502 is stepping motor driver ICs with MOS output trnsistors. The ICs cn control two-phse stepping motor forwrd nd reverse by bipolr driving. They hve power-sving circuit nd stndby circuit. Ordering Informtion Fetures IK6502N DIP-16 They re similr substituting products of TB6674. Both products hve sme pckges nd sme pin ssignments. One-chip two-phse bipolr stepping motor driver (including two bridge drivers) Power sving opertion is vilble Stndby opertion is vilble Current consumption 20 μa (typ.) Built-in punch-through current restriction circuit for system relibility nd noise suppression TTL-comptible inputs INA, INB, PS, nd V S2B terminls ON resistnce PS = L: 3.0 Ω (Typ.) PS = H: 8.5 Ω (Typ.) High driving bility : I O (START) 350 ma (MAX.): V S1 ENABLE : I O (HOLD) 100 ma (MAX.): V S2 ENABLE Typicl PKG DIP16 GND terminl = HEAT SINK Over current shutdown circuit (ISD) Therml shutdown circuit (TSD) Under voltge lockout circuit (UVLO) Pull-down resistnce for input terminl (250 kω)
Block Digrm Pin Description Pin No. Symbol 1 V S2A Low-voltge power supply terminl 2 V CC Power voltge supply terminl for control 3 IN A A-ch forwrd rottion / reverse rottion signl terminl, Truth Tble 1 4 GND GND terminl 5 GND GND terminl 6 IN B B-ch forwrd rottion / reverse rottion signl terminl, Truth Tble 1 7 PS Power sving signl input terminl 8 V S2B Stndby signl input terminl, Truth Tble 2 9 V S1B High-voltge power supply terminl 10 φb Output B 11 ΦB Output B 12 GND GND terminl 13 GND GND terminl 14 ΦA Output A 15 φa Output A 16 V S1 A High-voltge power supply terminl
Truth Tble 1 Input Output PS IN φ Φ L L L H ENABLE V S1 L H H L ENABLE V S1 H L L H ENABLE V S2 (Power sving) H H H L ENABLE V S2 (Power sving) Truth Tble 2 V S2B L H Mode POWER OFF (Stndby mode) OPERATION Note: Apply 5V to V S2A s supply terminl. Terminl circuit Input terminl (INA, INB, PS, nd V S2B ) The digrm is prtly-provided nd omitted or simplified for explntory purposes.
Absolute Mximum Rtings (T = 25 C) Chrcteristic Symbol Rting Unit Supply voltge V CC 6.0 V S1 24.0 V Output current IK6502N V S2 Up to V CC I O (PEAK) ±400 I O (START) ±350 I O (HOLD) ±100 Input voltge V IN Up to V CC V Power dissiption 1.4 (Note 1) IK6502N P D 2.7 (Note 2) Operting temperture Topr -30 to 75 C Storge temperture Tstg -55 to 150 C ma W Note 1: IC only Note 2: This vlue is obtined if mounting is on 50 mm 50 mm 0.8 mm PCB, 60 % or more of which is occupied by copper. Operting Conditions (T = 25 C) Chrcteristic Symbol Min. Typ. Mx. Unit Supply voltge Output current VCC 4.5-5.5 V S1 8.0-22.0 V S2A 2.7-5.5 IK6502N I O - - ±350 ma Input voltge V IN 0 - V CC V Mximum frequency of input pulse Minimum resolution of input pulse f IN - - 25 khz tw 20 - - μs V Vlue of ON resistnce tends to increse when the difference between V S1 nd V S2A becomes 5 V or less.
Electricl Chrcteristics Unless otherwise specified, T = 25 C, V CC = 5 V, V S1 = 12 V, nd V S2A = 5 V Chrcteristic Symbol Test Circuit Test Condition Min Typ. Mx Unit Supply current I CC1 I CC2 1 PS: H, V S2B : H PS: L, V S2B : H 3 5 3 5 ma I CC3 V S2B : L 1 20 μa Input voltge High V IN H 2.0 Vcc V Low V IN L INA, INB, PS, V S2B -0.2 0.8 Input hysteresis voltge* Input current V IN hys 1 90 mv INA, INB, PS, V I S2B V IN = 5.0 V IN (H) 5 20 38 μa Built in pull-down resistnce 1 I IN (L) V IN = 0 V 1 μa Output ON resistnce (Note) IK6502N Ron 1H 2 PS: L, V S2B : H I OUT =400mA 3 5 Ron 2H 3 PS: H, V S2B : H I OUT =100mA 8.5 16 Ron L 2 V S2B : H I OUT =400mA 0.9 3.5 Ω Diode forwrd voltge V F U 1.2 2.5 4 I F = 350 ma, PS = L V F L 1.0 2.2 V Dely time tp LH 0.5 IN φ tp HL 0.5 μs Therml shutdown circuit* TSD (Design trget only) 160 C TSD hysteresis * TSDhys (Design trget only) 20 C * : IK Semicon does not implement testing before shipping.
Under voltge Lockout Circuit (UVLO) The IK6502 incorportes n under voltge lockout circuit. Outputs re turned off (Hi-Z) under the conditions s follows; V CC 4.0 V (Design trget) or V S1A 6.0 V (Design trget) nd V S1B 6.0 V (Design trget) or V S2A 2.2 V (Design trget) The UVLO circuit hs hysteresis nd the function recovers under the conditions s follows; V CC = 4.1 V (Design trget), V S1A/ VS1B = 6.5 V (Design trget), V S2A = 2.3 V (Design trget) UVLO opertion
UVLO opertion UVLO opertion
Over Current Protection (ISD) Circuit The IC incorportes the over current protection circuit tht monitors the current flowing through ech output power trnsistor. If current, which is out of the detecting current, is sensed t ny one of these trnsistors, ll output trnsistors re turned off (Hi-Z). (However, ISD is not incorported in upper PchDMOS when PS is high level (V S2A is 5V usge) becuse ON resistnce is lrge. Msking time is 20 μs. The opertion does not recover utomticlly (ltch method). There re two recovery methods written below. (1) Power monitor turns on when ny of the power supply decreses nd reches the specified voltge. (2) V S2B is set low level for 20 μs or more nd then set high. The opertion recovers in 10 μs. Reference design trget of detecting current is s follows; PS = L, V S1A (12 V) : PchDMOS = 0.8 A PS = H/PS = L in common : Lower NchDMOS = 1.1 A Plese reduce the externl noise to prevent mlfunction for ISD. ISD opertion
Therml Shutdown Circuit (TSD) The IK6502 incorportes therml shutdown circuit. If the junction temperture (Tj) exceeds 160 C (design trget only), ll the outputs re tuned off (Hi-Z). It recovers utomticlly t 140ºC. It hs hysteresis width of 20ºC. TSD = 160 C (design trget only) TSD opertion
Test Circuit 1. I CC1, I CC2, I CC3, I IN A, I IN B, nd I PS Item SW 1 SW 2 SW 3 SW 4 I CC1 b b I CC2 b b b I CC3 b b b I IN A I IN B I PS All terminls of INA, INB, nd PS should output low or be connected to the ground terminl in mesuring I CC3.
Test Circuit 2. Ron 1H1, Ron 1H2, Ron L2, nd Ron L3 *: Adjust R L to correspond to I L. Item SW 1 SW 2 SW 3 SW 4 SW 5 I L (ma) V SAT 1H1 V SAT 1H2 V SAT L2 V SAT L3 b b b d b c b b b d b c b b d b c b b b d b c 100 400 b 100 b 400
Test Circuit 3. Ron 2H1, Ron 2H2, nd Ron L1 *: Adjust R L to correspond to I L. Item SW 1 SW 2 SW 3 SW 4 SW 5 I L (ma) V SAT 2H1 V SAT 2H2 V SAT L1 b b d b c b b d b c b b c b d 20 100 b 20
Test Circuit 4. V FU, nd V FL Mesuring Method Item SW 1 SW 2 V FU V FL b c d e e b c d
Timing Chrt (two-phse excittion) Therml Performnce Chrcteristics IK6502N (DIP-16)
Appliction Circuit Note 1: Connect the V S2A terminl to the lower supply voltge (5 V). Note 2: Supply smoothing cpcitor* should be connected between ech supply terminl (Vcc, V S2A, nd V S1A/B ) nd GND terminl. *: (Ex.): Cpcitors of tens of μf nd 0.1 μf which re connected in prllel. Note 3: Utmost cre is necessry in the design of the output, Vcc, V M, nd GND lines since the IC my be destroyed by short-circuiting between outputs, ir contmintion fults, or fults due to improper grounding, or by short-circuiting between contiguous terminls. Note 4: By our short-circuited exmintion of neighboring terminls, when 9 nd 10 terminls or 15 nd 16 terminls re short-circuited, in ny cse might to be destroyed nd cuse the trouble of smoking etc. Plese use n pproprite fuse to the power supply line. Note 5: Connect V S1A terminl nd V S1B terminl externlly. Note 6: Connect ech GND terminl externlly.
Pckge Dimensions