Chapter 13 Clocked Circuits SEQUENTIAL VS. COMBINATIONAL CMOS TG LATCHES, FLIP FLOPS SET-RESET (SR) ARBITER LATCHES FLIP FLOPS EDGE TRIGGERED DFF FF TIMING Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 1
o Baker Ch. 13 Clocked Circuits CLK D Q In SEQUENTIAL CIRCUITS DESCRIPTION VTC V o1 Combinational Logic Circuit Combinational V i1 t su V o1 = V i 2 V o2 = V i 1 DATA STABLE V i2 = V o1 Out V "Adapted from Digital Integrated Circuits, A Design Perspective, i1 = V o2 Rabaey, Chandrakasan, and Nikolic, Copyright 2003 Prentice Hall/Pearson." V o2 t hold t c 2 q V i1 A V i2 In DATA STABLE C t t t B Combinational Logic Circuit State Sequential Register D V o2 Q CLK Out COMBINATIONAL INPUTS DETERMINE OUTPUT SEQUENTIAL FEEDBACK FROM OUTPUT EXAMPLES OF SEQUENTIAL CKTS REGISTERS COUNTERS OSCILLATORS MEMORIES GENERIC TERMINOLOGY SETUP TIME DATA VALID BEFORE CLOCK CHG HOLD TIME DATA VALID AFTER CLOCK CHG LATCH OUT=IN, OR OUT=STABLE LEVEL-SENSITIVE REGISTER OUT=IN WHEN CLOCK TRANSITIONS EDGE-SENSITIVE BISTABLE TWO VALID STATES Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 2
CMOS TG DESCRIPTION NEED BOTH N & P TO PASS DATA WHAT IS THE BENEFIT? WHAT IS THE DRAWBACK? APPLICATION 4 TO 1 MUX 2 M = N M NUMBER OF CONTROL LINES N NUMBER OF INPUTS CHOOSES 1 OF 4 INPUTS M=2, N=4 WHERE IS THIS USED? S1 S2 Z S1=AB VS CD 0 0 D S2=A VS B, C VS D 0 1 C 1 0 B 1 1 A Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 3
CMOS TG VS PG VS NOR DESCRIPTION Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 4
SEQUENTIAL CIRCUITS STATIC* LATCHES LEVEL SENSITIVE DELAY DUE TO CONTENTION AFFECTS SENSE AMPS WEAKEN ONE INVERTER 1 0 1 SR (SET-RESET) LATCH NAND, NOR BASED S-HIGH, R-LOW, RESETS OUTPUT R-HIGH, S-LOW, SETS OUTPUT BAR BASIC BLOCK FOR DFF, MEMORY 0 1 0 1 0 1 0 0 1 0 ARBITER LATCH USED IN ASYNCHRONOUS DESIGNS, CLOCK SYNCHRONIZATION ONLY ONE OUTPUT HIGH OUTPUT DEPENDS ON WHICH INPUT IS FIRST TO GO HIGH OUT2 NO VDD WHEN IN1=1 *NOT USING PARASITIC CAP IN CKT Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 5
LATCHES DESCRIPTION LEVEL SENSITIVE LATCH CLOCK HIGH, D INPUT Q OUT WHERE IS THE DELAY? WHY DOES I2 HAVE LONG L? Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 6
SEQUENTIAL CIRCUITS STATIC* REGISTER MASTER-SLAVE REGISTER (DFF) DESCRIPTION EDGE TRIGGERED, E.G., REGISTER USES TG TO CLOCK MASTER, SLAVE OPERATION TWO LEVEL SENSITIVES LATCHES CLOCK=L, B TRACKS D, Q HELD CLOCK=H, B GOES TO SLAVE TIMING CLOCK RISE TIME MUST BE SMALL BUFFERS IN SERIES WITH CLK POOR QA EXAMPLE CLK L H Q FOLLOWS D *NOT USING PARASITIC CAP IN CKT Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 7
FLIP FLOPS DESCRIPTION TG RESISTANCE IS Rp Rn NODE A CAP: CA = (1) C OXN /2 + C OXP /2 + (2) 3/2 (C OXN + C OXP ) #1 IS NODE A CAP DUE TO TG #2 IS INPUT CAP OF I1 WHAT IS MISSING? NODE B CAP: CB = (1) 3/2 (C OXN + C OXP ) (2) C OXN /2 + C OXP /2 + #1 IS INPUT CAP OF I2 #2 IS OUT CAP OF I1 WHAT IS MISSING? HAND CALCULATION VS SIM 4.5ps VS. 30ps 13.5ps VS. 90ps MUST SIMULATE Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 8
TIMING OF FLIP FLOPS DESCRIPTION Need to simulate various t s / t h Delay Degradation Percent 10% 0% Failure of D Q T (setup/hold) When t s / t h is marginal, delay changes Ex. D input is rising as clock is changing Node B is set to a 0 Node B starts to see a 1 state Clock changes Slave sees a partial 1 Q inverter takes longer to change D ts CLK 5 1 Q td 1 5 Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 9
Kaeslin, Top-Down Digital VLSI Design, Chpt. 8, Figure 8.13 Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 10