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ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Transfer Gate and Dynamic Logic Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Email: Lynn.Fuller@rit.edu Department webpage: http://www.microe.rit.edu 11-12-2015 DynamicLogic.ppt Page 1

ADOBE PRESENTER This PowerPoint module has been published using Adobe Presenter. Please click on the Notes tab in the left panel to read the instructors comments for each slide. Manually advance the slide by clicking on the play arrow or pressing the page down key. Page 2

OUTLINE Introduction Basic Concepts CMOS Transmission Gate Logic Dynamic D-Latches and D Flip-Flops Domino Logic References Homework Page 3

INTRODUCTION This document describes dynamic logic techniques. Dynamic logic means that the logic levels (high or low) is stored on capacitors. Each logic gate has its own self capacitance that can be used to store this high or low value. These stored values can discharge over time unless they are refreshed periodically. Important concepts of charge leakage, capacitive feed through and charge sharing will be introduced. Page 4

PASS TRANSISTOR A pass transistor is suppose to allow an input signal to pass to an output node unaltered when the transistor is on and when the transistor is off (high z state) the output signal is held at the previous value. S VDD I D VO=VDD 0 V D I S VO=VT VIN High Z C PMOS C PMOS VDD C D VDD I S VO=VDD-VT I S D 0 v VO=0 VIN High Z VDD C NMOS +V C NMOS 0 V C Page 5

PASS TRANSISTOR A pass transistor is suppose to allow an input signal to pass to an output node unaltered when the transistor is on and when the transistor is off (high z state) the output signal is held at the previous value. VDD D I S D I S D I S VO=VDD-VT +V +V NMOS +V C D Vin=VDD VDD D S +VDD-VT I VDD D S S +VDD-2VT C VO = VDD-3VT +V NMOS Page 6

ANALOG SWITCHES TRANSMISSION GATE I PMOS Vt= -1 S zero D C V1 V2 V1 V2 D NMOS Vt=+1 +5 S C Transmission Gate For current flowing to the right (ie V1>V2) the PMOS transistor will be on if V1 is greater than the threshold voltage, the NMOS transistor will be on if V2 is <4 volts. If we are charging up a capacitor load at node 2, to 5 volts, initially current will flow through NMOS and PMOS but once V2 gets above 4 volts the NMOS will be off. If we are trying to charge up V2 to V1 = +1 volt the PMOS will never be on. A complementary situation occurs for current flow to the left. Single transistor switches can be used if we are sure the Vgs will be more than the threshold voltage for the specific circuit application. (or use larger voltages on the gates) Page 7

ANALOG SWITCH ENABLE FALSE Page 8

ANALOG SWITCHES ENABLE TRUE Page 9

ANALOG SWITCHES CURRENT IN M3 AND M4 I in M4 I in M3 Page 10

CALCULATION OF TIME HIGH Z HOLDS CHARGE Lets assume: VDD=5V, RITSUBN7 SPICE model, L=2um, W=40um, Area of Drain or Source is 40umx20um, Capacitance on the output node is ~50fF, and JS=3.23E-9 A/cm2 Calculate the time it takes for the output high to drop to ½ VDD if the charge is lost by reverse leakage in the output Drain/Source junction. (ie Capacitive load only) Q=CV I = Q/t = CV/t I=JS Area = CV/t t = (CV)/(JS Area) t = (50E-15x2.5)/(3.23E-9 x (40E-4 x 20E-4)) = 4.84 seconds Page 11

SPICE LEVEL-1 MOSFET MODEL G S 2.3fF CGSO COX 9.2fF CGDO 2.3fF D p+ p+ RS ID RD CBS 24.3fF 0.21fF 24.3fF CBD CGBO B The capacitors in this model are a function of the voltages on the D, G, S and B terminals. CGDO is across a voltage gain in many circuits so that capacitor will appear to be larger do to Miller effect. CG Rochester = Institute C Gin of + Technology C G-S + C G-D (1-Av) = 9.2fF + 2.3fF + 2.3fF x (1- -5) = ~25.3fF Page 12

SPICE MODELS FOR MOSFETS * From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology.MODEL RITSUBN7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8 +VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology.MODEL RITSUBP7 PMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=2.26E-7 NCH=7.12E16 NSUB=3.16E16 XT=8.66E-8 +VTH0=-1.0 U0= 376.72 WINT=2.0E-7 LINT=2.26E-7 +NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) Page 13

(+V to -V) ANALOG SWITCH WITH (0 to 5 V) CONTROL S D Vout Vin D S Analog Switch +V 0-5V Logic Control Inverter +5 m1 m2 -V m3 m4 Positive Feedback Amplifier 0-5 volt level shifter to V and +V Page 14

(+V to -V) ANALOG SWITCH WITH (0 to 5 V) CONTROL If the Control goes high m1 starts to turn off and m3 starts to turn on. The output of m3..m4 starts to move higher turning m2 on which makes the output of m1..m2 go lower which turns m4 off making the output of m3..m4 to go even higher. This positive feedback makes the outputs go all the way to +V and V rails with only a 0V or 5V control signal. The voltages on the gates of the analog switch transistors will be +V or V which is what is needed to make Vout go to all the way to +V or V rails. Page 15

(+V to -V) ANALOG SWITCH WITH (0 to 5 V) CONTROL Page 16

3 BIT ANALOG MULTIPLEXER V8 V7 V6 V5 V4 V3 V2 V1 b1 b1 b2 b2 b3 b3 LSB MSB Vout Each Switch is an Analog Switch as discussed above MSB 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 LSB b3 b2 b1 Vout V1 V2 V3 V4 V5 V6 V7 V8 Page 17

DIGITAL TO ANALOG CONVERSION A digital word of n bits is converted to an analog voltage. If n = 3 then 2 n or 8 different analog values are possible. If n=10 then 1024 different analog values are possible. b1 bn D to A Analog Vout For example if the reference voltage is 3 volts and n = 3 and the digital word is 101 then the Analog Vout = 3V x 5/8 = 1.875V 101=5 2 n =8 Page 18

3 BIT DIGITAL TO ANALOG CONVERTER (DAC) Vref b1 b1 b2 b3 b3 b2 Vref 7/8 Vref 6/8 Vref 5/8 Vref 4/8 Vref 3/8 Vref 2/8 Vref 1/8 LSB MSB Vout Resistors are all equal value Page 19

128 PHOTODIODES Dynamic Logic ANALOG MULTIPLEXER APPLICATION ANALOG MULTIPLEXER D1 D2 D3 D4 D5 D6 D7 D8 SWITCHES A A B B C C Analog out A.G 7 BIT COUNTER Sync Sync pulse (at 0000000B) Clock Reset Page 20

CMOS TRANSMISSION GATE LOGIC XOR gate requires only 8 transistors (including inverters) while static gate solution requires 16 transistors. A B A OUT = AB + AB B Page 21

CMOS TRANSMISSION GATE MULTIPLEXER S0 S1 SA SB SC SD A A B OUT B C OUT D Two Level BCD Select 16 Transistors C D Single Level Decoded Select 16 Transistors Page 22

CMOS TRANSMISSION OR & AND GATE A A VDD OUT VDD OUT B B AND-2 Gate OR-2 Gate Page 23

CMOS TRANSMISSION GATE DATA LATCH Clocked DATA Latch DATA CLK D Q Q Q OUT CLK CLK CLK Only 8 transistors for a clocked data latch, compared to CMOS with 14 transistors. Page 24

CMOS DYNAMIC DATA LATCH DATA Latch VDD DATA CLK M1 M2 D Q Q X OUT CLK M4 M3 When the clock goes low the data stored at node X is refreshed. When the clock goes high the data (D) is stored as charge on node X. Page 25

CMOS DYNAMIC DATA LATCH VDD CLK M1 CLK DATA M2 Q Q DATA CLK M4 M3 Q Sketch Q Page 26

CMOS DOMINO LOGIC EVOLUTION +V +V +V +V precharge VA VO VO VA VO VA VO VB VA VB VB VB CMOS evaluate CLK Pseudo CMOS YEARS Dynamic Domino Page 27

CMOS DOMINO LOGIC DOMINO Logic +V CLK VA VB VC NMOS complex VOUT Domino Logic gates require a clock. High output is easy to obtain since the upper transistor will be on when the clock is off. If the output is suppose to be low it is only low during the clock pulse when the lower transistor is on (dynamic logic). Page 28

CMOS DOMINO LOGIC When the clock is low Vout is precharged high. When the clock is high Vout is valid. Page 29

STATIC CMOS NOR-2 When the clock is low Vout is precharged high. When the clock is high Vout is valid. Page 30

CMOS 3-NOR - DOMINO LOGIC +V +V VC VA VB VC VOUT VA VB VOUT CLK STATIC NOR Dynamic NOR Page 31

CMOS 3-NAND - DOMINO LOGIC +V +V VA VOUT VA VOUT VB VB VC VC STATIC NAND CLK Dynamic NAND Page 32

OTHER GATES - DOMINO LOGIC +V VA VOUT = A (B+C) VB VC CLK The NMOS complex can have other functions. Page 33

CASCADED DOMINO GATES CLK +V +V +V Y1 F1 Y2 F2 Y3 F3 NMOS complex NMOS complex NMOS complex The dynamic NMOS logic gates cannot be connected directly to another dynamic logic gate because all the outputs are precharged high thus no inputs will be low. (See next page) Page 34

CMOS DOMINO LOGIC All outputs are precharged high when the clock is low, meaning all inputs to subsequent gates are high when the clock is off. If the output is suppose to be low it will not be. By placing a static inverter between two domino logic gates an input can be low even during the precharge phase. Of course this inverts the output but we can account for that in the logic design. The combination of the dynamic stage and the inverter is called a domino stage. A cascade of three domino stages would result in quick precharge for all three stages. When the clock goes high during the evaluation stage the outputs of the NMOS complex will fall low from left to right like dominos (if the logic calls for lows). The clock must remain high long enough for this domino effect to propagate through the circuit. The clock is typically asymmetric with the high output longer than the low output. The timing will be fastest with stronger pull down path in the dynamic block and stronger pull up path in the inverter. These types of circuits are typically faster than their static logic equivalent. Applications include fast readout CCD s. Page 35

REFERNCES 1. Hodges Jackson and Saleh, Analysis and Design of Digital Integrated Circuits, Chapter 4. 2. Sedra and Smith, Microelectronic Circuits, Sixth Edition, Chapter 13. 3. Dr. Fuller s Lecture Notes, http://people.rit.edu/lffeee Page 36

HOMEWORK DYNAMIC LOGIC 1. Use SPICE to simulate the transmission gate OR gate. Set up the input pulses for A and B to provide all of the four different input combinations. Show both inputs and the output on separate plot planes. 2. Do a SPICE simulation for a transmission gate data latch. 3. Do SPICE for the circuit on page 31. Dynamic logic gate to give this function VOUT = A (B+C) Page 37

SPICE MODELS FOR CD4007 MOSFETS *SPICE MODELS FOR RIT DEVICES - DR. LYNN FULLER 8-7-2015 *LOCATION DR.FULLER'S WEBPAGE - http://people.rit.edu/lffeee/cmos.htm * *Used in Electronics II for CD4007 inverter chip *Note: Properties L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.1 NRS=0.1.MODEL RIT4007N7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=4E-8 XJ=2.9E-7 NCH=4E15 NSUB=5.33E15 XT=8.66E-8 +VTH0=1.4 U0= 1300 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=300 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-8 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *Used in Electronics II for CD4007 inverter chip *Note: Properties L=10u W=360u Ad=18000p As=18000p Pd=820u Ps=820u NRS=O.54 NRD=0.54.MODEL RIT4007P7 PMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=5E-8 XJ=2.26E-7 NCH=1E15 NSUB=8E14 XT=8.66E-8 +VTH0=-1.65 U0= 400 WINT=1.0E-6 LINT=1E-6 +NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-8 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 pclm=5 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) Page 38

SPICE MODELS FOR MOSFETS * From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology.MODEL RITSUBN7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8 +VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology.MODEL RITSUBP7 PMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=2.26E-7 NCH=7.12E16 NSUB=3.16E16 XT=8.66E-8 +VTH0=-1.0 U0= 376.72 WINT=2.0E-7 LINT=2.26E-7 +NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) Page 39

SPICE MODELS FOR MOSFETS *4-4-2013 LTSPICE uses Level=8 * From Electronics II EEEE482 FOR ~100nm Technology.model EECMOSN NMOS (LEVEL=8 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=5E-9 XJ=1.84E-7 NCH=1E17 NSUB=5E16 XT=5E-8 +VTH0=0.4 U0= 200 WINT=1E-8 LINT=1E-8 +NGATE=5E20 RSH=1000 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *4-4-2013 LTSPICE uses Level=8 * From Electronics II EEEE482 FOR ~100nm Technology.model EECMOSP PMOS (LEVEL=8 +TOX=5E-9 XJ=0.05E-6 NCH=1E17 NSUB=5E16 XT=5E-8 +VTH0=-0.4 U0= 100 WINT=1E-8 LINT=1E-8 +NGATE=5E20 RSH=1000 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) * Page 40

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