Solid State Device Fudametals ES 345 Lecture ourse by Alexader M. Zaitsev alexader.zaitsev@csi.cuy.edu Tel: 718 98 81 4101b ollege of State Islad / UY
Dopig semicoductors Doped semicoductors are semicoductors, which cotai impurities, foreig atoms icorporated ito the crystal structure of the semicoductor. Either these impurities ca be uitetioal, due to lack of cotrol durig the growth of the semicoductor, or they ca be added o purpose to provide free carriers i the semicoductor. Ioizatio of a shallow door ad a shallow acceptor. ollege of State Islad / UY
Dopats for dopig A 4 semicoductors Dopats i silico ad germaium Acceptors Doors ollege of State Islad / UY 3
Dopats for A 3 B 5 semicoductors Dopats i GaAs Acceptors Doors Ga As Ga As Ga As Ga As Ga -type: tellurium, sulphur (substitutig As), ti, silico, germaium (substitutig Ga). p-type: zic, chromium (substitutig Ga), silico, germaium (substitutig As). ollege of State Islad / UY 4
Ioizatio eergy of dopats i semicoductors Ioizatio eergy of shallow doors ad acceptors ca be evaluated usig hydrogeic model: Ioizatio eergy E Hio ad orbital radius a 0 of hydroge atom m 0 e 4 E Hio 13.6 ev 8e0 h Ioizatio eergy E io ad orbital radius r D,A of doors ad acceptors E io m* e 4 8e e 0 h ~50 mev r D,A 4πεε 0ħ m e ~1 m Trajectory of a electro boud to a door io withi a semicoductor crystal. ollege of State Islad / UY 5
Eergy levels of doors ad acceptors oductio Bad Door Level E d E c Door ioizatio eergy Acceptor Level Valece Bad Acceptor ioizatio eergy E a E v Ioizatio eergy of selected doors ad acceptors i silico Doors Acceptors Dopat Sb P As B Al I Ioizatio eergy, E c E d or E a E v (mev) 39 44 54 45 57 160 ollege of State Islad / UY 6
Homework Hydrogeic model of doors ad acceptors alculate the ioizatio eergies ad radii of doors ad acceptors i Si ad Ge. Dielectric costat of silico is e 11.7. Dielectric costat of germaium is e 16.. m */m 0 0.6 m p */m 0 0.39 ollege of State Islad / UY 7
p i harge eutrality 1/ i d a d a p 1/ i a d a d ollege of State Islad / UY Solid State Device Fudametals Sice doped semicoductor, as a whole, is electroeutral, cocetratio of egative charges equals the cocetratio of positive charges. Aioized Dioized p 8
Homework ocetratio of electros ad holes 1. alculate cocetratios of electros ad holes i Si ad Ge with door cocetratio of 3x10 17 cm -3 ad acceptor cocetratio of 8x10 16 cm -3 at room temperature.. Will these cocetratios chage much with temperature icrease to 100? 9 ollege of State Islad / UY
harge carrier cocetratio i doped semicoductor -type D A i p D A i D if D A, ad p i d p-type a d i p a d p i if, a d p a ad i a ollege of State Islad / UY 10
Dopat compesatio: Example What are ad p i Si with (a) D 610 16 cm -3 ad A 10 16 cm -3 ad (b) additioal 610 16 cm -3 of A? (a) d a i p / 10 410 0 16 cm 3 / 410 (b) a 10 16 + 610 16 810 16 cm -3 > d 16.510 3 cm 3 + + + + + + 410 16 cm -3...... d 610 16 cm -3..... a... 10... 16 cm -3 p a d i / p 10 810 0 16 / 10 610 16 16 510 10 3 cm 16 3 cm The resultig carrier desity i compesated material is approximately equal to the differece betwee the door ad acceptor cocetratio: 3 + + + + + +...... d 610 16 cm -3 a 810 - - - - - - - -..... 16 cm. -3 p 10 16 cm -3 ollege of State Islad / UY 11
Homework harge carrier cocetratio i -type ad p-type semicoductor 1. alculate cocetratios of electros ad holes i Si ad Ge cotaiig 3x10 17 cm -3 doors ad 8x10 16 cm -3 acceptors at room temperature with assumptio A, D >> i.. ompare the obtaied values with those calculated i Homework o slide 9. ollege of State Islad / UY 1
Positio of Fermi level versus dopat cocetratio With cocetratio of doors, the Fermi level approaches the coductio bad. With cocetratio of acceptors, the Fermi level approaches the valece bad. E F e E ( E E F kt )/ kt l p E F V E e V ( E E F V kt )/ kt l V p Fermi eergy of doped silico (-type ad p-type) vary with dopig desity. As the dopig icreases, Fermi level shifts towards coductio bad (E c ) i the case of -type dopig ad shifts towards valace bad (E v ) i p-type dopig. ote where Fermi level crosses oductio (valace) bad). ollege of State Islad / UY 13
The Fermi level ad carrier cocetratio Where is E F for 10 17 cm -3? E E F e 0.06 l ( E E kt l F )/ kt 19 17.810 /10 0.146 ev 0.146 ev E E F E Where is E F for p 10 14 cm -3? p E F E V V e ( E E F kt l 0.06 l1.04 V )/ kt V p 19 14 10 /10 0.31eV 0.31 ev E E F E V ollege of State Islad / UY 14
Homework Positio of Fermi level i -type ad p-type semicoductor 1. alculate positio of Fermi level i -type silico with door cocetratio of 3x10 17 cm -3 at room temperature.. alculate positio of Fermi level i p-type silico with acceptor cocetratio of 8x10 16 cm -3 at room temperature. 15 ollege of State Islad / UY
Positio of Fermi level i doped semicoductor versus temperature As the temperature icreases Fermi level shifts towards the middle of the badgap. ollege of State Islad / UY 16
omplete ioizatio of dopats D 10 17 cm -3. What fractio of the doors are ot ioized? Solutio: First assume that all the doors are ioized. D 10 17 cm 3 E F E 146 mev 45meV 146 mev E d E c E f Probability of ot beig ioized: 1 0.5 1 e ( E E )/ kt ((14645)meV)/ 6meV D F 1 0.5 e 1 0.04 E v It is reasoable to assume that at room temperature the complete ioizatio occur, i.e., D. Is assumptio D valid for low doped semicoductors? ollege of State Islad / UY 17
Example: arrier cocetratios What is the hole cocetratio i a -type semicoductor with 10 15 cm -3 of doors? 10 15 cm -3. p 0-3 i 10 cm 15 3 10 cm 10 5 cm -3 After icreasig temperature by 60, remais the same at 10 15 cm -3 while p icreases by about a factor of 300 because of thermal activatio.. E i e What is if p 10 17 cm -3 i a p-type silico wafer? g / kt 0-3 i 10 cm 17 3 p 10 cm 10 3 cm -3 ollege of State Islad / UY 18
Homework Positio of Fermi level i -type ad p-type semicoductor at elevated temperature 1. alculate positio of Fermi level i -type silico with door cocetratio of 3x10 17 cm -3 at a temperature of 00.. alculate positio of Fermi level i p-type silico with acceptor cocetratio of 8x10 16 cm -3 at a temperature of 00. ollege of State Islad / UY 19
Temperature depedece of charge carrier cocetratio Electro desity as a fuctio of temperature i silico with: D 10 16 cm -3 A 10 14 cm -3 E - E D E A - E V 50 mev. d High T: p i V e E g / kt 300 RT LT Low T: D 1/ e ( E E D )/ kt ollege of State Islad / UY 0
Workig temperature rage of semicoductor device At high temperatures, the electrical differece betwee the ad p regios disappears ad the p- juctio becomes ieffective i cotrollig carrier movemet. The basic upper temperature limit of semicoductor material is determied by its badgap eergy. A rule-of-thumb is that the maximum temperature (i K) is approximately 500 times the badgap eergy i ev. For Si this rule gives T max ~ 90. The lower temperature limit is determied by the thermal ioizatio eergy of the dopats. If the temperature is too low, the dopats are ot sufficietly ioized ad there are o isufficiet charge carriers. The result is a coditio called "freeze-out." For example, silico freezes out at about 40 K. ollege of State Islad / UY 1
Depedece of the temperature rage o dopig The higher dopat cocetratio the wider the temperature rage ollege of State Islad / UY
Homework Workig temperature rage 1. High Temperature Limit: For -type silico with 10 16 cm -3 phosphorous doors, at what temperature the cocetratio of holes is 10% of that of electros?. Low Temperature Limit: For -type silico with 10 16 cm -3 phosphorous doors, at what temperature the cocetratio of electros is 10% of that of doors? 3 ollege of State Islad / UY