048 SCIENCE CHINA Information Sciences April 2010 Vol. 53 No. 4: 878 884 doi: 10.1007/s11432-010-0079-8 Frequency dispersion effect and parameters extraction method for novel HfO 2 as gate dielectric LIU HongXia 1, KUANG QianWei 1, LUAN SuZhen 1, ZHAO Aaron 2 & TALLAVARJULA Sai 2 1 School of Microelectronics, Xidian University, Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Xi an 710071, China; 2 Applied Materials Inc, Sunnyvale, CA, 94086, USA Received May 25, 2009; accepted September 10, 2009 Abstract The electric characteristic of MOS capacitor with HfO 2 /SiO 2 /p-si grown by ALCVD (atom layer chemical vapor deposition) is investigated. The C-V curves show that the accumulation capacitances take on the frequency dispersion at high frequency. For MOS capacitor with ultra thin HfO 2 /SiO 2 gate stack, different fabrication processes and measurement equipment will cause parasitic effect. Here an equivalent circuit model that can eliminate the frequency dispersion effect is proposed. The C-V characteristics curve at high frequency shows some distortion because of the bulk defects and the interface states. This paper discusses the distortion of the high frequency MOS C-V characteristic curve. A data processing method is advanced and interface trap density distribution in the band gap is presented. By comparing the ideal C-V curve with the experimental C-V curve, the typical electrical parameters of MOS capacitor are extracted, including the shift of flat-band voltage, the oxide charges and the density of interface traps at the SiO 2 /Si interface. Keywords high k gate dielectric, HfO 2, frequency dispersion, equivalent circuit model, two-frequency C-V measurement, parameters extraction Citation Liu H X, Kuang Q W, Luan S Z, et al. Frequency dispersion effect and parameters extraction method for novel HfO 2 as gate dielectric. Sci China Inf Sci, 2010, 53: 878 884, doi: 10.1007/s11432-010-0079-8 1 Introduction Through efforts of several decades, semiconductor devices have been dramatically scaled down to nanoscale in order to achieve higher device density and performance. As the technology node approaches to 45 nm, the equivalent thickness of silicon oxide gate dielectric reduces to only around 1 nm, which causes intolerable gate leakage current, and makes silicon oxide tends to its fundamental physical limit [1 6]. To reduce the substantial gate leakage current resulting from direct quantum mechanical tunneling across the dielectric layer, high k dielectrics which can give large gate capacitances with dielectric films physically thicker than those of corresponding silicon oxide gate dielectrics are needed. Measurement of C-V curve is an important means to characterize electrical characteristics of high k gate dielectric in MOS devices [7 12]. Nevertheless, the resulting C-V characteristics cannot be directly Corresponding author (email: hxliu@mail.xidian.edu.cn)
LIU HongXia, et al. Sci China Inf Sci April 2010 Vol. 53 No. 4 879 analyzed, as the capacitance measured in accumulation regime appears to be strongly dependent of the measurement frequency. That is why it is called frequency dispersion effect. In this paper, an efficient equivalent circuit model is proposed. Based on this model, the correct capacitance value of HfO 2 /SiO 2 stack gate capacitance can be achieved by measuring C-V curve at two different frequencies. By analyzing the influence of the interface state charge and the distortion regulation of the C-V curve, a data processing method is proposed. Based on the corrected C-V curve, the distribution of the interface state density is presented. And the error of calculating flat-band voltage, fixed charge density and mobile charge density by traditional C-V method are discussed and corrected. 2 Sample fabrication The experiment sample was fabricated by Applied Materials Inc. MOS capacitors with HfO 2 /SiO 2 stack gate were fabricated on p-type silicon wafer. In the process, the SiO 2 dielectric with a thickness of 0.8 nm was deposited on p-type Si (100) substrates as the buffer layer, which can decrease the interface states, charge trapping and the Coulomb scatting greatly. Using ALD technology, the HfO 2 thin film with a thickness of 3 nm was deposited on ultra-thin SiO 2 layer at 330 C by precursor reaction of hafnium tetrachloride (HfCl 4 ) and water vapor. The growth rate is around 0.08 nm each cycle. After each cycle, N 2 was used to purge the deposition chamber, with the pressure of the chamber around 0.01 Torr. The stack gate dielectric consists of a 0.8 nm SiO 2 interfacial layer and a 3 nm HfO 2 layer, as is shown in Figure 1. The Al electrode with the thickness of 2000 Å was deposited on the HfO 2 /SiO 2 stack gate by electron beam physical vapor deposition (EBPVD), forming capacitors with four different areas S 1, S 2, S 3 and S 4. S 1 =21 21 πµm 2, S 2 =37 37 µm 2, S 3 = 65 21 µm 2, S 4 =15 15 πµm 2. 3 Four-element equivalent circuit model Figure 2 shows the equivalent model of frequency dispersion effect. The typical two-element parallel circuit model is shown in Figure 2(a). It consists of capacitor C and conductance G. Nevertheless, as the gate oxide thickness keeps decreasing, and the leakage current caused by tunneling mechanism keeps increasing, the corresponding equivalent resistance should be considered. Moreover, the series resistance caused by the contact of metal and substrate will influence the measured capacitance. All this makes the two-element model inaccurate. Therefore, Figure 2(b) presents a three-element equivalent circuit for solving these problems. For the same equivalent thickness, HfO 2 /SiO 2 stack gate has a larger physics thickness than SiO 2, which will effectively reduce the gate leakage current. Figure 3 shows the J-V curve for 3 nm HfO 2 /0.8 nm SiO 2 stack gate. The leakage current density for the 3 nm HfO 2 /0.8 nm SiO 2 stack gate under 5 V is only 0.212 µa/cm 2, which indicates that parallel resistance can be neglected for HfO 2 /SiO 2 stack gate. There are a larger number of defects in HfO 2 than in SiO 2. The trapping and de-trapping process in these defects will seriously influence the measured capacitance value. Besides, the parallel capacitance introduced by connect line and probe system will also influence the capacitance measurement [13 16]. Therefore, Figure 2(c) presents a new four-element equivalent circuit, from which we can get the corrected dual-frequency model. In this equivalent circuit, C 0 represents the ideal gate capacitance, R P is not considered for the small leakage current, R S represents the series resistance of substrate and metal contact, and R s represents the parallel capacitance introduced by connect line and probe system. Besides, the model introduces the D t that represents the influence of the defects on HfO 2 dielectric. With this model, the accurate capacitance can be calculated when testing results under two different frequencies are provided. The impedance of the two-element circuit model shown in Figure 2(a) is given by where D = G ωc Z(ω) = D j ωc(1 + D 2 ), (1) is the dissipation, and G and C both come from measurement values.
880 LIU HongXia, et al. Sci China Inf Sci April 2010 Vol. 53 No. 4 Figure 1 TEM photo of HfO 2 /SiO 2 stack gate MOS capacitor deposited by ALD. Figure 2 Equivalent model of frequency dispersion effect for HfO 2 /SiO 2 stack gate. (a) Two-element equivalent model; (b) three-element equivalent model; (c) four-element equivalent model. Figure 3 J-V curve for 3 nm HfO 2 /0.8 nm SiO 2 stack gate. The impedance of the four-element circuit model shown in Figure 2(c) is given by Z(ω) = Rs(1 jωcsrs) Dt j 1 + (ωcsrs) 2 + ωc0(1 + Dt 2 ). (2) The real and imaginary parts of eq. (1) are equal to those of eq. (2) respectively. The real part reads D ωc(1 + D 2 ) = R s 1 + (ωc s R s ) 2 + D t ωc 0 (1 + Dt 2 (3) ).
LIU HongXia, et al. Sci China Inf Sci April 2010 Vol. 53 No. 4 881 Figure 4 Measured curves and dual-frequency corrected C-V curves for MOS capacitors with different areas. (a) C-V curve (S 1 =21 21 πµm 2 ); (b) C-V curve (S 2 =37 37 µm 2 ); (c) C-V curve (S 3 =65 21 µm 2 ); (d) C-V curve (S 4 =15 15 πµm 2 ). The imaginary part reads 1 ωc(1 + D 2 ) = ωc s Rs 2 1 + (ωc s R s ) 2 + 1 ωc 0 (1 + Dt 2 ). (4) Measuring C and G at two different frequencies, substituting them into eqs. (3) and (4) for each frequency, making subtraction, and solving C 0, D t, C s, R s, finally we have eqs. (5) (8). [ ] D t ω 1 D 1 C 0 = (ω 1 ω 2 ) 1 + Dt 2 C 1 (1 + D1 2) ω 2 D 2 C 2 (1 + D2 2), (5) D t = [C 1 C 2 (1 + D1 2)(1 + D2 2 )]2 [ω 1 C 2 (1 + D2 2) ω 2C 1 (1 + D1 2)][ω 1D 1 C 2 (1 + D2 2) ω 2D 2 C 1 (1 + D1 2 (6) )], C s = ω DC 0(1 + D 2 t ) D t (1 + D 2 ) C 0 (1 + D 2 t ) C(1 + D 2 ), (7) R s = CC 0 (1 + D 2 )(1 + D 2 t ) C s [DC 0 (1 + D 2 t ) D t C(1 + D 2 )][C 0 (1 + D 2 t ) C(1 + D 2 )]. (8) 4 Model verification and parameters extraction The C-V characteristic of the HfO 2 /SiO 2 gate MOS capacitor was measured by Keithley 590 system. Figure 4(a) (d) show the C-V curves measured at two different frequencies and four-element model corrected dual-frequency C-V curves of HfO 2 /SiO 2 /p-si MOS capacitor samples with four different areas. The areas of the capacitors are S 1 =21 21 πµm 2, S 2 =37 37 µm 2, S 3 = 65 21 µm 2, S 4 =15 15 πµm 2.
882 LIU HongXia, et al. Sci China Inf Sci April 2010 Vol. 53 No. 4 Figure 5 Comparison of ideal C-V curve and dual-frequency corrected C-V curve. (a) C-V curve (S 1 =21 21 πµm 2 ); (b) C-V curve (S 2 =37 37 µm 2 ); (c) C-V curve (S 3 =65 21 µm 2 ); (d) C-V curve (S 4 =15 15 πµm 2 ). As shown in Figure 4, there is serious frequency dispersion at high frequency (f =1 MHz) for capacitors with different areas, which is shown using the symbol of square. The C-V characteristic with measurement frequency 100 khz is shown by the symbol of circle. Considering the influence of D t, R S and C S, the frequency dispersion can be effectively eliminated by the four-element circuit model, which is shown using the symbol of triangle. The corrected C-V curve is much closer to the C-V curve at 100 khz, with an error less than 0.1%, which means that the four-element equivalent model can correct the C-V characteristic at high frequency. The error between measured value and corrected value is caused by the hot noise. 5 Experiment result and analysis Figure 5(a) (d) give a comparison of the dual-frequency corrected C-V curve and ideal C-V curve of MOS capacitors with different areas. As shown in the figure, there is also difference between corrected curve and ideal curve. This difference is caused by the interface traps. As the interface traps cannot follow the voltage variety of alternating current under high frequency testing, the measured C-V curve will shift along the coordinate axis of voltage, which makes it different from the ideal C-V curve. Besides, compared with the ideal curve, distortion is found at the upside of the corrected C-V curve, while the underside keeps the same. As we know, the interface states located at the underside half of the band gap are donor-like interface states. The MOS devices will be in the inversion region. When the positive voltage is applied on the gate electrode, the surface band will bend toward underside and E F will approach to E c, so that this part of the C-V curve should be the same as the ideal C-V curve. When the gate voltage is negative, the surface band will bend toward upside, and the donor-like interface states above E F will be positive. In order to compensate for the extra positive charge at the interface states, an extra negative V g should be given to make the surface lie in flat-band state. As V g increases towards negative, a larger
LIU HongXia, et al. Sci China Inf Sci April 2010 Vol. 53 No. 4 883 Table 1 Extracted parameters of MOS capacitors Parameters S 1 S 2 S 3 S 4 C OX (pf) 38.551 38.106 37.994 19.675 V FB (V) 0.773 0.788 0.765 0.789 N OX (cm 2 ) 1.74 10 12 1.10 10 12 1.98 10 12 5.49 10 11 D it (@0.56 ev) 4.32 10 11 3.2 10 11 1.7 10 11 8.34 10 11 V g is needed to compensate for the positive charge interface states, which will make the C-V curve shift toward the negative direction. When E F is moved to the donor-like interface states energy level, inflexions with different variation law will appear in C-V curve. The capacitance values of different area MOS capacitors can be obtained from Figure 5. Capacitances of samples S 1, S 2, S 3 and S 4 are 38.551, 38.106, 37.994 and 19.675 pf respectively. The flat-band voltage can also be obtained from Figure 5. After finding out the capacitance value at 0 V in ideal C-V curve, the corresponding voltage of this capacitance value in the corrected curve is the flat-band voltage V FB, and the corresponding capacitance value is the flat-band capacitance C FB. According to the flat-band voltage equation V FB = Φ ms Q ox /C ox, the oxide charge density can be calculated if the substrate doping concentration, metal work function and flat-band voltage are given. For Al electron and p-type Si, the work function difference Φ ms = 0.818 V. The oxide charge density of four samples are 1.74 10 12, 1.10 10 12, 1.98 10 12 and 5.49 10 11 cm 2 respectively. With Terman method, the interface state density at SiO 2 /Si interface can be calculated, which are 4.32 10 11, 3.2 10 11, 1.7 10 11 and 8.34 10 11 cm 2 respectively. From Figure 5, the electrical parameters of MOS capacitors with different areas can be extracted, as shown in Table 1. 6 Conclusions The electrical characteristic of HfO 2 /SiO 2 /p-si stack gate MOS capacitor is investigated. Frequency dispersion effect is found at high frequencies. Therefore, an equivalent circuit model for eliminating the frequency dispersion effect is proposed. Compared with the traditional two-frequency equivalent circuit model, three parasitic parameters, namely influence of defects, series resistance and parallel capacitance are introduced in this model. Experimental and calculated results indicate that the four-element model can eliminate the frequency dispersion effect. The existence of the interface state will influence the high frequency C-V characteristic. By studying the distribution of the interface state in the band gap, the regulation of distortion of the C-V curve are obtained. By comparing the ideal C-V curve with the experimental C-V curve, the typical electrical parameters of MOS capacitors are extracted. The experimental results show that the model can eliminate the frequency dispersion effect and provide accurate capacitance value. Acknowledgements This work was supported by the National Natural Science Foundation of China (Grant No. 60976068), the Cultivation Fund of the Key Scientific and Technical Innovation Project, Ministry of Education of China (Grant No. 708083), Specialized Research Fund for the Doctoral Program of Higher Education (Grant No. 200807010010), and Applied Materials Innovation Fund (Grant No. XA-AM-200701). References 1 Ribes G, Mitard J, Denais M, et al. Review on high-k dielectrics reliability issues. IEEE Trans Device Materials Reliab, 2005, 5: 5 19 2 Kim Y M, Lee J C. Reliability characteristics of high-k dielectrics. Microelectr Reliab J, 2004, 44: 183 193 3 Deshpande A S. Fundamental studies on alternative high-k gate dielectric materials. Dissertation for the Doctoral Degree. Chicago: University of Illinois at Chicago, 2005. 133 138
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