ENGG 1203 Tutorial_9 - Review Boolean Algebra 1. Combinational & Sequential Logic 2. Computer Systems 3. Electronic Circuits 4. Signals, Systems, and Control Remark : Multiple Choice Questions : ** Check carefully : Lose marks if INCORRECT? 1 2 Combinational Logic Each function can be represented equivalently in 3 ways: Truth table Boolean logic expression Schematics Two standard canonical forms of organizing the terms: Sum of Product (SOP): Product of Sum (POS): De Morgan s theorem (break the bar, change the operator): Simplifying Logic Circuits Two methods for simplifying: Algebraic method (use Boolean algebra theorems) Karnaugh mapping method (systematic, step-by-step approach) NOT CARE SOP : output = 1 POS : output = 0 3 4
Example : Example 1 A K-map for an output for four inputs, A, B, C, and D is given by : Which of the following is a possible expression for the output? 3 time delay 2 time delay 5 gates 2 gates >> Less overall propagation delay << 5 Direct using K-map, we have Y BD ABD ABC ABC Ans : A 6 Example 2 Which is the output of the following digital circuit? A+B (A+B)(A+C). A+BC A+C B+C (B +C)(B+C).. C B + C B Y ( A BC) C... Y ( A B ) C Ans : A 7 Example 3 Which is the output of the following digital circuit? x+y x +y x +y (x+y )(x +y) x +y +z. xy+x y xy+x y +z (xy+x y +z)(x +y +z) Ans : A OR E 8
Example 4 Which is the output of the following digital circuit? ( + abb ( + ) + ab 1 ) + ab 1 + b) Example 5 Which of the following circuit correctly represents the function of the following truth table? Ans : E 9 Ans : E 10 Example 6 Example 7 Which of the following is equivalent to ( x y) z? Given that A B 1, which of the following expressions are equivalent? Ans : A OR E Ans : A 11 12
Sequential Logic In combinational logic, the output is a pure function of the present input only, i.e., no memory effect. In sequential logic, the output depends not only on the present input, but also on the history of the input, i.e., memory effect. Sequential logic circuits are circuits that contains state elements. State elements are circuits that remember its input. Flip-Flop Edge-Trigger Flip-Flop: a circuit that changes its output only when the value of its clock input changes. 0 1 = Rising Edge 1 0 = Falling Edge D Flip-Flop: A D-FF has 1 data input port D, and a single output port Q. At the rising edge of clock signal, the value at input D is captured. 13 14 Flip-Flop T Flip-Flop: Finite State Machine An abstraction of computation. Finite number of states that the machine can be included. The conditions under which it will transition from one state to another. At any moment in time, an FSM can only exist in ONE of the defined states. 15 16
Finite State Machine All possible states & transitions are included. Each state transition is labeled with: Condition that the transition should take place Output of the FSM during the transition. Steps in designing a State Machine Draw a state transition diagram An initial state Other states to keep track of various activities Transitions Generate a state transition table and a output table Write state transition table and output table in binary State assignment, i.e., the code used for each state Derive canonical sum-of-product expressions K map, Logisim.. Draw the circuit Register, State Transition Logic and Output Logic Circuit 17 18 FSM - State diagram FSM - Next state and output logic - write down ALL known transition, other as NOT Care The FSM that determines outputs from presents states ONLY - K-map, Logisim, simplification - Design logic circuit -Next state logic -State register -Output logic SYSTEM 19 The FSM that determines outputs from presents states and INPUT 20
Moore and Mealy Machine (Input /Output) Example 8 Debouncing State Machine For mechanical switches, output usually bounces between 0 and 1 for a short period before settle, similar to the diagram shown below. Moore Machine The FSM that determines outputs from presents states ONLY Less integrated Safer for use.. Mealy Machine The FSM that determines outputs from presents states and INPUT Less gates. faster or slower? 21 22 Example 8 Complete the state diagram Example 8 Complete the following next state logic table for the debouncing FSM. For don t care situations, write down X in the corresponding space. 23 24
Example 9 Logic on Blood Types Example 9a Complete the following truth table. 25 26 Example 9b Based on your answer in a, derive and simplify the expression of m in terms of d1, d0, a1, a0 using Karnaugh map. Putting in the K-map, we have, Example 9c Implement this blood type compatibility test (BTCT) circuit using only NOT, 2-input AND, and 2-input OR gates. m d1d 0a0 a1a0 d 0a1a 0 d1d 0 Therefore, the simplified expression form is : m d 1d 0a0 a1a0 d 0a1a 0 d1d 0 27 28
Example 9 d Example 9d NOT care states to 00 K map b1 tatb( t b 0 tat ab ab ( t b t 0 t 0 ) ) 29 30 Example 9e Tradeoffs : Benefits of reusing existing circuits : Less design effort Shorter time to market Higher assurance that at least part of the system is in working condition Shortcoming of reusing existing circuits: Potentially slower circuits due to extra interfacing logic Difficult to debug with circuits developed by third party that are closed-source or lack of documentation. 31 Number Systems 3 commonly used number systems: Base 10 : decimal Base 2 : binary Base 16 : hexadecimal Conversions between different number systems: From binary to hexadecimal: 4 digits 2 = 1 digit 16 From decimal to binary/hexadecimal : short division with base 2 or 16; Count from the bottom. From binary/hexadecimal to decimal : start from the right-most with Binary point: integral part: 2 0, 2 1, 2 2 ; fractional part: 2-1, 2-2, 2-3. 32
Representing Numbers Sources & Linear Components Unsigned numbers : non-negative. [0, 2 n -1] Signed-magnitude: add a sign bit (1 for negative, 0 for positive). [-(2 n-1-1); (2 n-1-1)] 1 s complement: for negative number, apply bitwise NOT. [-(2 n-1-1); (2 n-1-1)] 2 s complement: adding 1 to the 1 s complement. [-2 n-1 ; (2 n-1-1)] Floating point numbers : representing a decimal value with the IEEE754 Single Precision (32-bit) format. IEEE754 Double Precision (64-bit) IEEE754 Extended Double Precision (80-bits) IEEE754 Quadruple Precession (128-bits) 33 34 Circuit Analysis Ohm s Law : proportional relationship between the voltage and current across a resistor. V = IR (1) Kirchhoff s Current Law (KCL) : sum of current in = sum of current out. (2) Kirchhoff s Voltage Law (KVL): sum of voltage around a loop = 0. (3) 35 Circuit Analysis Current source Open ; Voltage source Short Thévenin's Theorem Remove R L, by Open circuit, then voltage across R L, is V Thevenin Open R L, replace source(s) by OPEN or SHORT, to find R Thevenin Norton's Theorems Replace R L by Short circuit, find I norton Open R L, replace source(s) by OPEN or SHORT, to find R norton R Thevenin = R norton V Thevenin = I norton R norton I norton = V Thevenin /R Thevenin 36 https://www.youtube.com/watch?v=vqaa4gwjy_4
Example 10(a) R L is the load resistor connected to the terminals A and B. We can maintain the same voltage V L and current I L in the transformation by the following procedure: The Th evenin equivalent voltage, V th, is equal to the voltage across AB if there is no load, i.e., an open circuit; Calculate the current I when AB is short-ciruited. Then, the Th evenin equivalent resistance, R th, is equal to V th /I. Example 10(a) 37 38 Example 10(b) Th evenin Theorem Using your knowledge developed from previous parts, determine in the voltage across AB in the following circuit : Example 10 (b) With the results in Part(a), we can simplify the circuit as follows : With KCL at point A, we get Therefore, we can easily see that v AB = 4V 39 40
Example 11(a) Try to determine the power consumption of the 4Ω resistor in the following circuit : Example 11 (a) 41 42 Example 11 (b) Example 11(c) By using results from Part (a) and (b), or otherwise, determine the power dissipated at the 4Ω resistor between a and b. 4 4 6 4V 18V 43 44
Operational Amplifiers Ideal Op-Amp No current flow into the input terminals, Infinite input resistance : I + = I - = 0 Configuration : Negative feedback. then V + = V - Buffer / Voltage follower Op Amp Buffer isolation or voltage follower Gain =1, same phase Non Inverting Op Amp R 1 = Infinite, R 2 = 0 R1 = Infinite, R2 = 0 GAIN =?? 45 UNIT Gain Power?? 46 Operational Amplifiers Non Inverting Amplifier Input signal connected to + input Inverting Amplifier Input signal connected to - input Differential Amplifiers Input signals connected to both + & - input Summing Amplifiers Connected with more than one input Basic Op-Amp Configurations http://www.ti.com/ww/en/bobpease/assets/an-31.pdf Basic Op-Amp Configurations http://www.ti.com/ww/en/bobpease/assets/an-31.pdf 47 48
Basic Op-Amp Configurations http://www.ti.com/ww/en/bobpease/assets/an-31.pdf Basic Op-Amp Configurations http://www.ti.com/ww/en/bobpease/assets/an-31.pdf 49 50 Basic Op-Amp Configurations http://www.ti.com/ww/en/bobpease/assets/an-31.pdf Example 13 In the following circuit, find R f in terms of R such that V o = 15V i. Two roots. 51 52
Example 14 Example 15 Find V +, V -, V o, V A and V B? V + and V - are virtually connected!!! Thus 5k appears in parallel to (3k+2k) So, by current division rule: 53 = -0.5m 0.5mx4k = -0.5m 0.5mx2k 54 = -0.5m+ 0.5mx3k Example 15 (Another Method) Example 16 55 56
Example 17 Example 18 Non-inverting inverting 57 58 Signals, Systems, and Control Building Blocks in Transform Domain z-transform and system transfer function Notations Arithmetic Feedback systems First-order feedback system Second-order feedback system Conversions between multiple representations Signal flow diagram Difference equation System function (with z operator, z-transform) System function (with R operator) Unit-sample response (long division) 59 60
Difference Equation and z-transform Difference equations : express signal in time domain. First-Order Feedback System z-transform : express signal in transform domain. 61 62 Second-Order Feedback System Example Feedback System Y(n) = X(n-2) + 1 2 Z-transform : Long Division Polynomial representations Y = + 1 63 64
General Feedback design A more generic setup of feedback loop: Feedback Control A general feedback pattern: controller = C(z), system = P(z), sensor = G(z) P(z) may be unstable Design C and G such that the closed-loop system 65 66 Pole location Where the pole 1 st order or 2 nd order real or complex pole is <1, =1, or > 1 Good Luck! 67 https://spectrum.ieee.org/at-work/innovation/engineering-achievements-the-two-lists -END - 68