74HC03-Q100; 74HCT03-Q100

Similar documents
74HC30-Q100; 74HCT30-Q100

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC151-Q100; 74HCT151-Q100

74HC08-Q100; 74HCT08-Q100

74HC153-Q100; 74HCT153-Q100

74HC86; 74HCT86. Quad 2-input EXCLUSIVE-OR gate. The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function.

74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate

74HC20; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NAND gate

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter

74HC10; 74HCT General description. 2. Features and benefits. 3. Ordering information. Triple 3-input NAND gate

74HC2G08-Q100; 74HCT2G08-Q100

74HC1G32-Q100; 74HCT1G32-Q100

74HC1G02-Q100; 74HCT1G02-Q100

The 74LV08 provides a quad 2-input AND function.

74HC153; 74HCT General description. 2. Features and benefits. Dual 4-input multiplexer

74AHC30-Q100; 74AHCT30-Q100

74HC32-Q100; 74HCT32-Q100

The 74LV08 provides a quad 2-input AND function.

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

2-input EXCLUSIVE-OR gate

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

74HC126; 74HCT126. Quad buffer/line driver; 3-state

74HC08; 74HCT General description. 2. Features and benefits. 3. Ordering information. Quad 2-input AND gate

74HC540; 74HCT540. Octal buffer/line driver; 3-state; inverting

74HC280; 74HCT bit odd/even parity generator/checker

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

Dual buffer/line driver; 3-state

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.

74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting

74HC541; 74HCT541. Octal buffer/line driver; 3-state

74HC132-Q100; 74HCT132-Q100

74HC00; 74HCT00. The 74HC00; 74HCT00 provides a quad 2-input NAND function.

74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

74HC174; 74HCT174. Hex D-type flip-flop with reset; positive-edge trigger

74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.

74HC139; 74HCT139. Dual 2-to-4 line decoder/demultiplexer

74HC365; 74HCT365. Hex buffer/line driver; 3-state

The 74LV32 provides a quad 2-input OR function.

74LVC General description. 2. Features and benefits. 3. Ordering information. Triple 3-input OR gate. The 74LVC332 is a triple 3-input OR gate.

74HC04; 74HCT General description. 2. Features and benefits. 3. Ordering information. Hex inverter

74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger

74HC253; 74HCT253. Dual 4-input multiplexer; 3-state

Dual buffer/line driver; 3-state

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

74HC132; 74HCT132. Quad 2-input NAND Schmitt trigger

74LVC07A-Q100. Hex buffer with open-drain outputs

3-to-8 line decoder, demultiplexer with address latches

74AHC1G00; 74AHCT1G00

74HC107-Q100; 74HCT107-Q100

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

74AHC14-Q100; 74AHCT14-Q100

74AHC86; 74AHCT86. Quad 2-input EXCLUSIVE-OR gate. The 74AHC86; 74AHCT86 provides a 2-input exclusive-or function.

74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate

74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop.

74AHC2G126; 74AHCT2G126

74AHC541-Q100; 74AHCT541-Q100

The 74LVC1G02 provides the single 2-input NOR function.

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer.

The 74LVC10A provides three 3-input NAND functions.

Octal buffer/line driver; 3-state

NXP 74HC_HCT1G00 2-input NAND gate datasheet

74AHC14; 74AHCT14. Hex inverting Schmitt trigger

2-input single supply translating NAND gate

7-stage binary ripple counter

74HC109-Q100; 74HCT109-Q100

74LVC1G125-Q100. Bus buffer/line driver; 3-state

Hex inverter with open-drain outputs

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

4-bit magnitude comparator

74HC107; 74HCT107. Dual JK flip-flop with reset; negative-edge trigger

74AHC125; 74AHCT125. Quad buffer/line driver; 3-state

74HC08; 74HCT08. Temperature range Name Description Version. -40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.

74HC3G04; 74HCT3G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Triple inverter

74HC175; 74HCT175. Quad D-type flip-flop with reset; positive-edge trigger

74HC2G02; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Dual 2-input NOR gate

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.

74HC4514; 74HCT to-16 line decoder/demultiplexer with input latches

74HC1G14; 74HCT1G14. The standard output currents are half of those of the 74HC14 and 74HCT14.

74HC238; 74HCT to-8 line decoder/demultiplexer

HEF40175B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Quad D-type flip-flop

74LVC125A. 1. General description. 2. Features and benefits. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

Low-power dual Schmitt trigger inverter

74LV03. 1 General description. 2 Features and benefits. 3 Ordering information. Quad 2-input NAND gate

74AHC1G14; 74AHCT1G14

74AVC16374-Q General description. 2. Features and benefits. 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

74HC597-Q100; 74HCT597-Q100

Single supply translating buffer/line driver; 3-state

74HC164; 74HCT bit serial-in, parallel-out shift register

74HC2G125; 74HCT2G125

74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description

74HC1G125; 74HCT1G125

Bus buffer/line driver; 3-state

Transcription:

Rev. 1 4 July 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input NND gate with open-drain outputs. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V CC. This product has been qualified to the utomotive Electronics Council (EC) standard Q100 (Grade 1) and is suitable for use in automotive applications. utomotive product qualification in accordance with EC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Input levels: For 74HC03-Q100: CMOS level For 74HCT03-Q100: TTL level ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-114F exceeds 2000 V MM JESD22-115- exceeds 200 V (C = 200 pf, R = 0 ) Multiple package options Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC03D-Q100 40 C to +125 C SO14 plastic small outline package; 14 leads; body width SOT108-1 74HCT03D-Q100 74HC03DB-Q100 40 C to +125 C SSOP14 3.9 mm plastic shrink small outline package; 14 leads; body SOT337-1 74HCT03DB-Q100 width 5.3 mm 74HC03PW-Q100 74HCT03PW-Q100 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

4. Functional diagram 1 2 4 5 9 10 12 13 1 1B 2 2B 3 3B 4 4B 1Y 2Y 3Y 4Y 3 6 8 11 B Y GND mna212 001aab715 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning Fig 4. Pin configuration SO14 Fig 5. Pin configuration (T)SSOP14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1 to 4 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) V CC 14 supply voltage 74HC_HCT03_Q100 ll information provided in this document is subject to legal disclaimers. NXP B.V. 2013. ll rights reserved. Product data sheet Rev. 1 4 July 2013 2 of 14

6. Functional description Table 3. Function table [1] Input Output n nb ny L L Z L H Z H L Z H H L [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage 0.5 +7 V V O output voltage [1] 0.5 +7 V I IK input clamping current V I < 0.5 V or V I >V CC +0.5 V [1] - 20 m I OK output clamping current V O < 0.5 V [1] - 20 m I O output current 0.5 V < V O - 25 m I CC supply current - 50 m I GND ground current 50 - m T stg storage temperature 65 +150 C P tot total power dissipation [2] SO14 and (T)SSOP14 packages - 500 mw [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 package: P tot derates linearly with 8 mw/k above 70 C. For (T)SSOP14 packages: P tot derates linearly with 5.5 mw/k above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC03-Q100 74HCT03-Q100 Unit Min Typ Max Min Typ Max V CC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V V I input voltage 0 - V CC 0 - V CC V V O output voltage 0 - V CC 0 - V CC V T amb ambient temperature 40 +25 +125 40 +25 +125 C t/v input transition rise and fall rate V CC = 2.0 V - - 625 - - - ns/v V CC = 4.5 V - 1.67 139-1.67 139 ns/v V CC = 6.0 V - - 83 - - - ns/v 74HC_HCT03_Q100 ll information provided in this document is subject to legal disclaimers. NXP B.V. 2013. ll rights reserved. Product data sheet Rev. 1 4 July 2013 3 of 14

9. Static characteristics Table 6. Static characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC03-Q100 V IH HIGH-level V CC = 2.0 V 1.5 1.2-1.5-1.5 - V input voltage V CC = 4.5 V 3.15 2.4-3.15-3.15 - V V CC = 6.0 V 4.2 3.2-4.2-4.2 - V V IL LOW-level V CC = 2.0 V - 0.8 0.5-0.5-0.5 V input voltage V CC = 4.5 V - 2.1 1.35-1.35-1.35 V V CC = 6.0 V - 2.8 1.8-1.8-1.8 V V OL LOW-level output voltage V I = V IH or V IL I O = 20 ; V CC = 2.0 V - 0 0.1-0.1-0.1 V I O = 20 ; V CC = 4.5 V - 0 0.1-0.1-0.1 V I O = 20 ; V CC = 6.0 V - 0 0.1-0.1-0.1 V I O = 4.0 m; V CC = 4.5 V - 0.15 0.26-0.33-0.4 V I O = 5.2 m; V CC = 6.0 V - 0.16 0.26-0.33-0.4 V I I input leakage current V I = V CC or GND; V CC =6.0V - 0.1 - - 1-1 I OZ OFF-state output current per input pin; V I =V IL ; V O =V CC or GND; other inputs at V CC or GND; V CC =6.0V; I O =0 - - ±0.5 - ±5.0 - ±10 I CC supply current V I = V CC or GND; I O =0; - 2.0 - - 20-40 V CC =6.0V C I input capacitance - 3.5 - - - - - pf 74HCT03-Q100 V IH HIGH-level V CC = 4.5 V to 5.5 V 2.0 1.6-2.0-2.0 - V input voltage V IL LOW-level V CC = 4.5 V to 5.5 V - 1.2 0.8-0.8-0.8 V input voltage V OL LOW-level output voltage V I =V IH or V IL ; V CC =4.5V I O =20-0 0.1-0.1-0.1 V I O = 4.0 m - 0.15 0.26-0.33-0.4 V I I I OZ input leakage current OFF-state output current V I =V CC or GND; V CC =5.5V per input pin; V I =V IL ; V O =V CC or GND; other inputs at V CC or GND; V CC = 5.5 V; I O =0 - - 0.1-1 - 1 - - ±0.5 - ±5.0 - ±10 74HC_HCT03_Q100 ll information provided in this document is subject to legal disclaimers. NXP B.V. 2013. ll rights reserved. Product data sheet Rev. 1 4 July 2013 4 of 14

Table 6. Static characteristics continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max I CC supply current V I = V CC or GND; I O =0; V CC =5.5V I CC C I additional supply current input capacitance per input pin; V I =V CC 2.1 V; I O =0; other inputs at V CC or GND; V CC = 4.5 V to 5.5 V 10. Dynamic characteristics - - 2.0-20 - 40-100 360-450 - 490-3.5 - - - - - pf Table 7. Dynamic characteristics GND = 0 V; C L = 50 pf; for load circuit, see Figure 7. Symbol Parameter Conditions 25 C 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) 74HC03-Q100 t pd propagation delay n, nb to ny; see Figure 6 [1] V CC = 2.0 V - 28 95 120 145 ns V CC = 4.5 V - 10 19 24 29 ns V CC = 5.0 V; C L =15pF - 8 - - - ns V CC = 6.0 V - 8 16 20 25 ns t t transition time see Figure 6 [2] V CC = 2.0 V - 19 75 95 110 ns V CC = 4.5 V - 7 15 19 22 ns V CC = 6.0 V - 6 13 16 19 ns C PD power dissipation capacitance per package; V I =GNDtoV CC [3] - 4 - - - pf 74HC_HCT03_Q100 ll information provided in this document is subject to legal disclaimers. NXP B.V. 2013. ll rights reserved. Product data sheet Rev. 1 4 July 2013 5 of 14

Table 7. Dynamic characteristics continued GND = 0 V; C L = 50 pf; for load circuit, see Figure 7. Symbol Parameter Conditions 25 C 40 C to +125 C Unit 74HCT03-Q100 t pd propagation delay n, nb to ny; see Figure 6 [1] V CC = 4.5 V - 12 24 30 36 ns V CC = 5.0 V; C L =15pF - 10 - - - ns t t transition time V CC = 4.5 V; see Figure 6 [2] - 7 15 19 22 ns C PD power dissipation capacitance per package; V I =GNDtoV CC 1.5 V [3] - 4 - - - pf [1] t pd is the same as t PLZ and t PZL. [2] t t is the same as t THL. [3] C PD is used to determine the dynamic power dissipation (P D in W): P D =C PD V CC 2 f i N+ (C L V CC 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. 11. Waveforms Min Typ Max Max (85 C) Max (125 C) Fig 6. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Input to output propagation delays Table 8. Measurement points Type Input Output V M V M V X 74HC03-Q100 0.5V CC 0.5V CC 0.1V CC 74HCT03-Q100 1.3 V 1.3 V 0.1V CC 74HC_HCT03_Q100 ll information provided in this document is subject to legal disclaimers. NXP B.V. 2013. ll rights reserved. Product data sheet Rev. 1 4 July 2013 6 of 14

V I negative pulse 0 V 90 % V M 10 % t W V M t f t r t r t f V I positive pulse 0 V 10 % 90 % V M t W V M V CC V CC G VI DUT VO RL S1 open RT CL 001aad983 Fig 7. Test data is given in Table 9. Definitions test circuit: R T = termination resistance should be equal to output impedance Z o of the pulse generator. C L = load capacitance including jig and probe capacitance. Test circuit for measuring switching times Table 9. Test data Type Input Load S1 position V I t r, t f C L R L t PZL, t PLZ 74HC03-Q100 V CC 6ns 15pF, 50pF 1k V CC 74HCT03-Q100 3.0 V 6 ns 15 pf, 50 pf 1 k V CC 74HC_HCT03_Q100 ll information provided in this document is subject to legal disclaimers. NXP B.V. 2013. ll rights reserved. Product data sheet Rev. 1 4 July 2013 7 of 14

12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E X c y H E v M Z 14 8 Q pin 1 index 2 1 ( ) 3 θ L p 1 7 L e b p w M detail X 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 0.25 1.75 0.10 0.069 0.010 0.004 1 2 3 b p c D (1) E (1) e H (1) E L L p Q v w y Z 1.45 1.25 0.057 0.049 0.25 0.01 0.49 0.36 0.019 0.014 0.25 0.19 0.0100 0.0075 8.75 8.55 0.35 0.34 4.0 3.8 0.16 0.15 1.27 6.2 5.8 0.244 0.228 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 0.05 1.05 0.041 1.0 0.4 0.039 0.016 0.7 0.6 0.028 0.024 0.25 0.25 0.1 0.01 0.01 0.004 θ 0.7 0.3 o 8 o 0.028 0 0.012 OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT108-1 076E06 MS-012 99-12-27 03-02-19 Fig 8. Package outline SOT108-1 (SO14) 74HC_HCT03_Q100 ll information provided in this document is subject to legal disclaimers. NXP B.V. 2013. ll rights reserved. Product data sheet Rev. 1 4 July 2013 8 of 14

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E X c y H E v M Z 14 8 Q 2 1 ( ) 3 pin 1 index 1 7 detail X L p L θ e b p w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT 1 2 3 b p c D (1) E (1) e H E L L p Q v w y Z(1) max. 0.21 1.80 0.38 0.20 6.4 5.4 7.9 1.03 0.9 1.4 mm 2 0.25 0.65 1.25 0.2 0.13 0.1 0.05 1.65 0.25 0.09 6.0 5.2 7.6 0.63 0.7 0.9 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT337-1 MO-150 99-12-27 03-02-19 Fig 9. Package outline SOT337-1 (SSOP14) 74HC_HCT03_Q100 ll information provided in this document is subject to legal disclaimers. NXP B.V. 2013. ll rights reserved. Product data sheet Rev. 1 4 July 2013 9 of 14

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E X c y H E v M Z 14 8 pin 1 index 2 1 Q ( ) 3 θ 1 7 e b p w M detail X L p L 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT 1 2 3 b p c D (1) E (2) e H (1) E L L p Q v w y Z max. mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT402-1 MO-153 EUROPEN PROJECTION ISSUE DTE 99-12-27 03-02-18 Fig 10. Package outline SOT402-1 (TSSOP14) 74HC_HCT03_Q100 ll information provided in this document is subject to legal disclaimers. NXP B.V. 2013. ll rights reserved. Product data sheet Rev. 1 4 July 2013 10 of 14

13. bbreviations Table 10. cronym CMOS DUT ESD HBM LSTTL MM TTL bbreviations Description Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT03_Q100 v.1 20130704 Product data sheet - - 74HC_HCT03_Q100 ll information provided in this document is subject to legal disclaimers. NXP B.V. 2013. ll rights reserved. Product data sheet Rev. 1 4 July 2013 11 of 14

15. Legal information 15.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 74HC_HCT03_Q100 ll information provided in this document is subject to legal disclaimers. NXP B.V. 2013. ll rights reserved. Product data sheet Rev. 1 4 July 2013 12 of 14

No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations non-english (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT03_Q100 ll information provided in this document is subject to legal disclaimers. NXP B.V. 2013. ll rights reserved. Product data sheet Rev. 1 4 July 2013 13 of 14

17. Contents 1 General description...................... 1 2 Features and benefits.................... 1 3 Ordering information..................... 1 4 Functional diagram...................... 2 5 Pinning information...................... 2 5.1 Pinning............................... 2 5.2 Pin description......................... 2 6 Functional description................... 3 7 Limiting values.......................... 3 8 Recommended operating conditions........ 3 9 Static characteristics..................... 4 10 Dynamic characteristics.................. 5 11 Waveforms............................. 6 12 Package outline......................... 8 13 bbreviations.......................... 11 14 Revision history........................ 11 15 Legal information....................... 12 15.1 Data sheet status...................... 12 15.2 Definitions............................ 12 15.3 Disclaimers........................... 12 15.4 Trademarks........................... 13 16 Contact information..................... 13 17 Contents.............................. 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 2013. ll rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 July 2013 Document identifier: 74HC_HCT03_Q100