Close-Form Moelng of ayout-depenent Mechancal Stress Vve Josh, Valery Suharev ±, Anres orres ±, Kana Agarwal*, Denns Sylvester, Dav Blaauw Unversty of Mchgan, Ann Arbor, MI {vve,enns,blaauw@eecs.umch.eu}, ± Mentor Graphcs Corp., lsonvlle, O {valerysuharev,anrestorres@mentor.com}, *IBM esearch ab, Austn, X {ba@us.bm.com} Abstract Moern CMOS technologes employ process-nuce stress to mprove carrer moblty an ncrease rve current. hs stress has been shown to be strongly layout epenent; however there s a lac of physcal moels relatng potental performance varaton to crtcal layout parameters. hs paper presents compact close-form moels that capture the layout epenence of mechancal stress nuce n the evce channel whle conserng all relevant sources of stress (, tensle/compressve ntre lners, an embee. he moels are calbrate usng rng oscllator frequency ata obtane from an expermental test chp to verfy ther accuracy. esults ncate that the moels accurately capture the layout epenence of stress an carrer moblty for a varety of layout permutatons an the root mean square error n the precte rng oscllator frequency s less than % for the fferent layout experments. hese moels can help rve layout optmzaton an tmng/power analyss wthout the use of technology computer-ae esgn (CAD tools, whch are slow an very lmte n capacty. Categores an Subect Descrptor: B.7.2 [ IC Desgn As] neral erms: Measurement, Performance, heory Keywors: Mechancal Stress, Moblty, Moelng. INODUCION Mechancal stress nucng layout features are use by moern CMOS processes n orer to enhance carrer moblty, for hgher performance. Mechancal stress breas the crystal symmetry of lcon, causng changes n the ban scatterng rates, an/or the carrer effectve mass, whch n turn affects carrer moblty [, 2]. Applcaton of the correct type of stress (tensle or compressve results n sgnfcantly hgher carrer moblty, an mproves transstor performance []. here are three maor layout epenent sources of mechancal stress: Shallow rench Isolaton ( generates compressve stress ue to thermal msmatch wth lcon [4], embee s eptaxally grown n the S/D regons of PMOS evces to nuce hgh compressve stress ue to lattce msmatch [5], an tensle/compressve ntre lner layers are ntegrate nto a sngle, hgh performance process flow calle the Dual Stress ner (DS approach [6]. However, stress ntrouce n the channel, an hence carrer moblty, show a strong epenence on the evce layout an ts neghborng features [7]. As a result, layout propertes such as actve area length, number of contacts, stance of the evce to the well ege, etc. become mportant n etermnng the mechancal stress nuce n the channel of a evce. Fgure shows the layout vew for the three PMOS evces n a -nput NAND gate, along wth the corresponng longtunal stress strbuton uner the channel, for a selecte cross-secton. Although the three evces have entcal gate wth an length, the channel stress s fferent n the three cases epenng on other layout features such as Fg : annel stress strbuton for PMOS evces n a -nput NAND for a selecte cross-secton. actve area length, an contact placement. he evce n the center (evce 2 has hgher stress than the two corner transstors because t s surroune by more. hs fference n stress s reflecte n ther performance, an smulatons show that the rve currents for the center an ege evces ffer by 8.2%. Such epenence can result n sgnfcant varaton n the performance an leaage of evces, base on ther context an layout. echnology computer-ae esgn (CAD tools have been use to smulate evce fabrcaton n orer to capture process nuce mechancal stress, an calculate ts mpact on evce performance an leaage. However, CAD tools base smulaton framewors nvolve tme consumng computatonal steps, an have severely lmte capacty n terms of the number of evces that can be accurately smulate n a sngle run. Hence, there s an urgent nee to evelop scalable, close-form moels for calculatng process nuce stress as a functon of the evce layout, an ts neghborng features, to enable fast an accurate moelng an smulaton of strane evces. In the past, [7, 8] have stue ths layout epenence for fferent sources of stress, for both NMOS an PMOS evces. However, there has been very lttle wor on comprehensve close-form moels of the layout epenence of process nuce stress, an ts mpact on carrer moblty. Authors n [9] focuse manly on moelng moblty changes ue to stress. [] presente a very goo metho at moelng layout epenence of process nuce stress through non process specfc analytc moels. However, whle these moels show a goo ft for solate evce level stress smulaton, they o not account for layout features such as stance of evce from the well ege (tensle/compressve lner nterface, presence of contacts, ummy poly, an neghborng evces. he paper also oes not account for the transverse/lateral stress epenence on layout. So, whle these moels prove a goo ft for smple evce level experments, they fal to account for ey neghborng features whch are crtcal for accurate stress smulaton, when focusng on the complete crcut layout. In ths paper, we propose compact close-form moels for layout epenence of process nuce stress, an ts mpact on carrer moblty. e analyze the physcs behn stress nucng process steps, an solve relevant equatons escrbng the stress strbuton, n orer to evelop the moels. nce the ervaton s base on unerlyng physcs, the erve moels are scalable. e moel stress ue to Shallow rench Isolaton (, tensle/compressve ntre lners, an embee S/D layers (use only n PMOS evces. In orer to quantfy the mpact of
stress on moblty, we use the pezoresstve moel [2]. nce longtunal stress vares across the evce wth; we propose parttonng the gate nto segments, such that each segment has almost constant stress, base on measure, stress-crtcal, layout parameters. e calculate the stress base moblty enhancement, n terms of moblty multplers, for each of these segments, an tae a weghte average of these multplers base on the slce wths to erve one moblty multpler for each evce. xperments base on rng oscllator frequency ata show that the moel accurately captures the varaton of layout epenent stress effect for a varety of layout permutatons. Propose moels are calbrate usng the frequency ata, an then use to prect the oscllaton frequency usng SPIC. he root mean square error n the precte rng oscllator frequency for the fferent sets of layout experments s less than %, verfyng the accuracy of the propose moels. he rest of the paper s organze as follows. Secton 2 scusses the ervaton of stress moels for the fferent stress nucng process steps, along wth the translaton of stress nto mpact on evce moblty. xpermental results are scusse n Secton, an Secton 4 conclues the paper. 2. MODING SSS NHANCD CAI MOBIIY For moel base smulaton of strane evces, we nee to calculate the mechancal stress nuce n the evce channel, an then translate the stress nto mpact on carrer moblty. hs mpact s quantfe n terms of moblty multplers, whch can then be use n crcut smulators such as SPIC to capture the stress effect. In ths secton, we frst present our close-form stress moels to enable fast an accurate stress moelng, an the secon part of the secton scusses translatng these stress numbers nto moblty multplers to calculate the mpact on performance an leaage by usng SPIC. 2. Stress Moels e evelop our stress moels by analyzng the physcs behn varous stress nucng process steps, an solvng relevant equatons. e analyze each source of stress separately, an a up the stress ue to each source, to obtan overall stress n the evce channel. nce the moels are base on the physcs behn each process step, they are scalable for future technology generatons. he sources of stress moele are: embee S/D layer (for PMOS evces, tensle/compressve ntre lners, an Shallow rench Isolaton (. he moels represent a very smple combnaton of transverse an longtunal recton D sprng approxmatons. he physcs base ervaton s one uner multple smplfyng assumptons an s suppose to prove a general form for the moel, whle the actual parameter values come from rgorous calbraton-optmzaton. For each evce, we conser all the features wthn a certan wnow of nfluence (of length, to calculate the resultng stress. 2.. mbee source/ran For PMOS evces, s eptaxally grown n cavtes that have been etche nto the source/ran areas [5]. A large compressve stress s create n the PMOS channel ue to lattce msmatch between an, thereby resultng n sgnfcant hole moblty mprovement. In ths process, NMOS s protecte by a cappng layer to prevent recess, an eptaxal growth. he ey to moelng the magntue of nuce stress s to entfy the physcs behn generaton of compressve stress, an solve relevant equatons by applyng smple sprng approxmatons. e assume that the wths of all structures are much bgger then ther lengths (quas D case. Bounary conton F Fg 2: Before expanson (top, after non-confne expanson (mle, an after eformaton of all segments ue to expanson (bottom. Fgure 2 shows a very smple layout use to explan the ervaton of D moels for compressve stress generate ue to embee. he layout s compose of two smple evces separate by, one wth embee n S/D regons (evce, an the other wthout t (evce. has a lattce constant larger than an hence t occupes more volume than woul occupy. he gray areas ( can be seen as tryng to expan n all the rectons. he scenaro after eptaxal growth of s epcte n the bottom pcture of Fgure 2. If χ s an atomc rato of n an Ω an Ω are the atomc volumes of an, respectvely, then t s easy to show that an ntal volume V (volume wthout ntroucton of n the S/D woul try to expan by Ω V χ, whch translates to a lnear V Ω expanson of Ω n all the three mensons. As F χ Ω shown n the mle pcture of Fgure 2, n the absence of any confnement (neghborng features, woul have expane by ths amount. he expansons for the left an rght regons can therefore be expresse as: Ω F χ F χ Ω Ω F Ω In realty, the presence of neghborng features opposes such an expanson, thereby creatng compressve stress n the evce channel. he eformaton of the sub-segment as compare to the non-confne case can be expresse as the fference between the non-confne an the actual confne case expanson. he bottom pcture n Fgure 2 shows the eformaton of fferent segments after expanson. e conser each layout segment as beng represente by a sprng (or an elastc beam characterze by fferent elastcty. It s assume that splacements at ens of the consere segment (leftmost an rghtmost eges are equal to zero. hs mght be treate as the symmetry bounary contons. At equlbrum, the forces actng from one subsegment on another at the ponts of contact are equal. It proves us, n the frame of the accepte approxmaton, wth the conton F F Bounary conton (
of equal stress along the entre lne of cross-secton. hs stress value wll epen on the layout composton n the regon of nterest. So, we can express the generate longtunal stress n fferent segments wth followng equatons. F F ( ( (2 Here, an are the elastcty constants of the -x x, slcon, an, varous an are the eformatons an nomnal mensons as shown n the fgure, an a s the stress generate n segment a ue to expanson. Usng the conton of equal stress, we can set up the system of equatons for etermnaton of unnown eformatons of the segments. he eformaton numbers for each segment can then be use to etermne the value of stress generate. Upon solvng these equatons, we obtan the longtunal stress n the channel: β ( ( ( β ( β Ω Ω χ In general, for any gven layout we can wrte the longtunal stress n a channel as: β n n negh ( ( BC BC ( β negh ( Here s the length of the -th -x x S/D segment on the same actve area as the evce whle negh an negh are the length of the neghborng actve areas. s the -th wth, n s the length of the n-th gate or non- source/ran (NMOS actve area n the longtunal recton. BC an BC are the bounary contons at the left an rght wnow eges representng stress-nuce ege splacements. In aton to the generaton of compressve longtunal stress ue to growth, transverse stran/stress s also generate because of tracton between channel segment an aacent structures. he expanson of these ran structures n transverse recton causes the aacent slcon (channel area to expan as well. hs s llustrate n Fgure. Hence, n orer to estmate nuce transverse stress n the evce channel, we nee to account for stress cause by the tracton wth aacent areas ue to expanson. he transversal stress can be calculate as (4 annel Orgnal borers Borers after eformaton Fg : Sample evce layout showng generaton of transverse stress β (5 2 β Here s the wth of the channel. an are the stress n aacent left an rght S/D -x x structures, whch can be calculate n a manner smlar to quaton 4 by replacng all (horzontal stances by (vertcal stances. Inexes an B are for top an bottom, respectvely. β ( negh B ( BC BC B (6 ( n negh ( B β n 2..2 Ntre ner Cappng stresse layer technology s one of the most mportant technques employe to generate a esrable stress n evce channel. ratonally, a slcon ntre base contact etch stop layer (CS s use as the source of the tensle stress. In ths technology, a x N y H z layer s eposte followe by a specal type of anneal to release hyrogen. hs results n volume shrnng, whch generates strong tensle stress n the surrounng confnement that gets transferre nto the channel regon of NMOS evces. In orer to avo tensle stress generaton n PMOS evces, fferent technologcal steps were ntrouce. he most effectve way was to ope the CS n the PMOS regons wth a mplant that results n volume expanson, an compressve stress generaton n the confnement []. atest hgh performance process noes have smultaneously ncorporate both tensle an compressve ntre lners nto a sngle hgh performance CMOS flow, calle the Dual Stress ner approach [6]. Nwell mas s generally use whle efnng the compressve an tensle regons an nwell eges can be seen as the nterface of compressve an tensle ntre. e efne α as the coeffcent of proportonalty between the asrawn length ( CS of a CS segment (stress effect s not accounte, an the confnement-free length ( * CS of the same segment f the ntre layer was allowe to expan/contract * wthout any confnement mpose by neghborng features: CS α. CS. Havng efne that, we can then procee to calculate the stress generate ue to ntre n a manner smlar to embee. he quas D approxmaton yels the followng expresson for cappng layer nuce longtunal stress as a functon of layout geometry. CS ( α CS ( BC BC CS Poly α CS (7
CS Poly N (DS nterface Poly CS Fg 4: Sample layout parameters for CS stress calculaton Here, C s the length of -th stress layer segment ether between two neghborng poly, or between poly an contact, or poly an borer of the chosen wnow, Poly s the length of the -th gate (channel length, an s the contact sze, all n the longtunal recton. mlar to the case, BC an BC are the bounary contons at the left an rght wnow eges representng stress-nuce ege splacements an CS, an are the elastcty constants of the cappng layer, slcon, an the contact materal, respectvely. In the absence of contacts, s taen as. Stress n the transverse recton can be obtane by replacng all the longtunal measurements wth transverse measurements an left an rght bounary contons wth the corresponng top an bottom lmts. he traverse stress can then be expresse as: CS ( α CS ( BC BC B CS Poly α CS Fgure 4 shows a set of relevant layout parameters for CS stress calculaton. As precte by the propose moel, the presence of polyslcon gates an contacts ecreases the stress ue to ntre lner by breang the contnuty of the eposte ntre lner layer. s create holes n the lner layer, whle polyslcon gates cause a bump n the eposte lner layer to brng own the stress. As a result, an solate evce wth no contacts wll have the hghest stress ue to ntre. hese effects are nclue n the moels expresse n quatons 7 an 8. 2.. Shallow rench Isolaton Shallow rench Isolaton ( creates stress ue to thermal msmatch between slcon an. he fference n the thermal expanson coeffcents causes compressve stresses to evelop n the evce once the wafer s coole own post annealng. e can quantfy the magntue of generate stress usng the expresson for lnear contracton that causes the stress to evelop. For a gven slcon segment, contracton upon coolng can be quantfe as: x, y ( α x, y (9 Here x,y s change n length upon coolng, α s the thermal expanson coeffcent of lcon, s the fference between the anneal temperature an the fnal temperature, an x,y s the asrawn length of the consere segment. hs s the contracton that woul occur n the absence of any confnement. e can then procee to calculate stress for a gven layout segment, by followng an approach smlar to that use for calculatng stress ue to, an ntre. he longtunal stress can be expresse as: (8 ( α α ( α ( BC ( α BC ( Here s the length of the -th segment, s the length of the -th slcon segment, α an α are the coeffcents of thermal expanson for slcon, an, respectvely. eplacng longtunal measurements by lateral (transverse measurements an left an rght bounary contons by top an bottom eges, we get the followng expresson for transverse stress: ( α α ( α ( BC ( α BC B ( It shoul be note that all the erve formulas whch escrbe the stress generate by fferent stress sources ((4, (6, (7, (8, (, ( contan the wnow ege splacements terms BC. hese splacements generally shoul be equal to zero, n accorance wth the assumpton of symmetry bounary conton. However, n some specfc cases, when the effect of global loa, such as pacagng, chp mountng or D ntegraton, on the varaton of transstor-to-transstor characterstcs s of nterest, these terms shoul come from the global fnte element base smulaton. Also note that these moels prove a general form for functons to estmate stress, the values for parameters such as, α, etc. are obtane by calbraton optmzaton an mght be fferent from the actual physcal values. 2.2 Convertng Stress to Moblty he layout epenence of process nuce stress leas to gates wth non unform stress, an, hence, non unform moblty, n the evce channel across the wth of the evce. Base on the close-form moels, we now the layout parameters that affect the stress nuce n the channel (such as number of contacts, stance of evce from well-ege, actve area length, etc.. hs nowlege can use to partton the evce gate nto segments, such that these stress-crtcal geometrcal parameters for a gven segment are constant throughout the segment wth. e can then calculate stress, an ts mpact on moblty, for each of these segments nepenently, an tae a weghte average of moblty multplers for fferent segments (base on segment wth, to etermne one sngle value of moblty multpler for the strane evce. Fgure 5 shows a sample evce layout (selecte from a larger MUX crcut layout parttone nto segments. For each segment, we can then procee to calculate stress ue to fferent sources, an sum t up to obtan the overall stress n each recton. However, n accorance wth Posson s ffect, layout generate longtunal stran also prouces a transverse stran whch s gven byε νε ; where ν s the Posson s factor, ε s the transverse stran, an ε s the longtunal stran. mlar relatonshp exsts for longtunal stress cause by layout generate transverse stress/stran. A complete stress strbuton n the -th segment can then be expresse as followng: ( tot ( tot ν ν (2 where, (tot an (tot are the total longtunal an the total transverse stress n the segment; an are the longtunal an transverse stress values calculate base on the moel, an ν s the Posson factor. As shown n Fgure 5, the longtunal stress s fferent for fferent segments of the evce base on the
Fg 5: MUX layout showng stress base parttonng of a ranom PMOS evce. longtunal layout parameters whle the traverse stress s same for the entre channel. Fnally, we use pezoresstve coeffcents to convert from stress to moblty [2]. Moblty multpler (µ mult for a gven segment s expresse as: μ ( tot ( tot μ mult π π ( μ Here, π an π are the longtunal an transverse pezoresstve coeffcents, respectvely. nce the pezoresstve coeffcents have a strong epenence on the opng concentratons [2], we assume that these coeffcents come from calbraton optmzaton as well. Fnally, we can tae a wth base weghte average of these multplers to obtan an overall evce moblty multpler, whch can then be use n a crcut smulator such as SPIC for accurate smulaton of strane evces.. XPIMNA SUS In orer to verfy the accuracy of propose stress moels, we use CAD smulaton base stress an on-current (I on ata for NMOS an PMOS evces n varous confguratons. e also valate our moels aganst rng oscllator frequency ata from an expermental test chp fabrcate n a process that contans both ntre lner an stress enhancement technques. he moels were separately calbrate for each case by settng up a system of equatons n terms of the unnown moel coeffcents (π, π, α, etc. usng measure layout parameters. e wrote a smple layout etor scrpt to measure layout stances, an segment the evce gate nto regons wth equal stress. As scusse n the prevous secton, ths segmentaton s one such that the stress-crtcal layout parameters such as actve area length, etc. are constant for each segment. SPIC base smulatons were use to generate tables for epenence of I on on moblty multplers. Fnally, MAAB coe base on least squares fttng s use to solve for moel coeffcents usng these equatons.. CAD xperments In ths set of experments we use a setup comprsng of suprem4 (for smulatng fabrcaton process to generate stress ata, an Davnc (for smulatng the on current values usng suprem4 generate stress ata to generate on current values for fferent layout confguratons of 65nm NMOS an PMOS evces. he CAD setup s accurately calbrate to the SPIC moels for the 65nm technology. Once calbrate, the moels are use to generate moblty multplers whch are then use n SPIC base smulaton of the evces, an the result s then compare to the CAD smulaton ata for each confguraton. e frst loo at the mpact of actve area length on evce stress. Actve area length s one of the most mportant layout parameters that mpacts channel stress qute sgnfcantly by ncreasng the regon aroun the channel(for PMOS. Fgure 6 shows the varaton of longtunal channel stress wth source/ran length ( s/ (normalze to mnmum value of s/ of an solate 65nm PMOS evce as smulate n suprem4 an Davnc CAD tool. Also shown n the fgure s the stress precte by the propose moel. Stress values are normalze to the value of stress at mnmum s/ for the technology. he fgure shows that ncreasng s/ ncreases stress n the channel an ths epenence s capture qute accurately by the propose stress moel. Next we focus on the CS stress an prect the CAD results wth the propose moel. he most crtcal layout parameter for CS s the stance to well ege whch serves as an nterface between the compressve an the tensle ntre lners. Fgure 7 shows CAD base smulaton for epenence of PMOS channel stress ue to ntre lner as a functon of stance from the well ege n the longtunal recton. As the stance from the well ege ncreases, so oes the compressve stress [7]. he stress values are normalze to the value at mnmum allowe stance from well ege for the 65nm technology. e then analyze on-current prectons for NMOS an PMOS obtane from CAD smulatons an the propose moels. For ths we generate a set of layout experments by varyng crtcal layout parameters. Dfferent combnatons of varous layout parameters, as shown n Fgure 8, are vare to generate several fferent experments. he frst few experments try to ncrease the stress base moblty by a combnaton of ncreasng the actve area length, movng the evce away from well ege (n the longtunal recton, sharng the actve area wth other evces, etc., whle the last few experments try to ecrease the stress base moblty by movng the evces closer to the well ege, ntroucng more contacts, an ecreasng actve area length. Fgure 9 shows the precte an smulate on current values (normalze to the on current for solate NMOS an PMOS evces wth one contact for varous CAD experments. he propose moel accurately prects the current values, an the S xx (normalze 2.2 2..8.6.4.2. mulaton Moel s/..2.4.6.8 2. 2.2 s/ (normalze Fg 6: ongtunal channel stress as a functon of actve area length as obtane by CAD smulatons an after propose moel fttng S xx (normalze.8 mulaton Moel.6.4.2. nwell 2 4 5 Dstance from well ege (normalze Fg 7: ongtunal channel stress as a functon of stance from well ege as obtane by CAD smulatons an after propose moel fttng
ensle lner ell ege Compressve lner e PMOS e ell ege ensle lner Fg 8: ayout permutatons n CAD experments for moel verfcaton Ion (normalze Ion (normalze.8.6.4.2..4.2. PMOS 2 4 6 8 xperments NMOS Precte mulate Precte mulate 2 4 6 8 xperments Fg 9: xpermental (CAD an precte on current values for NMOS an PMOS evces Frequency (normalze. xpermental.8 Precte.6.4.2..98.96 N ACIV CONAC 5 5 2 xperments Fg : xpermental (harware an precte rng oscllator frequences for fferent layout confguratons root mean square error n precte on current value s less than.8% for both PMOS an NMOS experments..2 Harware xperments In ths set of experments, the propose stress moels are calbrate an verfe usng rng oscllator frequency ata from an expermental test chp. he rng oscllator ata s measure an average over several es to reuce the mpact of ranom an e-to-e systematc varatons. For the purpose of calbraton, we assume that the frequency of oscllaton s rectly proportonal to average rve current for the rng oscllator, whch was confrme to be a val assumpton usng SPIC base smulatons of the rng oscllator crcut. Once calbrate, the moels are use to calculate mpact of stress n terms of moblty multplers for fferent rng oscllator layout confguratons. Fgure shows the comparson between the measure frequency ata an the precte frequency (normalze for varous layout experments. he plot s ve nto three stnct regons corresponng to three fferent set of layout confguratons consttutng the harware experments. In the nwell experments, we vary the stance between nwell ege an evce n both lateral an longtunal rectons. nce nwell mas s use to efne the nterface between compressve an tensle ntre lners, such changes have an mpact on longtunal an traverse stress ue to the ntre layer. In the secon set of experments, actve area layout an length was vare to change the amount of embee next to the channel (only for PMOS evces, an the stance between ege an gate. In the contact experments, we vare the number of contacts n the evces consttutng the rng oscllator. he plot shows that the moels exhbt a very goo ft to the harware ata wth the root mean square error between smulate an measure ata to be only.9%. 4. CONCUSION In ths wor, we propose compact, close-form moels for layout epenence of process nuce stress. e partton each evce channel nto segments wth equal stress n orer to calculate the mpact on moblty n terms of moblty multplers. e extensvely verfy our moels aganst harware an CAD smulaton ata for a large number of layout permutatons. he moels enable fast an accurate stress precton for a evce n a gven layout envronment. he root mean square error n the precte behavor s observe to be less than % for the fferent experments, thereby, verfyng the accuracy of the moels. eferences [] F. Anreu et al., xpermental an Comparatve Investgaton of ow an Hgh Fel ransport n Substrate- an Process- Inuce Strane Nanoscale MOSFs, Proc. VSI ech. Symp. ech. Dg., pp. 76-77, 25. [2] K. Mstry et al., Delayng Forever: Unaxal Strane lcon ransstors n a 9nm CMOS echnology," Proc. VSI ech. Symp. ech. Dg., pp. 5-5, 25. [] V. an et al., Stran for PMOS performance Improvement, Proc. CICC, pp. 667-674, 25. [4]. A. Banch et al., Accurate moelng of trench solaton nuce mechancal stress effects on MOSF electrcal performance, Proc. IDM, pp. 7-2, 22. [5] Z. uo et al., Desgn of hgh performance PFs wth strane channel an laser anneal, Proc. IDM, pp. 489-492, 25. [6] H. S. Yang et al., Dual stress lner for hgh performance sub - 45nm gate length SOI CMOS manufacturng, Proc. IDM, pp. 75-77, 24. [7] V. Josh et al., Stress Aware ayout Optmzaton, Proc. Internatonal Symposum on Physcal Desgn (ISPD, pp. 68-74, 28. [8] V. Moroz et al., he Impact of ayout on Stress-nhance ransstor Performance, Proc. SISPAD, pp. 4-46, 25. [9]. A. Banch et al., Accurate moelng of trench solaton nuce mechancal stress effects on MOSF electrcal performance, Proc. IDM, pp. 7-2, 22. [] M. V. Dunga et al., A Holstc Moel for Moblty nhancement through Process-Inuce Stress, Proc. I Conf. on lectron Devces an Sol-State Crcuts, pp. 4-46, 25. [] Shmzu et al., ocal mechancal-stress control (MC: a new technque for CMOS-performance enhancement, Proc. IDM, 2, pp. 4-46. [2] Y. Kana, A Graphcal epresentaton of the Pezoresstance Coeffcents n lcon, I ransactons on lectron Devces,. 29, No., 982, pp. 64-7.