Comp 2 Spring 25 2/ Lecture page Sequential Logic These must be the slings and arrows of outrageous fortune ) Synchronous as an implementation of Sequential 2) Synchronous Timing Analysis 3) Single synchronous clock design 4) Finite State Machines 5) Metastability L6 Synchronous Logic Road Traveled So Far Fets & voltages Logic gates circuits Sequential Logic Voltage-based encoding V OL, V IL, V IH, V OH contract: discrete-valued inputs complete in/out spec. static discipline t CD and t PD Acyclic connections Composable blocks Design: truth tables sum-of-products simplification muxes, ROMs, PLAs Storage & state Dynamic discipline Finite-state machines Metastability Throughput & latency Pipelining Our motto: Sweat the details once, and then put a box around it! L6 Synchronous Logic 2
Comp 2 Spring 25 2/ Lecture page 2 Something We Can t Build (Yet) What if you were given the following design specification: button When the button is pushed: ) Turn on the light if it is off 2) Turn off the light if it is on The light should change state within a second of the button press light What makes this circuit so different from those we ve discussed before?. State i.e. the circuit has memory 2. The output was changed by a input event (pushing a button) rather than an input value L6 Synchronous Logic 3 Sequential = Stateful Memory Device LOAD Current State Logic New State Input Output Plan: Build a Sequential Circuit with stored digital STATE Memory stores CURRENT state, produced at output Logic computes NEXT state (from input, current state) OUTPUT bit (from input, current state) State changes on LOAD control input Didn t we develop some memory devices last time? L6 Synchronous Logic 4
Comp 2 Spring 25 2/ Lecture page 3 Review of Flip Flop Timing <t PD D CLK D CLK >t CD D t PD : maximum propagation delay, CLK t CD : minimum contamination delay, CLK >t SETUP >t HOLD t SETUP : setup time guarantee that D has propagated through feedback path before master closes t HOLD : hold time guarantee master is closed and data is stable before allowing D to change L6 Synchronous Logic 5 Synchronous Timing Analysis reg reg2 uestions for register-based designs: How much time for useful work (i.e. for combinational delay)? CLK CLK t t 2 Does it help to guarantee a minimum t CD? How bout designing registers so that t CD,reg > t HOLD,reg? t = t CD,reg + t CD, > t HOLD,reg2 t 2 = t PD,reg + t PD, < t CLK -t SETUP,reg2 What happens if CLK signal doesn t arrive at the two registers at exactly the same time (a phenomenon known as clock skew )? Minimum Clock Period : t CLK >t PD,reg + t PD, + t SETUP,reg2 L6 Synchronous Logic 6
Comp 2 Spring 25 2/ Lecture page 4 Example: Flip Flop Timing start button button button Current state 3 t CD = ns t PD = 3ns t S = 2ns t H = 2ns t CD =? t PD = 5ns ROM 64x4 D clock unlock Next state 3 uestions:. t CD for the ROM? 2. Min. clock period? 3. Constraints on inputs? L6 Synchronous Logic 7 Single Synchronous Clock Sequential Synchronous However, Synchronous = A recipe for robust sequential circuits: No combinational cycles Only care about value of combinational circuits just before rising edge of clock Period greater than every combinational delay Change saved state after noise-inducing transitions have stopped! L6 Synchronous Logic 8
Comp 2 Spring 25 2/ Lecture page 5 Designing Sequential Logic We ll use sequential when we need to organize the solution to some design problem as a sequence of steps: How to open digital combination lock w/ 3 buttons ( start, and ): Step : press start button Step 2: press button Step 3: press button Step 4: press button Step 5: press button Information remembered between steps is called state. Might be just what step we re on, or might include results from earlier steps we ll need to complete a later step. L6 Synchronous Logic 9 Implementing a State Machine Current state start Next state unlock --- --- --- start start digit start error start start digit digit2 digit error digit digit digit2 digit3 digit3 unlock unlock error unlock error unlock unlock error --- --- error 6 different states encode using 3 bits L6 Synchronous Logic
Comp 2 Spring 25 2/ Lecture page 6 Now Do It With Hardware! start button button button Current state ROM 64x4 6 inputs 2 6 locations each location supplies 4 bits unlock Next state 3 3 D Trigger update periodically ( clock ) L6 Synchronous Logic Abstraction du jour: Finite State Machines m Clocked FSM n A FINITE STATE MACHINE has k STATES S... S k (one is "initial state) m INPUTS I... I m n OUTPUTS O... O n Transition Rules S'(s,i) for each state s and input i Output Rules Out(s) for each state s L6 Synchronous Logic 2
Comp 2 Spring 25 2/ Lecture page 7 Discrete State, Time inputs STATE s ROM NEXT s outputs Two design choices: () outputs only depend on state (Moore) (2) outputs depend on inputs + state (Mealy) s state bits 2 s possible states Clock STATE NEXT Clock Period Clock Period 2 Clock Period 3 Clock Period 4 Clock Period 5 L6 Synchronous Logic 3 State Transition Diagrams S S U= S S S S D U= D2 U= D3 U= U U=, A state transition diagram is an abstract graph representation of a state machine, where each state is represented as a node and each transition is represented as a as an arc. It represents the machine s behavior not its implementation. S E U= S NAME of state Heavy circle means INITIAL state = no buttons pressed OUTPUT when in this state (Moore) XXX U= INPUT causing transition L6 Synchronous Logic 4
Comp 2 Spring 25 2/ Lecture page 8 Valid State Diagrams S S S2 MOORE Machine: Outputs on States / S / / S / / S2 / MEALY Machine: Outputs on Transitions Arcs leaving a state must be: () mutually exclusive can t have two choices for a given input value (2) collectively exhaustive every state must specify what happens for each possible input combination. Nothing happens means arc back to itself. L6 Synchronous Logic 5 Let s Play State Machine Let s emulate the behavior specified by the state machine shown below when processing the following string from LSB to MSB. S S S2 39 = 2 State Input Next Output T= S S T= S S T=2 S S T=3 S S2 T=4 S2 S T=5 S S T=6 S S It looks to me like this machine outputs a whenever the bit sequence that it has seen thus far is a multiple of 3. L6 Synchronous Logic 6
Comp 2 Spring 25 2/ Lecture page 9 in/out S3 -/ Busted Stuff S / / S8 / S5 S6 / -/ / / S7 CONVENIENT NOTATION: When a transition is made on the next input regardless of its value the arc can be labeled with an X or - / / S9 / S2 / AMBIGOUS TRANSITIONS (Mutual Exclusive property violated): For each input there can only be one arc leaving a state UNSPECIFIED TRANSITIONS (Collectively Exhaustive property violated): There must be an arc leaving a state for all valid inputs (It can, however, loop back to the same state) / / / -/ S4 Can you spot the problems? input/output (Mealy) L6 Synchronous Logic 7 FSM Party Games. What can you say about the number of states? k ROM k 2. Same question: m States x y z n States 3. Here's an FSM. Can you discover its rules? L6 Synchronous Logic 8
Comp 2 Spring 25 2/ Lecture page What s My Transition Diagram? =OFF, =ON? vs. "" = Surprise! If you know NOTHING about the FSM, you re never sure! If you have a BOUND on the number of states, you can discover its behavior: K-state FSM: Every (reachable) state can be reached in < k steps. BUT... states may be equivalent! L6 Synchronous Logic 9 FSM Equivalence vs. ARE THEY DIFFERENT? NOT in any practical sense! They are EXTERNALLY INDISTINGUISHABLE, hence interchangeable. FSMs EUIVALENT iff every input sequence yields identical output sequences. ENGINEERING GOAL: HAVE an FSM which works... WANT simplest (ergo cheapest) equivalent FSM. L6 Synchronous Logic 2
Comp 2 Spring 25 2/ Lecture page Housekeeping issues. Initialization? Clear the memory? inputs STATE s That symbol doesn t register ROM or gates outputs NEXT s 2. Unused state encodings? - waste ROM (use PLA or gates) - meaning? 3. Synchronizing input changes with state update? 4. Choosing encoding for state? L6 Synchronous Logic 2 If we follow these simple rules Can we guarantee that our system will always work? In In Out Out Clk Clk Out Out With careful design we can make sure that the dynamic discipline is obeyed everywhere, except for the. L6 Synchronous Logic 22
Comp 2 Spring 25 2/ Lecture page 2 The world doesn t run on our clock! So, what happens if we miss an occasional set-up or hold time? D This is a transparent latch like one that you d find on the front end of an edge-triggered flip-flop Set-up time assures that this signal is stable before the clock transitions G Hold time assures that the data hangs around long enough so that these two paths don t disagree while latch switches to memory mode DG= Recall that the state of a flip-flop is held by a pair of inverters with feedback. G= L6 Synchronous Logic 23 Persistent invalid states One of the jobs of a digital gate is to restore questionable input signals to a valid output levels. V in V out V out VTC of inverter pair Latched in a state A question that arises sometimes: which valid level to restore to? Latched in an undefined state VTC of feedback path (V in =V out ) The only way this happens is if we allow an invalid level into our feedback loop. That only happens if we violate our set-up or hold times. Latched in a state V in L6 Synchronous Logic 24
Comp 2 Spring 25 2/ Lecture page 3 Metastability Metastability is the occurrence of a persistent invalid output. An unstable equilibria. The idea of Metastability is not new: Didn t I learn about this in Comp 2? The Paradox of Buridan s Ass Buridan, Jean (3-58), French Scholastic philosopher, who held a theory of determinism, contending that the will must choose the greater good. Born in Bethune, he was educated at the University of Paris, where he studied with the English Scholastic philosopher William of Ockham (whom you might recall from his razor business). After his studies were completed, he was appointed professor of philosophy, and later rector, at the same university. Buridan is traditionally, but probably incorrectly, associated with a philosophical dilemma of moral choice called "Buridan's ass. In the problem an ass starves to death between two alluring bundles of hay because it does not have the will to decide which one to eat. L6 Synchronous Logic 25 Real-World Metastability If we launch a ball up a hill we expect one of 3 possible outcomes: State A a) Goes over b) Rolls back c) Stalls at the apex State A State C State B That last outcome is not very stable. -a gust of wind -Brownian motion - it doesn t take much L6 Synchronous Logic 26
Comp 2 Spring 25 2/ Lecture page 4 How do balls relate to digital? V out Our hill is simply the derivative of the VTC. V V out in V in Notice that the higher the gain thru the transition region, the steeper the peak of the hill. Thus, making it harder to get into a metastable state. Nonetheless, Metastability will happen! L6 Synchronous Logic 27 Observed Behavior: typical metastable symptoms Following a clock edge on an asynchronous input: CLK D We may see exponentially-distributed metastable intervals: Or periods of high-frequency oscillation (if the feedback path is long): L6 Synchronous Logic 28
Comp 2 Spring 25 2/ Lecture page 5 Avoiding Metastability Synchronizers, extra flip flops between the asynchronous input and your, are the best insurance against metastable states. The higher the clock rate, the more synchronizers should be considered. In Clk A metastable state here will probably resolve itself to a valid level before it gets into my circuit. Out And one here will almost certainly get resolved. In Out Clk L6 Synchronous Logic 29 Summary Dynamic discipline (setup and hold times) Sequential = combinational + memory New abstraction: Finite State Machines (FSMs) transition diagrams showing states, outputs, and transition arcs: mutually exclusive, collectively exhaustive Metastability Synchronous admits the possibility of a persistent invalid state This state will eventually resolve to a valid state, but it could take an arbitrarily long time By using synchronizer Flip Flops on all potentially asynchronous inputs we can reduce probability of admitting an invalid value into our system to a frequency longer than the product s lifespan. L6 Synchronous Logic 3