Chapter 4: Designing Combinational Systems Uchechukwu Ofoegbu

Chapter 4: Designing Combinational Systems Uchechukwu Ofoegbu Temple University

Gate Delay ((1.1).1) ((1.0).0) ((0.1).1) ((0.1).0) ((1.1) = 1 0

s = sum c out carry-out a, b = added bits C = carry in a b c c out s 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 One-bit Carry Ripple Adder 1 0 0 0 1 15 2 three-input two-input 0 1 NAND, 1 3 0 two-input NAND, four- 11 two-input XOR, NAND, 3 two-input three NANDs, not gates, 1 three- input NAND, and three not gates if 1 complemented 1 0 1 input inputs 0 OR are not available 1 1 1 1 1 S = a b c+a bc +ab c +abc c out = a bc+ab c+abc +abc = bc+ac+ab S = c(a b +ab)+c (ab +a b) c out = c (a+b)+ab S = c(aφb) +c (aφb) = c Φ(aΦb) Xor can be replaced with 4 two input NAND gates c out = c(aφb)+ab

One-bit Full Binary Adder Gate implementation for the One-bit Full Adder n-bit ripple-carry binary adder Worst case propagation delay 2n time units; Gate delay=1

Gate Delay through a 1-bit Adder Copyright 2008 The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

Gate Delay through an n-bit Adder 1. Delay from inputs to c out + 2. (n-2)*delay from c in + to c out in to 3. Max(delay from c in to c out or c in to s) For the multilevel adder: 5 + 2(n-2) 2) + 3 Total delay does = (2n+4) not have to be so long!! What is the delay for a 64 bit adder?

Gate Delay Improvements SOP minimization for two-bit adders Complex equations Fan-in limitations With a maximum fan-in of 7, adding n-bit would have a total delay of (n+1) Four-bit adders 7483, 7483A, 74283 differ only in pin connections Produces the sum with four-level inputs Uses combination of NAND, NOR, AND, NOT and XOR gates Delay from c in to c out = 3 3 Total delay = of (3/4 n+1) 4-bit adders are cascaded for larger adders

One-bit Full Binary Adder a b c s Gate implementation for the One-bit Full Adder C out n-bit ripple-carry binary adder Worst case propagation delay 2n time units; Gate delay=1

Gate Delay Improvements Copyright 2008 The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

Carry-Look-Ahead Adder Carry generate signal (g) is 1 if that stage of the adder has a carryout of 1 whether or not there was a carry-in Carry propagate signal (p) is 1 if that stage of the adder has a carryout of 1 if he carry-in is 1 Both g and p can be generated for all n bits in 1 gate delay. The carry out is 1 if the last bit generated a carry, or if it propagated a carry and the stage below it generated one. All the carries can be generated in 2 additional delays after g and p are available, independent of n. All sums can be generated in 4, independent of n. Gate Delay Improvements

One-bit Full Binary Subtractor/Adder Subtract y from x, with a borrow-in from the previous bit position, b in d: difference b out : borrow-out x y b in b out d 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 b = xy + xb + out yb in d = bin ( x y)

Organization of a 1-bit comparator Compares two numbers to determine if A is less than B A is equal to B A if greater than B Can be extended to any bit size

Truth Table for Simple 1-bit 1 Comparator A 2 B 2 A 1 B 1 Y: A=B 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1. In groups, come up with a minimum SOP expression for this simple comparator. Assume all inputs are available in both complimented and uncomplemented versions, design a logic circuit for your algebraic expression What is the minimum delay for your design

1 3 5 Group Work Homework: 2, 4, 7,

Binary Decoders Selects one of several outputs when activated n-bit binary number results in 2 n output lines

Binary Decoders Selected output is high

Binary Decoders Selected output is low

Binary Decoders Selected output is high only when Enable bit is high or Enable Prime is low

Binary Decoders Active Low and three enable bits Active when ALL THREE enable bits are active

Binary Decoders Copyright 2008 The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

Exact Opposite of a binary decoder Binary Encoders Used to select a device from several possible What is the difference devices between Device A 0 If only one of the inputs can and be when 1, then there is the no truth device signaling? table for a 4-2 encoder is: A 0 A 1 A 2 A 3 z 0 z 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 1 1 1 Z 0 =A 2 +A 3 Z 1 =A 1 +A 3

Priority Encoders NR= AAAAAAAA 0 1 2 3 4 5 6 7 Z = A + A + A + A 0 4 5 6 7 Z = A + A + ( A + A ) A A 1 6 7 2 3 4 5 Z = A + A A + A A A + AA A A 2 7 5 6 3 4 6 1 2 4 6

Multiplexers A switch that is used to pass one input as a function of select inputs

Multiplexers

Group Work 10 assume you have 4-input NAND also available 13*

Programmable Logic Devices Also known as gate arrays Involves gate diagrams combinational circuits with lines for all possible connection

Programmable Logic Devices - Illustration Base array is manufactured first Each connection is added when needed based on user specifications

Programmable Logic Devices - Illustration Field Programmable Gate Arrays (FPGAs( FPGAs) A fuse in connected in the midst of each connection line If the connection is not wanted, the fuse is blown

Programmable Logic Devices - Illustration Field Programmable Gate Arrays (FPGAs( FPGAs) (a) Unprogrammed and-gate. (b) Unprogrammed or-gate. (c) Programmed and-gate realizing the term ac. (d) Programmed or-gate realizing the term a + b. (e) Special notation for an andgate having all its input fuses intact. (f) Special notation for an or-gate having all its input fuses intact. (g) And-gate with nonfusible inputs. (h) Or-gate with nonfusible inputs.

Programmable ROMs You only need a list of minterms One AND gate for each minterm Appropriate minterm gates are connected to each output W(A, B, C, D) = Σm(3, 7, 8, 9, 11, 15) X(A, B, C, D) = Σm(3, 4, 5, 7, 10, 14, 15) Y(A, B, C, D) = Σm(1, 5, 7, 11, 15)

Programmable Logic Arrays - PLAs You only need SOP expressions Main concern is the number of AND gates available You may use just a sum of minterms, or minimize each function or maximize charing W = AB C + A CD + ACD X = A BC + ACD + A CD + BCD Y = A C D + ACD + BCD 7 terms W = AB C + CD X = A BC + ACD + A CD + (BCD or ABC) Y = A C D + ACD + (BCD or A BD) 8 or 9 terms depending on if we choose BCD

Programmable Array Logic - PAL Each output comes from an OR gate that has its own group of AND gates W = AB C + CD Y = A BC + A CD + ACD + {BCD or ABC} Z = A C D + ACD + {A BD or BCD}

Group Work 14d ROM

Group Work 14d PLA F = A' B' C' D + A' C D' + A' B C + A C' D' + A C' D G = A' B' C' D + A B' + A C' D + A C D H = A' B' C' D + B C + A C' D' + A C D

Group Work 14d PLA

Group Work PAL