DIGITAL LOGIC DESIGN

DIGITAL LOGIC DESIGN

NUMBERS SYSTEMS AND CODES

Any number in one base system can be converted into another base system Types 1) decimal to any base 2) Any base to decimal 3) Any base to Any base

Complements arc used in digital computers to simplify the subtraction operation and for log- ical manipulation They are two types of complements 1) Diminished radix complement (r n - 1)-N {r is the base of num system} 2) Radix Complement (r n - 1)-N+1

If the base = 10 The 9's complement of 546700 is 999999-546700 = 453299. If the base = 2 The 1's complemcnt of 1011000 is 0100111.

the 10's complement of 012398 is 987602 the 1's complement of 1101100 is 0010100

Discard end carry for r s complement Using 10's complement subtract 72532-3250. M = 72532 10's complement of N = + 96750 Sum = 169282 Discard end carry for 10 s complement Answer = 69282

X - Y = 1010100-1000011 X = 1010100 1's comp of Y =+ 0111100 Sum = 1 0010000 Add End-around carry = + 1 X - Y = 0010001 1

No communication channel or storage device is completely error-free As the number of bits per area or the transmission rate increases, more errors occur. Impossible to detect or correct 100% of the errors

- 3 Types of Error Detection/Correction Methods - Cyclic Redundancy Check (CRC) - Hamming Codes - Reed-Solomon (RS) 10011001011 = 1001100 + 1011 ^ ^ ^ Code word information error-checking bits/ bits parity bits/ syndrome/ redundant bits

One of the most effective codes for errorrecovery Used in situations where random errors are likely to occur Error detection and correction increases in proportion to the number of parity bits (errorchecking bits) added to the end of the information bits code word = information bits + parity bits Hamming distance: the number of bit positions in which two code words differ. 10001001 10110001 * * * Minimum Hamming distance or D(min) : determines its error detecting and correcting capability. Hamming codes can always detect D(min) 1 errors, but can only correct half of those errors.

EX. Data Parity Code Bits Bit Word 00 0 000 01 1 011 10 1 101 11 0 110 000* 100 001 101* 010 110* 011* 111

- Single parity bit can only detect error, not correct it - Error-correcting codes require more than a single parity bit EX. 0 0 0 0 0 0 1 0 1 1 1 0 1 1 0 1 1 1 0 1 Minimum Hamming distance = 3 Can detect up to 2 errors and correct 1 error

1. Let the information byte F = 1001011 2. The sender and receiver agree on an arbitrary binary pattern P. Let P = 1011. 3. Shift F to the left by 1 less than the number of bits in P. Now, F = 1001011000. 4. Let F be the dividend and P be the divisor. Perform modulo 2 division. 5. After performing the division, we ignore the quotient. We got 100 for the remainder, which becomes the actual CRC checksum. 6. Add the remainder to F, giving the message M: 1001011 + 100 = 1001011100 = M

7. M is decoded and checked by the message receiver using the reverse process. 1010100 1011 1001011100 1011 001001 1001 0010 001011 1011 0000 Remainder

We need to consider formal techniques for the simplification of Boolean functions. Identical functions will have exactly the same canonical form. Minterms and Maxterms Sum-of-Minterms and Product-of- Maxterms Product and Sum terms Sum-of-Products (SOP) and Product-of-Sums (POS)

Literal: A variable or its complement Product term: literals connected by Sum term: literals connected by + Minterm: a product term in which all the variables appear exactly once, either complemented or uncomplemented Maxterm: a sum term in which all the variables appear exactly once, either complemented or uncomplemented

Any Boolean function F( ) can be expressed as a unique sum of minterms and a unique product of maxterms (under a fixed variable ordering). In other words, every function F() has two canonical forms: Canonical Sum-Of-Products (sum of minterms) Canonical Product-Of-Sums (product of maxterms)

Canonical Sum-Of-Products: The minterms included are those m j such that F( ) = 1 in row j of the truth table for F( ). Canonical Product-Of-Sums: The maxterms included are those M j such that F( ) = 0 in row j of the truth table for F( ).

Replace with (or vice versa) and replace those j s that appeared in the original form with those that do not. Example: f 1 (a,b,c) = a b c + a bc + ab c + abc = m 1 + m 2 + m 4 + m 6 = (1,2,4,6) = (0,3,5,7) = (a+b+c) (a+b +c ) (a +b+c ) (a +b +c )

Expand non-canonical terms by inserting equivalent of 1 in each missing variable x: (x + x ) = 1 Remove duplicate minterms f 1 (a,b,c) = a b c + bc + ac = a b c + (a+a )bc + a(b+b )c = a b c + abc + a bc + abc + ab c = a b c + abc + a bc + ab c

Expand noncanonical terms by adding 0 in terms of missing variables (e.g., xx = 0) and using the distributive law Remove duplicate maxterms f 1 (a,b,c) = (a+b+c) (b +c ) (a +c ) = (a+b+c) (aa +b +c ) (a +bb +c ) = (a+b+c) (a+b +c ) (a +b +c ) (a +b+c ) (a +b +c ) = (a+b+c) (a+b +c ) (a +b +c ) (a +b+c )

Formal logic: In formal logic, a statement (proposition) is a declarative sentence that is either true(1) or false (0). It is easier to communicate with computers using formal logic. Boolean variable: Takes only two values either true (1) or false (0). They are used as basic units of formal logic.

Boolean function: Mapping from Boolean variables to a Boolean value. Truth table: Represents relationship between a Boolean function and its binary variables. It enumerates all possible combinations of arguments and the corresponding function values.

Boolean algebra: Deals with binary variables and logic operations operating on those variables. Logic diagram: Composed of graphic symbols for logic gates. A simple circuit sketch that represents inputs and outputs of Boolean functions.

Refer to the hardware to implement Boolean operators. The most basic gates are

Postulate 1 (Definition): A Boolean algebra is a closed algebraic system containing a set K of two or more elements and the two operators and + which refer to logical AND and logical OR

(1) x + 0 = x (2) x 0 = 0 (3) x + 1 = 1 (4) x 1 = 1 (5) x + x = x (6) x x = x (7) x + x = x (8) x x = 0

(9) x + y = y + x (10) xy = yx (11) x + ( y + z ) = ( x + y ) + z (12) x (yz) = (xy) z (13) x ( y + z ) = xy + xz (14) x + yz = ( x + y )( x + z) (15) ( x + y ) = x y (16) ( xy ) = x + y (17) (x ) = x

Examples: (a) a + ab = a(1+b)=a (b) a(a + b) = a.a +ab=a+ab=a(1+b)=a. (c) a + a'b = (a + a')(a + b)=1(a + b) =a+b (d) a(a' + b) = a. a' +ab=0+ab=ab

(a) (a + b)' = a'b' (b) (ab)' = a' + b' Generalized DeMorgan's Theorem (a) (a + b + z)' = a'b' z' (b) (a.b z)' = a' + b' + z

F = ab + c d F =?? F = ab + c d + b d F =??

Show that: (a(b + z(x + a')))' =a' + b' (z' + x') (a(b + z(x + a')))' = a' + (b + z(x + a'))' = a' + b' (z(x + a'))' = a' + b' (z' + (x + a')') = a' + b' (z' + x'(a')') = a' + b' (z' + x'a) =a +b' z' + b'x'a =(a + b'x'a) + b' z' =(a + b'x )(a +a ) + b' z' = a + b'x + b' z = a' + b' (z' + x')

NAND-AND AND-NOR NOR-OR OR-NAND

The objectives of this lesson are to learn about: 1. Universal gates - NAND and NOR. 2. How to implement NOT, AND, and OR gate using NAND gates only. 3. How to implement NOT, AND, and OR gate using NOR gates only. 4. Equivalent gates.

BCD is a code for the decimal digits 0-9 Excess-3 is also a code for the decimal digits

Inputs: a BCD input, A,B,C,D with A as the most significant bit and D as the least significant bit. Outputs: an Excess-3 output W,X,Y,Z that corresponds to the BCD input. Internal operation circuit to do the conversion in combinational logic.

Excess-3 code is easily formed by adding a binary 3 to the binary or BCD for the digit. There are 16 possible inputs for both BCD and Excess-3. It can be assumed that only valid BCD inputs will appear so the six combinations not used can be treated as don t cares.

Lay out K-maps for each output, W X Y Z A step in the digital circuit design process.

Where are the Minterms located on a K-Map?

W(A,B,C,D) = Σm(5,6,7,8,9) +d(10,11,12,13,14,15) X(A,B,C,D) = Σm(1,2,3,4,9) +d(10,11,12,13,14,15) Y(A,B,C,D) = Σm(0,3,4,7,8) +d(10,11,12,13,14,15) Z(A,B,C,D) = Σm(0,2,4,6,8) +d(10,11,12,13,14,15)

W minimization Find W = A + BC + BD

X minimization Find X = BC D +B C+B D

Y minimization Find Y = CD + C D

Z minimization Find Z = D

Specification Digital readouts on many digital products often use LED seven-segment displays. Each digit is created by lighting the appropriate segments. The segments are labeled a,b,c,d,e,f,g The decoder takes a BCD input and outputs the correct code for the seven-segment display.

Input: A 4-bit binary value that is a BCD coded input. Outputs: 7 bits, a through g for each of the segments of the display. Operation: Decode the input to activate the correct segments.

Construct a truth table

Create a K-map for each output and get A = A C+A BD+B C D +AB C B = A B +A C D +A CD+AB C C = A B+A D+B C D +AB C D = A CD +A B C+B C D +AB C +A BC D E = A CD +B C D F = A BC +A C D +A BD +AB C G = A CD +A B C+A BC +AB C

Karnaugh Maps for Simplification 76

Boolean algebra helps us simplify expressions and circuits Karnaugh Map: A graphical technique for simplifying a Boolean expression into either form: minimal sum of products (MSP) minimal product of sums (MPS) Goal of the simplification. There are a minimal number of product/sum terms Each term has a minimal number of literals Circuit-wise, this leads to a minimal two-level implementation 77

A two-variable function has four possible minterms. We can rearrange these minterms into a Karnaugh map x y minterm 0 0 x y 0 1 x y 1 0 xy 1 1 xy X Y 0 1 0 x y x y 1 xy xy Now we can easily see which minterms contain common literals Minterms on the left and right sides contain y and y respectively Minterms in the top and bottom rows contain x and x respectively X Y 0 1 0 x y x y 1 xy xy Y Y X x y x y X xy xy 78

Imagine a two-variable sum of minterms: x y + x y Both of these Minterms appear in the top row of a Karnaugh map, which means that they both contain the literal x x y Y x y X xy xy x y + x y = x (y + y) [ Distributive ] = x 1 [ y + y = 1 ] = x [ x 1 = x ] What happens if you simplify this expression using Boolean algebra? 79

Another example expression is x y + xy Both minterms appear in the right side, where y is uncomplemented Thus, we can reduce x y + xy to just y x y Y x y X xy xy How about x y + x y + xy? We have x y + x y in the top row, corresponding to x There s also x y + xy in the right side, corresponding to y This whole expression can be reduced to x + y x y Y x y X xy xy 80

For a three-variable expression with inputs x, y, z, the arrangement of minterms is more tricky: YZ 00 01 11 10 0 x y z x y z x yz x yz X 1 xy z xy z xyz xyz Y x y z x y z x yz x yz X xy z xy z xyz xyz Z YZ 00 01 11 10 0 m 0 m 1 m 3 m 2 X 1 m4 m 5 m 7 m 6 Another way to label the K-map (use whichever you like): Y m 0 m 1 m 3 m 2 X m 4 m 5 m 7 m 6 Z 81

With this ordering, any group of 2, 4 or 8 adjacent squares on the map contains common literals that can be factored out Y x y z x y z x yz x yz X xy z xy z xyz xyz Z x y z + x yz = x z(y + y) = x z 1 = x z Adjacency includes wrapping around the left and right sides: Y x y z + xy z + x yz + xyz = z (x y + xy + x y + xy) x y z x y z x yz x yz = z (y (x + x) + y(x + x)) X xy z xy z xyz xyz = z (y +y) Z = z We ll use this property of adjacent squares to do our simplifications. 82

We can fill in the K-map directly from a truth table The output in row i of the table goes into square m i of the K-map Remember that the rightmost columns of the K-map are switched x y z f(x,y,z) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 Y 0 1 0 0 X 0 1 1 1 Z Y m 0 m 1 m 3 m 2 X m 4 m 5 m 7 m 6 Z 83

You can find the minimal SoP expression Each rectangle corresponds to one product term The product is determined by finding the common literals in that rectangle Y Y 0 1 0 0 X 0 1 1 1 Z x y z x y z x yz x yz X xy z xy z xyz xyz Z y z xy F(x,y,z)= y z + xy 84

The most difficult step is grouping together all the 1s in the K-map Make rectangles around groups of one, two, four or eight 1s All of the 1s in the map should be included in at least one rectangle Do not include any of the 0s Each group corresponds to one product term Y 0 1 0 0 X 0 1 1 1 Z 85

Make as few rectangles as possible, to minimize the number of products in the final expression. Make each rectangle as large as possible, to minimize the number of literals in each term. Rectangles can be overlapped, if that makes them larger. 86

Let s consider simplifying f(x,y,z) = xy + y z + xz You should convert the expression into a sum of minterms form, The easiest way to do this is to make a truth table for the function, and then read off the minterms You can either write out the literals or use the minterm shorthand Here is the truth table and sum of minterms for our example: x y z f(x,y,z) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 f(x,y,z) = x y z + xy z + xyz + xyz = m 1 + m 5 + m 6 + m 7 87

You can also convert the expression to a sum of minterms with Boolean algebra Apply the distributive law in reverse to add in missing variables. Very few people actually do this, but it s occasionally useful. xy + y z + xz = (xy 1) + (y z 1) + (xz 1) = (xy (z + z)) + (y z (x + x)) + (xz (y + y)) = (xyz + xyz) + (x y z + xy z) + (xy z + xyz) = xyz + xyz + x y z + xy z = m 1 + m 5 + m 6 + m 7 expression The resulting expression is larger than the original one! But having all the individual minterms makes it easy to combine them together with the K-map In both cases, we re actually unsimplifying our example 88

In our example, we can write f(x,y,z) in two equivalent ways f(x,y,z) = x y z + xy z + xyz + xyz Y x y z x y z x yz x yz X xy z xy z xyz xyz Z f(x,y,z) = m 1 + m 5 + m 6 + m 7 In either case, the resulting K-map is shown below Y m 0 m 1 m 3 m 2 X m 4 m 5 m 7 m 6 Z Y 0 1 0 0 X 0 1 1 1 Z 89

Simplify the sum of minterms m 1 + m 3 + m 5 + m 6 Y X Z Y m 0 m 1 m 3 m 2 X m 4 m 5 m 7 m 6 Z 90

Here is the filled in K-map, with all groups shown The magenta and green groups overlap, which makes each of them as large as possible Minterm m 6 is in a group all by its lonesome The final MSP here is x z + y z + xyz Y 0 1 1 0 X 0 1 0 1 Z 91

There may not necessarily be a unique MSP. The K-map below yields two valid and equivalent MSPs, because there are two possible ways to include minterm m 7 Y 0 1 0 1 X 0 1 1 1 Z Y 0 1 0 1 X 0 1 1 1 Z y z + yz + xy Y 0 1 0 1 X 0 1 1 1 Z y z + yz + xz Remember that overlapping groups is possible, as shown above 92

We can do four-variable expressions too! The minterms in the third and fourth columns, and in the third and fourth rows, are switched around. Again, this ensures that adjacent squares have common literals Grouping minterms is similar to the three-variable case, but: You can have rectangular groups of 1, 2, 4, 8 or 16 minterms You can wrap around all four sides 93

Y w x y z w x y z w x yz w x yz w xy z w xy z w xyz w xyz W wxy z wxy z wxyz wxyz wx y z wx y z wx yz wx yz Z X Y m 0 m 1 m 3 m 2 m 4 m 5 m 7 m 6 m 12 m 13 m 15 m 14 X W m8 m 9 m 11 m 10 Z 94

The expression is already a sum of minterms, so here s the K-map: Y 1 0 0 1 0 1 0 0 0 1 0 0 X W 1 0 0 1 Y m 0 m 1 m 3 m 2 m 4 m 5 m 7 m 6 m 12 m 13 m 15 m 14 X W m8 m 9 m 11 m 10 Z Z We can make the following groups, resulting in the MSP x z + xy z Y 1 0 0 1 0 1 0 0 0 1 0 0 X W 1 0 0 1 Z w x y z w x y z w x yz w x yz w xy z w xy z w xyz w xyz wxy z wxy z wxyz wxyz W wx y z wx y z wx yz wx yz Z Y X 95

W V= 0 V= 1Y Y m 16 m 17 m 19 m 8 m 20 m 21 m 23 m 22 X X m 28 m 29 m 31 m W 30 m24 m 25 m 27 m 26 Z m 0 m 1 m 3 m 2 m 4 m 5 m 7 m 6 m 12 m 13 m 15 m 14 m 8 m 9 m 11 m 10 Z 96

1 1 1 1 1 1 1 1 1 1 1 1 1 1 V= 0 V= 1 f = XZ Σm(4,6,12,14,20,22,28,30) + V W Y Σm(0,1,4,5) + W Y Z Σm(0,4,16,20) + VWXY Σm(30,31) + V WX YZ m11 97

Maxterms are grouped to find minimal PoS expression yz 00 01 11 10 x 0 1 x +y+z x+y+z x+y +z x+y +z x +y+z x +y+z x +y +z x +y +z 98

F(W,X,Y,Z)= M(0,1,2,4,5) x 0 1 x +y+z x+y+z x+y +z x+y +z x +y+z x +y+z yz 00 01 x +y +z 11 x +y +z 10 F(W,X,Y,Z)= Y. (X + Z) x 0 1 0 0 1 yz 0 00 01 11 100 0 1 1 99

F(W,X,Y,Z)= Σm(0,1,2,5,8,9,10) = M(3,4,6,7,11,12,13,14,15) 0 0 0 0 0 0 0 0 0 F(W,X,Y,Z)= (W + X )(Y + Z )(X + Z) Or, F(W,X,Y,Z)= X Y + X Z + W Y Z Which one is the minimal one? 10 0

F(W,X,Y,Z)= M(0,2,3,4,5,6) = Σm(1,7,8,9,10,11,12,13,14,15) 1 1 F(W,X,Y,Z)= W + XYZ + X Y Z 1 1 1 1 1 1 1 1 10 1

You don t always need all 2 n input combinations in an n-variable function If you can guarantee that certain input combinations never occur If some outputs aren t used in the rest of the circuit We mark don t-care outputs in truth tables and K-maps with Xs. x y z f(x,y,z) 0 0 0 0 0 0 1 1 0 1 0 X 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 X 1 1 1 1 Within a K-map, each X can be considered as either 0 or 1. You should pick the interpretation that allows for the most simplification. 10 2

Find a MSP for f(w,x,y,z) = m(0,2,4,5,8,14,15), d(w,x,y,z) = m(7,10,13) This notation means that input combinations wxyz = 0111, 1010 and 1101 (corresponding to minterms m 7, m 10 and m 13 ) are unused. Y 1 0 0 1 1 1 x 0 X 0 x 1 1 W 1 0 0 x Z 10 3

Find a MSP for: f(w,x,y,z) = m(0,2,4,5,8,14,15), d(w,x,y,z) = m(7,10,13) Y 1 1 1 1 x x 1 1 X W 1 x Z f(w,x,y,z)= x z + w xy + wxy 10 4

K-maps are an alternative to algebra for simplifying expressions The result is a MSP/MPS, which leads to a minimal two-level circuit It s easy to handle don t-care conditions K-maps are really only good for manual simplification of small expressions... Things to keep in mind: Remember the correct order of minterms/maxterms on the K-map When grouping, you can wrap around all sides of the K-map, and your groups can overlap Make as few rectangles as possible, but make each of them as large as possible. This leads to fewer, but simpler, product terms There may be more than one valid solution 10 5

UNIT 3

A process with 5 steps Specification Formulation Optimization Technology mapping Verification 1 st three steps and last best illustrated by example

Fundamental circuits that are the base building blocks of most larger digital circuits They are reusable and are common to many systems. Examples of functional logic circuits Decoders Encoders Code converters Multiplexers

Multiplexers Selectors for routing data to the processor, memory, I/O Multiplexers route the data to the correct bus or port. Decoders are used for selecting things like a bank of memory and then the address within the bank. This is also the function needed to decode the instruction to determine the operation to perform. Encoders are used in various components such as keyboards.

DESIGN OF SEQUENTIAL CIRCUITS

In this chapter you will learn about: Logic circuits that can store information Flip-flops, which store a single bit Registers, which store multiple bits Shift registers, which shift the contents of a register Counters of various types

Sensor Reset Set Memory element On Off Alarm Alarm turned on when On/Off = 1 Alarm turned off when On/Off = 0 Once triggered, alarm stays on until manually reset The circuit requires a memory element

Basic latch is a feedback connection of two NOR gates or two NAND gates It can store one bit of information It can be set to 1 using the S input and reset to 0 using the R input.

A B A feedback loop with even number of inverters If A = 0, B = 1 or when A = 1, B = 0 This circuit is not useful due to the lack of a mechanism for changing its state

Reset Set Q

Gated latch is a basic latch that includes input gating and a control signal The latch retains its existing state when the control input is equal to 0 Its state may be changed when the control signal is equal to 1. In our discussion we referred to the control input as the clock We consider two types of gated latches: Gated SR latch uses the S and R inputs to set the latch to 1 or reset it to 0, respectively. Gated D latch uses the D input to force the latch into a state that has the same logic value as the D input.

Setup Time t su The minimum time that the input signal must be stable prior to the edge of the clock signal. Hold Time t h The minimum time that the input signal must be stable after the edge of the clock signal. t su t h Clk D Q

A flip-flop is a storage element based on the gated latch principle It can have its output state changed only on the edge of the controlling clock signal

We consider two types: Edge-triggered flip-flop is affected only by the input values present when the active edge of the clock occurs Master-slave flip-flop is built with two gated latches The master stage is active during half of the clock cycle, and the slave stage is active during the other half. The output value of the flip-flop changes on the edge of the clock that activates the transfer into the slave stage.

D Master D Q Q m Slave D Q Q s Q Clock Clk Q Clk Q Q (a) Circuit Clock D Q m Q = Q s (b) Timing diagram D Q Q (c) Graphical symbol

D Q Clock Q Graphical symbol

Comparison of Level-Sensitive and Edge-Triggered D Storage Elements

SR flip-flop (Set, Reset) T flip-flop (Toggle) D flip-flop (Delay) JK flip-flop

Previous State -> Present State S R 0 -> 0 0 X 0 -> 1 1 0 1 -> 0 0 1 1 -> 1 X 0 Previous State -> Present State T 0 -> 0 0 0 -> 1 1 1 -> 0 1 1 -> 1 0

Previous State -> Present State D 0 -> 0 0 0 -> 1 1 1 -> 0 0 1 -> 1 1 Previous State -> Present State J K 0 -> 0 0 X 0 -> 1 1 X 1 -> 0 X 1 1 -> 1 X 0

S R 0->0 0 X 0->1 1 0 1->0 0 1 1->1 X 0 CLK S R Q T 0->0 0 0->1 1 1->0 1 1->1 0 CLK T Q

D 0->0 0 0->1 1 1->0 0 1->1 1 CLK D Q J K 0->0 0 X 0->1 1 X 1->0 X 1 1->1 X 0 CLK J K Q

Procedure uses excitation tables Method: to realize a type A flipflop using a type B flipflop: 1. Start with the K-map or state-table for the A-flipflop. 2. Express B-flipflop inputs as a function of the inputs and present state of A-flipflop such that the required state transitions of A-flipflop are reallized. x Q g CL x Q y h CL y Type B Type A 1. Find Q + = f(g,h,q) for type A (using type A state-table) 2. Compute x = f1(g,h,q) and y=f2(g,h,q) to realize Q +.

Example: Use JK-FF to realize D-FF 1) Start transition table for D-FF 2) Create K-maps to express J and K as functions of inputs (D, Q) 3) Fill in K-maps with appropriate values for J and K to cause the same state transition as in the D-FF transition table D Q Q + J K 0 0 0 0 X 0 1 0 X 1 1 0 1 1 X 1 1 1 X 0 State-Table e.g. when D=Q=0, then Q + = 0 the same transition Q-->Q + is realize with J=0, K=X Q 0 0 1 1 D Q Q + 0 1 0 1 0 1 R X 0 1 0 0 1 0 1 X X S 0 1 0 X J 0 1 X X D Q 0 1 K X X 1 0 X T 0 1 1 0 0 1 X 1 0 D 0 1 0 1 J = D K = D

Example: Implement JK-FF using a D-FF J K Q Q+ D T 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 1 J K J K Clk D DFF C T T-FF Q Q JK Q 0 J 00 01 11 10 0 0 1 1 JK Q 0 J 00 01 11 10 0 0 1 1 Clk C 1 1 0 0 1 1 0 1 1 0 K K d= jq + Kq t= jq + kq

PRESET and CLEAR: asynchronous, level-sensitive inputs used to initialize a flipflop. PRESET, CLEAR: active low inputs Clk PRESET T Q CLEAR PRESET = 0 --> Q = 1 CLEAR = 0 --> Q = 0 LogicWorks Simulation 200 400 SET 1 0 D S Q 0 1 T Q CRQ Clk 1 0 CLR Clk CLR SET T Q

Counters are a specific type of sequential circuit. Like registers, the state, or the flip-flop values themselves, serves as the output. The output value increases by one on each clock cycle. After the largest value, the output wraps around back to 0. Using two bits, we d get something like this: Present State Next State A B A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 00 1 01 1 1 1 11 10

Counters can act as simple clocks to keep track of time. You may need to record how many times something has happened. How many bits have been sent or received? How many steps have been performed in some computation? All processors contain a program counter, or PC. Programs consist of a list of instructions that are to be executed one after another (for the most part). The PC keeps track of the instruction currently being executed. The PC increments once on each clock cycle, and the next program instruction is then executed.

Let s try to design a slightly different two-bit counter: Again, the counter outputs will be 00, 01, 10 and 11. Now, there is a single input, X. When X=0, the counter value should increment on each clock cycle. But when X=1, the value should decrement on successive cycles. We ll need two flip-flops again. Here are the four possible states: 00 01 11 10

Here s the complete state diagram and state table for this circuit. 0 00 01 1 0 1 1 0 1 11 10 0 Present State Inputs Next State Q 1 Q 0 X Q 1 Q 0 0 0 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 0

If we use D flip-flops, then the D inputs will just be the same as the desired next states. Equations for the D flip-flop inputs are shown at the right. Why does D 0 = Q 0 make sense? Present State Inputs Next State Q 1 Q 0 X Q 1 Q 0 0 0 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 0 Q 0 0 1 0 1 Q 1 1 0 1 0 X D 1 = Q 1 Q 0 X Q 0 1 1 0 0 Q 1 1 1 0 0 X D 0 = Q 0

Here are some D Flip Flop devices from LogicWorks. They have both normal and complemented outputs, so we can access Q0 directly without using an inverter. (Q1 is not needed in this example.) This circuit counts normally when Reset = 1. But when Reset is 0, the flip-flop outputs are cleared to 00 immediately. There is no three-input XOR gate in LogicWorks so we ve used a four-input version instead, with one of the inputs connected to 0.

If we use JK flip-flops instead, then we have to compute the JK inputs for each flip-flop. Look at the present and desired next state, and use the excitation table on the right. Q(t) Q(t+1) J K 0 0 0 x 0 1 1 x 1 0 x 1 1 1 x 0 Present State Inputs Next State Flip flop inputs Q 1 Q 0 X Q 1 Q 0 J 1 K 1 J 0 K 0 0 0 0 0 1 0 x 1 x 0 0 1 1 1 1 x 1 x 0 1 0 1 0 1 x x 1 0 1 1 0 0 0 x x 1 1 0 0 1 1 x 0 1 x 1 0 1 0 1 x 1 1 x 1 1 0 0 0 x 1 x 1 1 1 1 1 0 x 0 x 1

Present State Inputs Next State Flip flop inputs Q 1 Q 0 X Q 1 Q 0 J 1 K 1 J 0 K 0 0 0 0 0 1 0 x 1 x 0 0 1 1 1 1 x 1 x 0 1 0 1 0 1 x x 1 0 1 1 0 0 0 x x 1 1 0 0 1 1 x 0 1 x 1 0 1 0 1 x 1 1 x 1 1 0 0 0 x 1 x 1 1 1 1 1 0 x 0 x 1 We can then find equations for all four flip-flop inputs, in terms of the present state and inputs. Here, it turns out J 1 = K 1 and J 0 = K 0. J 1 = K 1 = Q 0 X + Q 0 X J 0 = K 0 = 1

Here is the counter again, but using JK Flip Flop n.i. RS devices instead. The direct inputs R and S are noninverted, or active-high. So this version of the circuit counts normally when Reset = 0, but initializes to 00 when Reset is 1.

This counter is called asynchronous because not all flip flops are hooked to the same clock. Look at the waveform of the output, Q, in the timing diagram. It resembles a clock as well. If the period of the clock is T, then what is the period of Q, the output of the flip flop? It's 2T! We have a way to create a clock that runs twice as slow. We feed the clock into a T flip flop, where T is hardwired to 1. The output will be a clock who's period is twice as long.

If the clock has period T. Q0 has period 2T. Q1 period is 4T With n flip flops the period is 2 n.

This is called as a ripple counter due to the way the FFs respond one after another in a kind of rippling effect.

To eliminate the "ripple" effects, use a common clock for each flip-flop and a combinational circuit to generate the next state. For an up-counter, use an incrementer => Incrementer A3 A2 A1 A0 S3 S2 S1 S0 D3 D2 D1 D0 Q3 Q2 Q1 Q0 Clock

Internal details => Internal Logic Incrementer XOR complements each bit AND chain causes complement of a bit if all bits toward LSB from it equal 1 Count Enable Forces all outputs of AND chain to 0 to hold the state Carry Out Added as part of incrementer Connect to Count Enable of additional 4-bit counters to form larger counters

Use the sequential logic model to design a synchronous BCD counter with D flip-flops State Table => Input combinations 1010 through 1111 are don t cares Current State Q8 Q4 Q2 Q1 Next State Q8 Q4 Q2 Q1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0

Use K-Maps to two-level optimize the next state equations and manipulate into forms containing XOR gates: D1 = Q1 D2 = Q2 + Q1Q8 D4 = Q4 + Q1Q2 D8 = Q8 + (Q1Q8 + Q1Q2Q4) Y = Q1Q8 The logic diagram can be drawn from these equations An asynchronous or synchronous reset should be added What happens if the counter is perturbed by a power disturbance or other interference and it enters a state other than 0000 through 1001?

Find the actual values of the six next states for the don t care combinations from the equations Find the overall state diagram to assess behavior for the don t care states (states in decimal) Present State Next State Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 1 0 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 0 1 1 0 1 1 1 0 1 0 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 0 8 7 9 6 11 0 5 14 1 15 12 13 10 4 2 3

For the BCD counter design, if an invalid state is entered, return to a valid state occurs within two clock cycles Is this adequate?!

The examples shown so far have all had 2 n states, and used n flip-flops. But sometimes you may have unused, leftover states. For example, here is a state table and diagram for a counter that repeatedly counts from 0 (000) to 5 (101). What should we put in the table for the two unused states? Present State Next State Q 2 Q 1 Q 0 Q 2 Q 1 Q 0 000 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 1 0??? 1 1 1??? 101 100 011 001 010

To get the simplest possible circuit, you can fill in don t cares for the next states. This will also result in don t cares for the flip-flop inputs, which can simplify the hardware. If Present the circuit State somehow Next ends State up in one of the unused states (110 or 111), its behavior Q 2 Q 1 will Qdepend 0 Q 2 on Qexactly 1 Q 0 what the don t cares were filled in with. 0 0 0 0 0 1 000 0 0 1 0 1 0 0 1 0 0 1 1 101 001 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 0 100 010 1 1 0 x x x 1 1 1 x x x 011

To get the safest possible circuit, you can explicitly fill in next states for the unused states 110 and 111. This guarantees that even if the circuit somehow enters an unused state, it will eventually end up in a valid state. This is called a self-starting counter. Present State Next State Q 2 Q 1 Q 0 Q 2 Q 1 Q 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 110 101 100 000 011 111 001 010

There are a couple of different counters available in LogicWorks. The simplest one, the Counter-4 Min, just increments once on each clock cycle. This is a four-bit counter, with values ranging from 0000 to 1111. The only input is the clock signal.

More complex counters are also possible. The full-featured LogicWorks Counter-4 device below has several functions. It can increment or decrement, by setting the UP input to 1 or 0. You can immediately (asynchronously) clear the counter to 0000 by setting CLR = 1. You can specify the counter s next output by setting D 3 -D 0 to any four-bit value and clearing LD. The active-low EN input enables or disables the counter. When the counter is disabled, it continues to output the same value without incrementing, decrementing, loading, or clearing. The counter out CO is normally 1, but becomes 0 when the counter reaches its maximum value, 1111.

As you might expect by now, we can use these general counters to build other counters. Here is an 8-bit counter made from two 4-bit counters. The bottom device represents the least significant four bits, while the top counter represents the most significant four bits. When the bottom counter reaches 1111 (i.e., when CO = 0), it enables the top counter for one cycle. Other implementation notes: The counters share clock and clear signals.

We can also make a counter that starts at some value besides 0000. In the diagram below, when CO=0 the LD signal forces the next state to be loaded from D 3 -D 0. The result is this counter wraps from 1111 to 0110 (instead of 0000).

We can also make a circuit that counts up to only 1100, instead of 1111. Here, when the counter value reaches 1100, the NAND gate forces the counter to load, so the next state becomes 0000.

Counters serve many purposes in sequential logic design. There are lots of variations on the basic counter. Some can increment or decrement. An enable signal can be added. The counter s value may be explicitly set. There are also several ways to make counters. You can follow the sequential design principles to build counters from scratch. You could also modify or combine existing counter devices.

Creating a sequential circuit to address a design need.

Steps in the design process for sequential circuits State Diagrams and State Tables Examples

Steps in Design of a Sequential Circuit 1. Specification A description of the sequential circuit. Should include a detailing of the inputs, the outputs, and the operation. Possibly assumes that you have knowledge of digital system basics. 2. Formulation: Generate a state diagram and/or a state table from the statement of the problem. 3. State Assignment: From a state table assign binary codes to the states. 4. Flip-flop Input Equation Generation: Select the type of flip-flop for the circuit and generate the needed input for the required state transitions

5. Output Equation Generation: Derive output logic equations for generation of the output from the inputs and current state. 6. Optimization: Optimize the input and output equations. Today, CAD systems are typically used for this in real systems. 7. Technology Mapping: Generate a logic diagram of the circuit using ANDs, ORs, Inverters, and F/Fs. 8. Verification: Use a HDL to verify the design.

Sequential machines are typically classified as either a Mealy machine or a Moore machine implementation. Moore machine: The outputs of the circuit depend only upon the current state of the circuit. Mealy machine: The outputs of the circuit depend upon both the current state of the circuit and the inputs.

The specification: The circuit will have one input, X, and one output, Z. The output Z will be 0 except when the input sequence 1101 are the last 4 inputs received on X. In that case it will be a 1.

Create states and meaning for them. State A the last input was a 0 and previous inputs unknown. Can also be the reset state. State B the last input was a 1 and the previous input was a 0. The start of a new sequence possibly. Capture this in a state diagram

Capture this in a state diagram Circles represent the states Lines and arcs represent the transition between state. The notation Input/Output on the line or arc specifies the input that causes this transition and the output for this change of state.

Add a state C State C Have detected the input sequence 11 which is the start of the sequence.

Add a state D State D have detected the 3 rd input in the start of a sequence, a 0, now having 110. From State D, if the next input is a 1 the sequence has been detected and a 1 is output.

The previous diagram was incomplete. In each state the next input could be a 0 or a 1. This must be included.

The state table This can be done directly from the state diagram. Now need to do a state assignment

Will select a gray encoding For this state A will be encoded 00, state B 01, state C 11 and state D 10

Generate the equations for the flip-flop inputs Generate the D 0 equation Generate the D 1 equation

The next step is to generate the equation for the output Z and what is needed to generate it. Create a K-map from the truth table.

The circuit has 2 D type F/Fs

UNIT 5

Data Storage (Volatile) Locations (Address) Byte or Word Data input Address Read Write Memory unit 16 x 8 Data output 18 4 / 18

Data Storage (Volatile) Locations (Address) Byte or Word m Data input 10 Address lines 1024 locations = 1 K k Address Read Write Memory unit 2 k x m m Data output 18 5 / 18

Memory Cell Select Input BC Output Select Read/Write Input S Q Output R Q Read/Write 18 6 / 18

Memory Array AddressL ines Memory Enable Read/Write I 1 I 0 2 x 4 Decoder E 0 1 2 3 Input Data BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC 18 7 / 18

k Address Memory Enable ROM 2 k x m m Data output 18 8 / 18

Conventional Symbol Array Logic Symbol 18 9 / 18

8 x 4 ROM AddressL ines Memory Enable 3 x 8 Decoder I 2 I 1 I 0 E 0 1 2 3 4 5 6 7 Output Data 19 0 / 18

8 x 4 ROM Address 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Data 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 1 0 0 1 0 1 1 1 0 0 0 0 A 2 A 1 A 0 1 3 x 8 Decoder I 2 I 1 I 0 E 0 1 2 3 4 5 6 7 D 3 D 2 D 1 D 0 19 1 / 18

Mask Programmed ROM Programmed during manufacturing Programmable Read-Only Memory (PROM) Blow out fuses to produce 0 Erasable Programmable ROM (EPROM) Erase all data by Ultra Violet exposure Electrically Erasable PROM (EEPROM) Erase the required data using an electrical signal 19 2 / 18

Boolean Functions: Sums-of-Products AND-plane followed by OR-plane Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 I 2 I 1 I 0 19 3 / 18

PROM Inputs PAL Fixed AND array (Decoder) Programmable OR array Outputs Inputs PLA Programmable AND array Fixed OR array Outputs Inputs Programmable AND array Programmable OR array Outputs 19 4 / 18

Example w(a,b,c,d) = (2,12,13) x(a,b,c,d) = (7,8,9,10,11,12,13,14,15) 1 2 3 1 2 3 4 5 6 7 8 9 10 F 1 w y(a,b,c,d) = (0,2,3,4,5,6,7,8,10,11,15) A I 1 z(a,b,c,d) = (1,2,8,12,13) Simplify: 4 5 F 2 x w = ABC + A B CD x = A + BCD y = A B + CD + B D B I 2 z = ABC + A B CD + AC D + A B C D = w + AC D + A B C D C I 3 6 7 8 9 F 3 y 10 11 F 4 z 12 D I 4 1 2 3 4 5 6 7 8 9 10 19 5 / 18

A B C I 1 I 2 I 3 Example: F 1 = AB + AC + A BC F 2 = (AC + BC) 0 1 F 1 F 2 19 6 / 18

Basic Macrocell Logic CLK OE D Q ENB Q 19 7 / 18

The following memory units are specified by the number of words times the number of bits per word. How many address lines and input-output lines are needed in each case? (a) 4K 16, (b) 2G 8, (c) 16M 32, (d) 256K 64. Give the number of bytes stored in the memories listed in Problem 7-1. Word number 723 in a memory of 1024 16 contains the binary equivalent of 3,451. List the 10-bit address and the 16-bit memory content of the word. 19 8 / 18

Specify the size of a ROM (number of words and number of bits per word) that will accommodate the truth table for the following combinational circuit components: (a) a binary multiplier that multiplies two 4-bit, (b) a 4-bit adder-subtractor, (c) a quadruple 2-to-1-line multiplexers with common select and enable inputs, and (d) a BCD-to-seven-segment decoder with an enable input. 19 9 / 18

Tabulate the truth table for an 8 4 ROM that implements the Boolean functions A(x,y,z) = (1,2,4,6) B(x,y,z) = (0,1,6,7) C(x,y,z) = (2,6) D(x,y,z) = (1,2,3,5,7) 20 0 / 18