ENG24 Digital Design Sequential Circuits: Part B Fall 27 S. Areibi Schl f Engineering University f Guelph Analysis f Sequential Circuits Earlier we learned hw t analyze cmbinatinal circuits We will extend analysis t synchrnus sequential We ll use. State tables and 2. State diagrams 4 Week #7 Tpics Review: Flip Flps Sequential Circuit Analysis Sequential Circuit Design Designing with D Flip-Flps Designing with JK Flip-Flps Designing with T Flip-Flps VHDL Representatins Examples 2 5 Resurces Analysis f Sequential Circuits Chapter #6, Man Sectins 6.4 Sequential Circuit Analysis 6.5 Sequential Circuit Design 6.7 VHDL Representatin f Sequential circuits The behavir f a sequential circuit is determined frm: Inputs, Outputs, Present state f the circuit. The analysis f a sequential circuit cnsists f: Obtaining a suitable descriptin that demnstrates the time sequence f inputs, utputs and states (STATE DIAGRAM). 3 6 Schl f Engineering
Step #: Derive Input Equatins Can describe inputs t FF with lgic equatins J A = ( B + YC) Time is Implied Nte that previus circuit used the Present state (A, B,..) t determine next state State and inputs t determine utput Synchrnus circuit When are transitins? K A = ( YB + C) D A = ( A + B ) D B = A Y = ( A+ B) 7 Anther Example D A = ( A + B ) Step #2: State Table Similar t truth table with state added A sequential circuit with `m FFs and `n inputs needs 2 m+n rws in state table. Next State and utput are determined using? (input equatins) D B = A Y = ( A + B) 8 D A = ( A + B ) D B = A Y = ( A + B) Input Equatins Step#3: State Diagram Mealy Mdel An alternative representatin t State Table Input Output Input Output The input equatins. Imply the type f flip-flp frm the letter symbls, 2. Fully specify the cmbinatinal circuit that drives the flip-flps. / / Input/Output 9 2 Schl f Engineering 2
Sequential Circuit Types State Table vs. Diagram Mre mdel utputs depend n states nly. Mealy mdel utputs depend n inputs & states 3 Prvides same infrmatin Table is perhaps easier t fill in frm descriptin Diagram is easier fr understanding and writing cde Analysisfr sequential circuits that emplys D flip flpsis easy. Why? Because the next state values are btained directly frm the input equatins. 6 State Diagram: Mre Analysis with JK Flip Flps Alternative representatin fr state table State/Output Inputs Fr circuits with ther types f flip flps such as JK, the next state values are btained by fllwing the tw step prcedure:. Obtain the binary values f each flip-flp input equatin in terms f the present state and input variables. 2. Use the crrespnding flip-flp characteristic table t determine the next state. 4 7 Mre vs. Mealy Machine Analysis with JK Flip Flps Mre Machine: Easy t understand and easy t cde. Might requires mre states (thus mre hardware). Mealy Machine: Mre cmplex since utputs are a functin f bth the state and input. Requires less states in mst cases, therefre less cmpnents. Chice f a mdel depends n the applicatin and persnal preference. Yu can transfrm a Mealy Machine t a Mre Machine and vice versa. J A = B J B = x K A = Bx K B = A x + Ax = A x 5 8 Schl f Engineering 3
JK Analysis: State Table Analysis vs. Design J A = B K A = Bx J B = x K B = A x + Ax = A x Flip Flp Inputs I. Use the Input equatins t determine the FF inputs. II. Use the FF inputs and Table t determine the next state. JK Characteristic Table The analysis f sequential circuits starts frm a circuit diagram and culminates in a state table r state diagram. The design f a sequential circuit starts frm a set f specificatins and we shuld btain the state diagram and finally the lgic diagram. 9 22 JK Analysis State Table Design Prcedure J A = B J B = x K A = Bx K B = A x + Ax = A x Flip Flp Inputs Design starts frm a specificatin and results in a lgic diagram r a list f Blean functins. The steps t be fllwed are:. Derive a state diagram 2. Reduce the number f states 3. Assign binary values t the states 4. Obtain the binary cded state table 5. Chse the type f flip flps t be used 6. Use Excitatin Tables t derive state table 7. Derive the simplified flip flp input equatins and utput equatins 8. Draw the lgic diagram 2 23 JK Analysis: State Diagram Sequential Circuit Design Remember that a synchrnus sequential circuit is made up f flip flps and cmbinatinal gates. Part f the design is t chse the flip-flp type and cmbinatinal circuit structure which, tgether with the flip-flps prduce a circuit that fulfills the stated specificatin. Hw many FLIP FLOPS?. The number f flip-flps is determined frm the number f states in the circuit 2. n flip-flps can represent up t 2 n binary states. 3. Examples:. 2 states requires a single Flip Flp 2. 4 states requires tw flip flps 3. 8 states requires three flip flps 4. 7 states requires again three flip flps 2 24 Schl f Engineering 4
Designing with D Flip-Flps Designing with D Flip-Flps Design a clcked sequential circuit that perates accrding t the state diagram. Use D Flip Flps Hwever, we have t minimize the expressinin a similar way used fr cmbinatinal lgic design! 25 28 Synthesizing Using D Flip Flps Designing with D Flip-Flps The next step is t create a state table and then select tw D flip flps t represent the fur states, labeling their utputs as A and B. There is ne input, x, and ne utput, y, representing the input sequence and the utput value respectively. Remember that the Excitatin Table (characteristic equatin) f the D flip flp is Q(t + ) = D Q This means that the next-state values in the state table specify the D input cnditin fr the flip flp. 26 29 Designing with D Flip-Flps Designing with D Flip-Flps Input equatins can be btained directly frm the table using minterms: A(t + ) = D A (A, B, x) = m(2,4,5,6) B(t + ) = D B (A, B, x) = m(,3,5,6) D A = AB + B D B = A + B + AB Y = B 27 3 Schl f Engineering 5
A Sequence Detectr Blean Minimizatin Design a circuit that detects a sequence f three nes. Use Mre Machine. I. Create the state diagram K-Maps can be used t minimize the input equatins, resulting in D A = Ax + Bx D B = Ax + B x Y = AB Input Circuit Detects ` at input Output Mre Machine 3 34 Synthesizing Using D Flip Flps Lgic Diagram f Sequence Detectr II. III. IV. The next step is t create a state table and then select tw D flip flps t represent the fur states, labeling their utputs as A and B. There is ne input, x, and ne utput, y, representing the input sequence and the utput value respectively. The utput y is ` nly when we detect the input sequence f ` 32 35 State Table fr Sequence Detectr Sequential Circuits with different Flip Flps (JK, T) The design f sequential circuits ther than D type flip flps is cmplicated by the fact that input equatins must be derived indirectly frm the state table. It is necessary t derive a functinal relatinship between the state table and the input equatins. Input equatins can be btained directly frm the table using minterms: A(t + ) = D A (A, B, x) = m(3, 5, 7) B(t + ) = DB(A, B, x) = m(, 5, 7) y(a, B, x) = m(6, 7) 33 36 Schl f Engineering 6
Excitatin Table Example: JK Synthesis Step #: Obtain State Table During the design, we usually knw the transitin frm present t next state but we need t find the flip flp input cnditins that will cause the required transitin. We need a table that lists the required inputs fr a given change f state, called an excitatin table. Example: N utput 37 4 Excitatin Tables JK Synthesis: State Table Characteristic Table Excitatin Table Present State Next State Characteristic Table Excitatin Table 38 4 Synthesis Using JK Flip Flps Cnt.. Example JK Synthesis Step #2: Use K-Maps Synthesis f circuits with JK flip flps is the same as with D flip flps Except that the input equatins must be evaluated frm the present-state t the next-state transitin derived frm the excitatin table. 39 42 Schl f Engineering 7
Cnt.. Example JK Synthesis Synthesis Using T Flip Flps A Bx JA = B Synthesis f circuits with T flip flps is the same as with JK flip flps except that the input equatins must be evaluated frm the present-state t the next-state transitin derived frm the T excitatin table. 43 46 Cnt.. Example JK Synthesis Synthesis Using T Flip Flps Design a cunter that cunts frm t and then back t again. Cnstraint: Use T Flip-Flps 44 47 Cnt.. JK Synthesis Lgic Diagram A Cunter using T Flip Flps Ntice the nly input is the clck! 45 48 Schl f Engineering 8
Example: T Flip Flp Synthesis Tw Dimensinal Tables Same thing, different layut 49 52 Cnt.. T Flip Flps Example Sequence Recgnizer (VHDL) By using K-maps we can minimize the flip flp input equatins. T A 2 T A Circuit has input: Wand utput: Z Recgnizes sequence f n W Specifically, if W has been and next bit is, make Z high Design a Mre and Mealy Machines T A W Sequence Recgnizer Z 5 53 One Dimensinal Tables Sequence Recgnizer (Mealy) w=/z= A B w=/z= w=/z= w=/z= Clk: t t t2 t3 t4 t5 t6 t7 t8 t9 t w: z: 5 54 Schl f Engineering 9
Mealy: Implementatin Mre: Implementatin A/z= w= B/Z= w= w= w=/z= w= w= A B C/z= w=/z= w=/z= w=/z= w= Clk: t t t2 t3 t4 t5 t6 t7 t8 t9 t Clk : t t t2 t3 t4 t5 t6 t7 t8 t9 t w: w: z: z: 55 58 -- (Mealy Machine f Sequence Recgnizer) library IEEE; clk_prcess: prcess(reset,clk) use IEEE.std_lgic_64.all; begin if reset = then -- Check fr reset and initialize state entity SeqRec_Mealy is present_state <= A; prt (reset, clk, w: in std_lgic; Elsif (rising_edge(clk)) then -- wait until the rising edge z: ut std_lgic); present_state <= next_state; end entity SeqRec_Mealy; end prcess clk_prcess; architecture behaviral f SeqRec_Mealy is type statetype is (A, B); -- define new type end architecture behaviral; signal present_state, next_state: statetype; Begin next_ut_prcess: prcess(present_state,w) is begin case present_state is -- depending upn current state when A => -- set utput signals and next state if w = '' then next_state <= A; z <= '; else next_state <= B; z <= ''; w=/z= when B => if w = '' then A B next_state <= B; z <= '; else w=/z= w=/z= w=/z= next_state <= A; z <= '; end case; end prcess next_ut_prcess; 56 -- (Mre Machine f Sequence Recgnizer) next_state_prcess: prcess( present_state, w) is library IEEE; begin use IEEE.std_lgic_64.all; case present_state is -- depending upn current state when A => -- set next state entity SeqRec_Mre is if w = '' then prt (reset, clk, w: in std_lgic; next_state <= A; z: ut std_lgic); else end entity SeqRec_Mre; next_state <= B; architecture behaviral f SeqRec_Mre is when B => type statetype is (A, B,C); -- define new type if w = ' then signal present_state, next_state: statetype; next_state <= A; Begin else next_state <= C; clk_prcess: prcess( reset, clk) begin when C => if reset = then -- Check fr reset and initialize state if w = then present_state <= A; next_state <= A; Elsif (rising_edge(clk)) then -- wait until the rising edge else present_state <= next_state; next_state <= C; end case; end prcess clk_prcess; end prcess next_state_prcess; utput_prcess: prcess( present_state) is w= begin A/z= B/Z= case present_state is -- depending upn current state when A => -- set utput signals w= w= z<= ; when B => z<= ; w= w= when C => C/z= z<= ; end case; end prcess utput_prcess; w= End architecture behaviral, 59 Sequence Recgnizer (Mre) w= A/z= B/Z= w= w= w= w= C/z= w= Clk: t t t2 t3 t4 t5 t6 t7 t8 t9 t w: z: 57 Schl f Engineering
T Flip Flp Analysis Analysis f a sequential circuit with T flip flps fllws the same prcedure utlined fr JK flip flps. The next state values in the state table can be btained by using the characteristic table r the characteristic equatin Q(t + ) = T Q = T Q + TQ 6 T Flip Flp Analysis Example x T A y T R R B T A = Bx T B = x Y = AB CLK 62 T Flip Flp Analysis State Table T A = Bx T B = x Y = AB A(t + ) = T A A = Bx A B(t + ) = T B B = x B 63 Schl f Engineering