www.fairchildsemi.com Application Note AN60 FAN4800 Combo Controller Applications eneral Description This application note shows the step-by-step process to design a high-performance supply. The equations shown in this document can also be used for different output voltages and total power. The complete power supply circuits shown in Figures 6 and 7 demonstrate the FAN4800 s ability to manage high output power while complying with international requirements regarding AC line quality. The FC section provides 80 DC to a dual-transistor current-mode forward converter. The output of the converter delivers + at up to 8.4 amps. The circuit operates from 85 to 65 AC with both power sections switching at 00kHz. The FC Stage owering the FAN4800 The FAN4800 is initialized once C is charged to through R 7 and R 8. FC switching action boosts the voltage on C 5 to 80 via L s inductance. T then supplies a well-regulated for the FAN4800 from its secondary winding. T s primary-to-secondary turns ratio (N R / N SEC ) is 8.8:. For proper circuit operation, high-frequency bypassing with low-esr ceramic or film capacitors on CC and REF is provided. Orderly FC operation upon start-up is achieved when D quick charges the boost capacitor to the peak AC line voltage before the boost switch Q is turned on. This ensures the boost inductor current is zero before F.5A AC NUT C 85 TO 65ac 0.68uF SENSE R5D R5C. R5B. R5A.. R 00 BR 4A, 600 KBL06 RA 45k RB 45k C 0. R 0k C 0.47uF R4 5.4k RA RB D L N5406 Q R7 75k D9 R 40 C0 0uF 5 R 7.5k D SL9R460 Q FQF9N50 C4 0nF 40 R6 4.7k R0 6.k NOT USED.5nF 00uF 450 C 0uF 5 78k R7B 78k D RFJ / +80 Q R7 Q FQF 6N50 R0 4.7k 0. D5 RFJ TB D7 MMBZ545B Q T R4 Q D6 FQF6N50 RFJ C0 R5 RAM / DC LMT R0A R0B.. TA R9 0 U FAN4800 R9.k EAO 6 EAO Q4 MMBT904 AC 5 D4 MMBZ545B SENSE 4 R 0k 4 RMS 5 SS FC OUT RAM D N540 6 7 RAM 8 RAM WM OUT ND DC LMT 0 9 D8 40 C.7k nf D0 40 0nF R 845k C4 C 0. 68nF R6 0k 0nF C0 5uF D N540 00nF 470pF C 0nF 0pF R ND Figure. The FC Stage 006 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800 Rev..0. /07/06
AN60 FC action begins. The value of the regulated voltage on C 5 must always be greater than the peak value of the maximum line voltage delivered to the supply. > in(rms_max) > (.44) ( 65) > 75 use 80 Because the FAN4800 uses transconductance amplifiers, the loop compensation networks are returned to ground (see the FAN4800 datasheet for the error amplifier characteristics/ advantages). This eliminates the interaction of the resistive divider network with the loop compensation capacitors, permitting a wide choice of divider values chosen to minimize amplifier offset voltages due to input bias currents. For reliable operation, R 7A and R 7B must have a voltage rating of at least 400 volts. Calculate the divider ratio (R 7A +R 7B )/R 8 by: + R7B.5 + R7B 80.5 + R7B 5 R Selecting the ower Components 8 The FAN4800 FC section operates with continuous inductor current to minimize peak current and to maximize available power. The boost inductor value found by setting Δ, the peak-to-peak value of high-frequency current, is typically 0% to 0% of the peak value of the maximum line current. in( peak _ max) in(max) O(max) η in(max) in( rms _ min) where in(peak_max) is a peak value of input current occurred at low line, in(rms_min) is RMS value of minimum line voltage, O(max) is the maximum output power, and η is efficiency. alue in(peak_max) defines value of Δ, where d is the specified percentage rate. L(max) is the inductor maximum current. Δ d in( peak _ max) Δ L(max) in( peak _ max) + Duty cycle D and switching frequency f S influence inductor selection. ( 4) ( 5) D D in( rms _ min) L fs Δ ( O in( rms _ min) ) in( rms _ min) η f d O { 80 (.44) ( 85) } ( 85) ( 0.95) 5 ( 80) ( 0 ) ( 0.5) ( 00).8mH in(rms_min) O O S O(max) use.0mh The boost diode D and switch Q are chosen with a reverse voltage rating of 500 to safely withstand the 80 boost potential. The maximum Q RMS current is obtained by Equation 8 and the maximum Q peak current is calculated by Equation 9. Qrms Qpeak 4 in( rms _ max) π in( rms _ min) O(max) 4 in( rms _ min) ηin( rms _ min) πo (.44) ( 00) 4.44 85 ( 0.95) ( 85).46 80.06 A Δ in( peak _ max) + O(max) ( O in(rms_min) ) in(rms_min) + ηin( rms _min) O fs L (.44) ( 00) 80 (.44) ( 85).44 85 + 5 ( 0.95) ( 85) ( 80) ( 0 ) ( 0 ).05A The boost diode average current can be calculated by: Davg O(max) O(max) O 00 0.6 A 80 The boost capacitor value is chosen to permit a given output voltage hold-up time in the event the line voltage is suddenly removed. C t HLD hold-up time (sec) (min) minimum voltage on C 5 at which the WM stage can still deliver full output power O { } O(max) HLD 5 ( NOM ) ( MN ) t ( 6) ( 7) ( 8) ( 9) ( 0) 006 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800 Rev..0. /07/06
AN60 A key advantage of using leading/trailing-edge modulation is that a large portion of the inductor current is "dumped" directly into the load (WM stage transformer) and not the boost capacitor. This relaxes the ESR requirement of the boost capacitor. For reference, Equation should be used as a starting point when choosing C 5 s maximum ripple current rating (at 0Hz). _rms O( ) ( peak _ rms ) Selecting the ower Setting Components The maximum average power delivered by the FC stage is set using the following procedure:. Find the resistive divider ratio that results in the voltage at the RMS pin being equal to.4 at the lowest line voltage. The voltage at this pin must be well filtered, yet able to respond well to transient line voltage changes. The resistor and capacitor values in the typical example were found empirically to offer the lowest ripple voltage and still respond well to line voltage changes. Should a ratio be required that is greatly different from that found in Equation, adjust the filter capacitor values according to Equations 4 and 5. f 5Hz, f Hz R TOT R A + R B + R + R 4. Find the constant of proportionality k M of the multiplier gain k in Equation 6a. To obtain "brownout" action below the lowest input voltage, the maximum gain of the multiplier must be used when finding k M. The maximum gain (0.5) occurs when the RMS input of the multiplier is.4. Equation 6 is the general expression for the multiplier gain versus the line voltage. R4.4 π R TOT in( rms _ min) RTOT C π f ( RA + RB) ( R + R4) R 4 RTOT + ( + ) ( + ) RA RB R R4 C π f R 4 ( a) ( 4) ( 5). Select the value of (R A +R B ) that permits the greatest multiplier output current without saturating the output. The maximum output current of the multiplier is 8.57μA. 4. Select the value of the current sense resistor to complete the calculations for the power setting components. ( R R ) ( R R ) k k rms k k M in(rms_min) ( 0.5) ( 85) 58.75 59 R MULO multiplier output termination resistance (.5kΩ). oltage Loop Compensation M A B ( EAO(max) ) k in( rms _ min) 0.65 + 8.57 0 ( 0.5) (.44) ( 85)( 6 0.65) A + B 8.57 0 R + R 989.8k Ω use MΩ A B R R R R 5A 5B 5C 5D R R R R RMULO km EAO(max) 0.65 η R R ( + ) O(max) A B ( 6) ( 6a) ( 7) (.5 0 ) ( 59)( 6 0.65) ( 0.95) ( 00)( 0 ) 5A 5B 5C 5D 6 R R R R 0.45 Ω use 0.Ω 5A 5B 5C 5D ( 8) Maximum transient response of the FC section, without instability, is obtained when the open-loop crossover frequency is one-half the line frequency. For this application, the compensation components (pole/zero pair) are chosen so that the closed loop response decreases at 0dB/decade, crossing unity gain at 0Hz, then immediately decreasing at 40dB/decade. The error amplifier pole is placed at 0Hz and an effective zero at one-tenth this frequency, or Hz. Find the crossover frequency ( S ) of the power stage. For reference, Equation 0 finds the power stage pole and Equation finds the power stage DC gain. 006 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800 Rev..0. /07/06
AN60 BOOST R7 FB 5.5 EAO 6 R Figure. oltage Amp Compensation in(max) fc πo( EAO(max) 0.65) O(max) πηo ( EAO(max) 0.65) 00 f The gain of the power stage at 0Hz is calculated by: The power stage gain is attenuated by the resistive divider (R 7A +R 7B )/R 8 according to Equation : (.46 ) ( 0.95) ( 80) ( 6 0.65) ( 00 0 ) 8.0Hz π RC RL L 5 (.46 ) ( 444) ( 00 0 ).0Hz O O(max) S( DC ) S( 0 Hz ) f f C (.44) ( 8.0).0 5.7 4.44dB fc 0 8.0 0.74 8.76dB ( 9) ( 0) RD + R7B +.7 78 + 78 +.7 6.6 0 4.59dB The amount of error amplifier gain required to bring the open-loop gain to unity at 0Hz is the negative of the sum of the power stage, plus divider stage gain (attenuation): The value of R, which sets the high-frequency gain of the error amplifier, can be determined by: Calculate C 8 ; which, together with R, sets the zero frequency at Hz. Since the pole frequency is ten times the zero frequency, the pole capacitor C 9 is one-tenth the value of C 8. Current Loop Compensation ( 8.76 ( 4.59) ) + R EA S( 0 Hz ) RD + 4.854dB ( 55.9 / ) EA gm 55.9 70 0 789.8k Ω use 845kΩ π R f Z (.46 ) ( 845 0 ) 6.8nF 0 68 0 0 6.8nF 9 ( 4) ( 5) The current loop is compensated like the voltage loop, except the choice of the open-loop crossover frequency. To prevent interaction with the voltage loop, the current loop bandwidth should be greater than ten times the voltage loop crossover frequency, but no more than one sixth the switching frequency, or 6.7kHz. The power stage crossover frequency is calculated by Equation 8, the pole frequency by Equation 9, and the power stage DC gain by Equation 0. use 68nF use 0nF ( 6) ( 7) 006 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800 Rev..0. /07/06 4
AN60 R5A R5B R5C R5D ND 0 SENSE AC EAO REF Figure. Current Amp Compensation f C Find the gain of the power stage at 6.7kHz..5k.5k ( 0.)( 80) R EAO The current loop contains no attenuating resistors, so find the error amplifier gain with: Determine the value of the current error amplifier setting resistor R. 4 REF R 5A R 5B R 5C R5D O π L (.46 ) ( 0 ) (.75).kHz f π RC L 5 RAM( ) (.46) ( 444) ( 00 0 ).0Hz same as (0) S( DC ) f f C (.44) (.0 0 ).0 44 6.0dB fc 6.7 0.0 0 6.7 0. 0 7.60dB S( 6.7 khz ) ( ) 7.60dB 7.58 / EA S( 6.7 khz ) ( 7.60) ( 8) ( 9) ( 0) Calculate the value of C 6 to form the zero at.67khz. The pole capacitor C 7 is one-tenth the value of C 6. The WM Stage Soft-Starting the WM Stage The FAN4800 features a dedicated soft-start pin for controlling the rate of rise of the output voltage and preventing overshoot during power on. The controller does not initiate soft-start action until the FC voltage reaches its nominal value, thereby preventing stalling of the output voltage due to excessive FC currents. WM action is terminated in the event the FAN4800 loses power or if the FC boost voltage falls below 8 DC. The soft-start capacitor value (C 9 ) for 50ms of delay is found by Equation 6. Setting the Oscillator Frequency There is one version of the FAN4800. The FAN4800N is where the FC and WM run at the same frequency. FAN4800N π R f EA R gm(ce) 7.58 85 0 89.k Ω use 7.5kΩ Z (.46 ) ( 7.5 0 ) (.67 0 ).nf n general, it is best to choose a small-valued capacitor C 8 to maximize the oscillator duty cycle (minimize the C 8 discharge time). Too small a value capacitor can increase the oscillator s sensitivity to phase modulation caused by stray field voltage induction into this node. For the practical use.5nf 0.5 0 0 50 pf 9 0 0 ( tss ) 0.95 0 0 ( 0.05) 0.95 μf ( 4) ( 5) ( 6) 006 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800 Rev..0. /07/06 5
AN60 D RFJ / +80 Q 00uF 450 78k R7 0. R0 4.7k Q FQF 6N50 D5 RFJ C 0uF 5 R7B 78k TB D7 MMBZ545B DA MBR545CT L, 00W R 7.5k R6 4.7k R0 6.k NOT USED.5nF DB MBR545CT Q T R4 Q D6 FQF6N50 RFJ C0 R5 RAM / DC LMT R0A R0B.. TA R9 0 C4 R.5k U MO C 00uF 5 R4.k C 4.7uF R 8.66k 0 U FAN4800 R9.k EAO AC 6 EAO 5 D4 MMBZ545B Q4 MMBT904 R6 0k C 00nF SENSE 4 RMS 4 R 0k U TL4A R5.6k RET 5 SS FC OUT RETURN 6 WM OUT R 845k C0 5uF 7 RAM 8 RAM 0 ND 9 DC LMT D8 40 D0 40 C4 R6 0k 0nF C.7k nf 0nF C 0. 68nF 470pF C 0nF 0pF R ND Figure 4. The WM Stage example, a 470pF capacitor is chosen for C 8. Equation 7 is accurate with values of R 6 greater than 0k. Current Limit R6 0.5 fsw 5 ( 0.5) ( 0 ) ( 470 0 ) 4.7kΩ ( 7) The WM power stage operates in current mode using R 0A and R 0B to generate the voltage ramp for duty cycle control. The FAN4800 limits the maximum primary current via an internal comparator; which, when exceeded, terminates the drive to the external power MOSFETs. Maximum primary current is: R ( MAX ) R R. +... 0.9Amps 0 A 0 B ( 8) oltage Mode (Feedforward) Should voltage mode control be used, it is necessary to know C 5 s peak voltage to choose the correct ramp generating components. Equation 9 finds the worst-case peak-to-peak ripple voltage across C 5. To find the peak voltage, divide the ripple voltage by two and add it to the regulated boost voltage. Remember that since the FAN4800 employs leading/ trailing modulation, the actual peak-to-peak ripple voltage is generally much less than the calculated value. + ESR C 4π fl R( ) OUT( ) 5 f L line frequency. Solve Equation 40 for the ramp resistor value. The ramp capacitor value should be in the range of 470pF ~ 0nF. Choose a resistor with an adequate voltage rating to withstand the boost voltage. ( 9) 006 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800 Rev..0. /07/06 6
AN60 R RAM σ (MAX) maximum WM duty cycle (0.45 for the FAN4800) R peak-to-peak boost capacitor ripple voltage for Equation 9. The ower Transformer Turns Ratio The minimum output voltage at the secondary of T is found in Equation 4. The secondary voltage is chosen to be 0 volts to increase the output voltage hold-up time. The transformer turns ratio is derived from Equation 4: The maximum secondary current with the output shorted is limited by Equation 4: σ (MAX ) ( 40) CRAM fsw ln O + 0.5 R SEC( MN ) OUT + σ (MAX ) +.0 0.45 7.7olts NR O NSEC SEC( MN ) 80 0 N :N 8: R SEC F ( 4) ( 4) Output oltage Compensation A TL4 shunt regulator U and opto-isolator U perform output voltage setting and regulation. The opto crosses the primary-to-secondary safety boundary, varying the voltage on the DC pin to keep the output voltage constant against line and load changes. Using current-mode control simplifies loop compensation, leaving only a single pole and zero in the output stage. The pole is created from the output capacitor and equivalent load resistance. The zero is formed from the filter capacitor and its ESR. n this example, the action of the zero occurs well after the closed-loop response has crossed unity, so it was not compensated with a pole. The output pole is canceled, increasing the overall bandwidth by the addition of R 6 and C, which form a zero with TL4. For more information on using the TL4, including gain/phase versus frequency characteristics, refer to the Fairchild Semiconductor datasheet for the TL4.. Output Design Changes The latest microprocessors and support circuitry require a. supply for proper operation. The FAN4800 is ideal for these applications, including the energy-efficient, ecologically friendly "reen" C. f the total output power required varies greatly from 00 watts, it is necessary to re-select certain components, beginning with the FC stage. T s turn ratio must be adjusted according to Equation 4 and another low-current secondary winding added using the same turns ratio as originally found for the + volts. This second winding is necessary to power the TL4/opto circuit because the. output is not adequate to fully bias the feedback circuitry. C may be increased to reduce the output ripple voltage. Figure 5 displays a. output stage capable of supplying 6 amps. SEC( MAX ) R ( MAX ) N SEC N ( 0.9) ( 8).5Amps R ( 4) DA UF400 L OUTUT., 6A The output inductor and rectifier are chosen with maximum current rating larger than the maximum secondary current. T DB C4 C Output Filter Component Filter Selection R C R 0.k L s value is chosen to efficiently minimize output ripple current, thereby easing the ESR requirement of the filter capacitor. C s ESR value is the dominant contributor to the output ripple. The maximum ESR value required is found in Equation 44: U MO R6 C ESR Lf σ R SW (C) SEC ( MAX ) ( 44) U TL4A R5.6k R peak-to-peak output ripple voltage. Figure 5.. Output Stage 006 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800 Rev..0. /07/06 7
AN60 F.5A AC NUT 85 TO 65ac C 0.68uF SENSE R5A. R5B. R5C. R5D. RAM D N540 D N540 R 00 C 0. 00nF BR 4A, 600 KBL06 RA 45k RB 45k R 0k C 0.47uF R4 5.4k RA RB 470pF R7 75k C0 0uF 5 C 0nF L D N5406 D SL9R460 D RFJ / +80 R Q Q Q FQF9N50 Q D9 40 40 C4 0nF 00uF 450 C 0uF 5 78k R7B 78k R7 0. TB R0 4.7k D7 MMBZ545B FQF 6N50 D5 RFJ DA MBR545CT NOTE : L; REMER MANETCS TDS-047 L; REMER MANETCS T-05007 T; REMER MANETCS MO-0 T; REMER MANETCS TSO-75 L, 00W R 7.5k R6 4.7k R0 6.k NOT USED.5nF R4 C0 R5 TA Q R9 0 R0A. Q FQF6N50 R0B. D6 RFJ T DB MBR545CT RAM / DC LMT C4 R.5k U MO C 00uF 5 R4.k C 4.7uF R 8.66k 0 U FAN4800 R9.k 4 5 EAO AC SENSE RMS SS EAO FC OUT 6 5 4 D4 MMBZ545B Q4 MMBT904 R 0k U TL4A R6 0k C 00nF R5.6k RET RETURN 6 WM OUT R 845k C0 5uF 7 8 RAM RAM ND DC LMT 0 9 D8 40 D0 40 C4 R6 0k 0nF.7k C nf 0nF C 0. 68nF 0pF R ND Figure 6. Complete 00W Circuit (Current Mode) 006 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800 Rev..0. /07/06 8
AN60 F.5A AC NUT 85 TO 65ac C 0.68uF SENSE R5A. R5B. R5C. R5D. RAM D N540 D N540 R 00 C 0. 00nF BR 4A, 600 KBL06 RA 45k RB 45k R 0k C 0.47uF R4 5.4k RA RB 470pF R7 75k C0 0uF 5 C 0nF L D N5406 D SL9R460 D RFJ / +80 R Q Q Q FQF9N50 Q D9 40 40 C4 0nF 00uF 450 C 0uF 5 78k R7B 78k R7 0. TB R0 4.7k D7 MMBZ545B FQF 6N50 D5 RFJ DA MBR545CT NOTE : L; REMER MANETCS TDS-047 L; REMER MANETCS T-05007 T; REMER MANETCS MO-0 T; REMER MANETCS TSO-75 L, 00W R 7.5k R6 4.7k R0 6.k NOT USED.5nF R4 C0 R5 TA Q R9 0 R0A. Q FQF6N50 R0B. D6 RFJ T DB MBR545CT RAM / DC LMT C4 R.5k U MO C 00uF 5 R4.k C 4.7uF R 8.66k 0 U FAN4800 R9.k 4 5 EAO AC SENSE RMS SS EAO FC OUT 6 5 4 D4 MMBZ545B Q4 MMBT904 R 0k U TL4A R6 0k C 00nF R5.6k RET RETURN 6 WM OUT R 845k C0 5uF 7 8 RAM RAM ND DC LMT 0 9 D8 40 D0 40 C4 R6 0k 0nF R9 6.9k.7k C nf 0nF C 0. 68nF 470pF 0pF R ND Figure 7. Complete 00W Circuit (oltage Mode) 006 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800 Rev..0. /07/06 9
AN60 DSCLAMER FARCHLD SEMCONDUCTOR RESERES THE RHT TO MAKE CHANES WTHOUT FURTHER NOTCE TO ANY RODUCTS HEREN TO MROE RELABLTY, FUNCTON, OR DESN. FARCHLD DOES NOT ASSUME ANY LABLTY ARSN OUT OF THE ALCATON OR USE OF ANY RODUCT OR CRCUT DESCRBED HEREN; NETHER DOES T CONEY ANY LCENSE UNDER TS ATENT RHTS, NOR THE RHTS OF OTHERS. LFE SUORT OLCY FARCHLD S RODUCTS ARE NOT AUTHORZED FOR USE AS CRTCAL COMONENTS N LFE SUORT DECES OR SYSTEMS WTHOUT THE EXRESS WRTTEN AROAL OF THE RESDENT OF FARCHLD SEMCONDUCTOR CORORATON. As used herein:.life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user..a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 006 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800 Rev..0. /07/06 0