Hanbat National University Prof. Lee Jaeheung

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Transcription:

Sun, HH yy ee -Se ung Hanbat National University Prof. Lee Jaeheung

,,, ( ),, (c o u n t e r ), /, (F i n i t e S t a t e M a c h i n e ; F S M ),, : (, 0 1 ) : a l w a y s i f a l w a y s,, V e r i l o g (n o n b l o c k i n g b l o c k i n g )

11.1.1 (Latch) Positive level-sen sitive D la tc h d clock D G Q q clock d q module dlatch(clock, d, q); input clock, d; output q; reg q; always @(clock or d) begin if(clock) q = d; module Positive level-sensitive D latch 11.1

11.1.1 (Latch) module tb_dlatch ; reg clk, d; Testbench for D latch dlatch U0(clk, d, q); initial begin clk = 1'b0; forever #10 clk = ~clk; initial begin d = 1'b0; forever begin #15 d = 1'b1; #20 d = 1'b0; #10 d = 1'b1; #10 d = 1'b0; #10 d = 1'b1; #15 d = 1'b0; module 11.2

11.1.1 (Latch) 11.1 N eg a tive level-sen sitive 8 D,.

11.1.1 (Latch) A c tive-low p ositive level-sen sitive D la tc h module dlatch_rst(rst, clock, d, q); input rst, clock, d; output q; reg q; always @(clock or rst or d) begin if(!rst) q = 1'b0; else if(clock) q = d; module 11.3

11.1.1 (Latch) 11.3 A c tive-low n eg a tive level-sen sitive 8 D,.

11.1.1 (Latch) L a tc h b loc k in g module latch_blk(en, a, b, c, y); input en, a, b, c; output y; reg m, y; always @(en or a or b or c) begin if(en) begin m = ~(a b); y = ~(m & c); module 11.4 Latch

11.1.1 (Latch) L a tc h n on b loc k in g module latch_nonblk(en, a, b, c, y); input en, a, b, c; output y; reg m, y; always @(en or a or b or c) begin if(en) begin m <= ~(a b); y <= ~(m & c); module Latch 11.5 Latch

11.1.1 (Latch) 1 1.6 1 1.4 b loc k in g. 1 1.4,,. module latch_blk2(en, a, b, c, y); input en, a, b, c; output y; reg m, y; 11.6 always @(en or a or b or c) begin if(en) begin y = ~(m & c); m = ~(a b); module

11.1.1 (Latch) 1 1.7 1 1.5 n on b loc k in g. 1 1.5,,. module latch_nonblk2(en, a, b, c, y); input en, a, b, c; output y; reg m, y; 11.7 always @(en or a or b or c) begin if(en) begin y <= ~(m & c); m <= ~(a b); module

11.1.2 (Flip flop) Positive ed g e-tr ig g er ed D F lip -f lop d clock D Q q clk d q module dff(clk, d, q); input d,clk; output q; reg q; Positive edge-triggered D Flip-flop always @(posedge clk) q <= d; module 11.8

11.1.2 (Flip flop) 11.8

11.1.2 (Flip flop) E d g e-tr ig g er ed D F lip -f lop w ith q a n d qb ou tp u ts module dff_bad1(clk, d, q, q_bar); input d, clk; output q, q_bar; reg q, q_bar; always @(posedge clk) begin // nonblocking assignments q <= d; q_bar <= ~d; module module dff_bad2(clk, d, q, q_bar); input d, clk; output q, q_bar; reg q, q_bar; Not Recommed always @(posedge clk) begin // blocking assignments q = d; q_bar = ~d; module 11.9(a) 11.9(b)

11.1.2 (Flip flop) E d g e-tr ig g er ed D F lip -f lop w ith q a n d qb ou tp u ts module dff_good(clk, d, q, q_bar); input d, clk; output q, q_bar; reg q; Recommed // using assign statement for q_bar assign q_bar = ~q; always @(posedge clk) q <= d; module 11.9(c)

11.1.2 (Flip flop) E d g e-tr ig g er ed D F lip -f lop w ith q a n d qb ou tp u ts Flip flop Flip flop 11.9 (a), (b) Flip flop 11.9 (c)

11.1.2 (Flip flop) q q_ b a r D 1 1.1 0, D. 1 1.1 0,. module dff_bad3(clk, d, q, q_bar); input d, clk; output q, q_bar; reg q, q_bar; 11.10 always @(posedge clk) begin q <= d; q_bar <= ~q; module

11.1.2 (Flip flop) E d g e-tr ig g er ed D F lip -f lop w ith sy n c h r on ou s a c tive-low r eset module dff_sync_rst(clk, d, rst_n, q, qb); input clk, d, rst_n; output q, qb; reg q; assign qb = ~q; always @(posedge clk) // include only clk begin if(!rst_n) // active-low reset q <= 1'b0; else q <= d; module 11.11

11.1.2 (Flip flop) E d g e-tr ig g er ed D F lip -f lop w ith sy n c h r on ou s a c tive-low r eset 11.11

11.1.2 (Flip flop) Edge-t r i gger ed D F l i p -f l o p w i t h a s y n c h r o n o u s a c t i v e-l o w r es et module dff_async_rst(clk, d, rst_n, q, qb); input clk, d, rst_n; output q, qb; reg q; assign qb = ~q; always @(posedge clk or negedge rst_n) // both clk and rst_n begin if(!rst_n) // active-low reset q <= 1'b0; else q <= d; module 11.12

11.1.2 (Flip flop) Edge-t r i gger ed D F l i p -f l o p w i t h a s y n c h r o n o u s a c t i v e-l o w r es et 11.12

11.1.2 (Flip flop) D V er ilog H D L,. a c tive-h ig h D a c tive-h ig h D a c tive-low D a c tive-h ig h D a c tive-h ig h D a c tive-low D

11.1.2 (Flip flop) b loc k in g module seq_blk(clk, a, b, c, d, e, y); input clk, a, b, c, d, e; output y; reg m, n, y; always @(posedge clk) begin m = ~(a & b); n = c d; y = ~(m n e); module 11.13 Flip Flop

11.1.2 (Flip flop) n on b loc k in g module seq_nonblk(clk, a, b, c, d, e, y); input clk, a, b, c, d, e; output y; reg m, n, y; always @(posedge clk) begin m <= ~(a & b); n <= c d; y <= ~(m n e); module Flip Flop 11.14 Flip Flop Flip Flop

11.1.2 (Flip flop) 1 1.1 5 1 1.1 3 b loc k in g. 1 1.1 3,,. module seq_blk2(clk, a, b, c, d, e, y); input clk, a, b, c, d, e; output y; reg m, n, y; 11.15 always @(posedge clk) begin y = ~(m n e); m = ~(a & b); n = c d; module

11.2 Blocking Nonblocking b loc k in g module blk1(clk, d, q3); input clk; output q3; input d; reg q3, q2, q1, q0; always @(posedge clk) begin q0 = d; q1 = q0; q2 = q1; q3 = q2; module 11.16(a) module blk2(clk, d, q3); input clk; output q3; input d; reg q3, q2, q1, q0; always @(posedge clk) begin q3 = q2; q2 = q1; q1 = q0; q0 = d; module 11.16(b) Flip Flop Flip Flop Flip Flop Flip Flop Flip Flop Shift register

11.2 Blocking Nonblocking n on b loc k in g module non_blk1(clk, d, q3); input clk; output q3; input d; reg q3, q2, q1, q0; always @(posedge clk) begin q0 <= d; q1 <= q0; q2 <= q1; q3 <= q2; module 11.17(a) module non_blk2(clk, d, q3); input clk; output q3; input d; reg q3, q2, q1, q0; always @(posedge clk) begin q3 <= q2; q2 <= q1; q1 <= q0; q0 <= d; module 11.17(b) Flip Flop Flip Flop Flip Flop Flip Flop

11.2 Blocking Nonblocking -1 a l w a y s n o n b l o c k i n g. -2 a l w a y s b l o c k i n g.

11.2 Blocking Nonblocking -3 a l w a y s n o n b l o c k i n g.

11.2 Blocking Nonblocking -4 a l w a y s b l o c k i n g n o n b l o c k i n g. module ba_nba1(q, a, b, clk, rst_n); output q; input a, b, rst_n, clk; reg q, tmp; always @(posedge clk or negedge rst_n) if(!rst_n) q <= 1'b0; else begin tmp = a & b; q <= tmp; module module ba_nba2(q, a, b, clk, rst_n); output q; input a, b, rst_n, clk; reg q, tmp; always @(posedge clk or negedge rst_n) if(!rst_n) q = 1'b0; //blocking else begin tmp = a & b; q <= tmp; //nonblocking module Bad Coding 11.18(a) 11.18(b)

11.2 Blocking Nonblocking module ba_nba3(q, a, b, clk, rst_n); output q; input a, b, rst_n, clk; reg q; always @(posedge clk or negedge rst_n) if(!rst_n) q <= 1'b0; else q <= a & b; module module ba_nba4(q, a, b, clk, rst_n); output q; input a, b, rst_n, clk; reg q; wire tmp; assign tmp = a & b; always @(posedge clk or negedge rst_n) if(!rst_n) q <= 1'b0; else q <= tmp; module Good Coding 11.18(c) 11.18(d)

11.2 Blocking Nonblocking -5 a l w a y s r e g. module badcode1(q, d1, d2, clk, rst_n); output q; input d1, d2, clk, rst_n; reg q; always @(posedge clk or negedge rst_n) if(!rst_n) q <= 1'b0; else q <= d1; always @(posedge clk or negedge rst_n) if(!rst_n) q <= 1'b0; else q <= d2; module 11.19 Multiple source driving

11.2 Blocking Nonblocking 1 1.2 0 ( a ), ( b ) y 1, y 2,. 1 1.2 0 ( a ), ( b ),,. module fbosc_blk(y1, y2, clk, rst); output y1, y2; input clk, rst; reg y1, y2; Blocking always @(posedge clk or posedge rst) if(rst) y1 = 0; // reset else y1 = y2; always @(posedge clk or posedge rst) if(rst) y2 = 1; // set else y2 = y1; module 11.20(a)

11.2 Blocking Nonblocking module fbosc_nonblk(y1, y2, clk, rst); output y1, y2; input clk, rst; reg y1, y2; Nonblocking always @(posedge clk or posedge rst) if(rst) y1 <= 0; // reset else y1 <= y2; always @(posedge clk or posedge rst) if(rst) y2 <= 1; // set else y2 <= y1; module 11.20(b)

11.3 n, u t ) n, P u t ) n, u t ) n, P u t ),,,, (Serial-I Serial-O (Serial-I arallel-o (P arallel-i Serial-O (P arallel-i arallel-o nonblocking,

11.3.1 - sout q[7] Q D q[2] Q D q[1] Q D q[0] Q D sin DFF DFF DFF DFF clk rst 11.17 - module shift_reg_nblk1(clk, rst, sin, sout); input clk, rst, sin; output sout; reg [7:0] q; assign sout = q[7]; always @(posedge clk) begin if(!rst) q <= 8'b0; else begin 11.21 q[0] <= sin; q[1] <= q[0]; q[2] <= q[1]; q[3] <= q[2]; q[4] <= q[3]; q[5] <= q[4]; q[6] <= q[5]; q[7] <= q[6]; module

11.3.1 - module shift_reg_nblk2(clk, rst, sin, sout); input clk, rst, sin; output sout; reg [7:0] q; assign sout = q[7]; always @(posedge clk) begin if(!rst) q <= 0; else begin q[0] <= sin; q[7:1] <= q[6:0]; module 11.22

11.3.1-11.22 11.17,. for

11.3.2 - - pout[8] din[8] pout[2] din[2] pout[1] din[1] pout[0] din[0] load MUX load MUX load MUX Q D Q D Q D Q D DFF DFF DFF DFF clk rst 11.19 -

11.3.2 - module pld_shift_reg(clk, rst, load, din, pout); input clk, rst, load; input [7:0] din; output [7:0] pout; reg [7:0] data_reg; assign pout = data_reg; always @(posedge clk) begin if(!rst) data_reg <= 0; else if(load) data_reg <= din; else data_reg <= data_reg << 1; module 11.23

11.3.2-11.23 8,.

11.3.2 - (w r= 0) (en = 0), d at a_ io in o u t rd w r 0. 11.1 clk rst (Active Low) en enable (Active Low) wr enable (Active Low) rd enable (Active Low) si so data_io / (inout)

11.3.2 - module shifter(clk, rst, en, wr, rd, si, so, data_io); parameter Len = 8; input clk, rst, en, wr, rd, si; output so; inout [Len-1:0] data_io; reg [Len-1:0] shift_reg; assign data_io =!rd? shift_reg : {Len{1'bz}}; assign so = shift_reg[7]; always @(posedge clk) begin if(!rst) shift_reg <= {Len{1'b0}}; else begin if(!en) begin shift_reg <= shift_reg << 1; shift_reg[0] <= si; else if(!wr) shift_reg <= data_io; module 11.24

11.3.2-11.24 ( )

11.3.2-11.24 ( )

11.3.2-1 1.2 4 /,.. clk rst (Active Low) en enable (Active Low) wr enable (Active Low) rd enable (Active Low) si so data_io / (inout) mode / (mode=0;, mode=1; )

11.3.3 ( L i n e a r F e e d b a c k S h i f t R e g i s t e r ; L F S R ) 2 N-, 2 N, ( p s e u d o-r a nd om s e q u e nce ), /,, ( d a t a int e gr it y ch e cks u m ) I C ( B u ilt -I n S e lf -T e s t ; B I S T ) d q d q d q d q d q d q d q d q sout DFF DFF DFF DFF DFF DFF DFF DFF clk rst 11.23 LFSR

11.3.3 ( L i n e a r F e e d b a c k S h i f t R e g i s t e r ; L F S R ) X O R L F S R : 0. 0, L F SR. X N O R L F S R : 1. 1, L F SR. 3 L F S R

11.3.3 3 L F S R module lfsr_bad1(q3, clk, pre_n); output q3; input clk, pre_n; reg q3, q2, q1; Bad Code assign n1 = q1 ^ q3; // Blocking always @(posedge clk or negedge pre_n) if(!pre_n) begin q3 = 1'b1; q2 = 1'b1; q1 = 1'b1; else begin q3 = q2; q2 = n1; q1 = q3; module 11.25(a)

11.3.3 3 L F S R module lfsr_good1(q3, clk, pre_n); output q3; input clk, pre_n; reg q3, q2, q1; // Nonblocking always @(posedge clk or negedge pre_n) if(!pre_n) begin q3 <= 1'b1; q2 <= 1'b1; q1 <= 1'b1; else begin q3 <= q2; q2 <= q1 ^ q3; q1 <= q3; module Good Code 11.25(b)

11.3.3 3 L F S R module lfsr_good2(q3, clk, pre_n); output q3; input clk, pre_n; reg q3, q2, q1; Good Code // Nonblocking always @(posedge clk or negedge pre_n) if(!pre_n) {q3,q2,q1} <= 3'b111; else {q3,q2,q1} <= {q2,(q1^q3),q3}; module 11.25(c)

11.3.3 3 LFSR module lfsr_bad2(q3, clk, pre_n); output q3; input clk, pre_n; reg q3, q2, q1; Bad Code always @(posedge clk or negedge pre_n) if(!pre_n) {q3,q2,q1} <= 3'b000; else {q3,q2,q1} <= {q2,(q1 ^ q3),q3}; module 11.25(d)

11.3.3 3 LFSR (a) (b) (c) (d) 11.25

11.3.3 1 1.2 3 8 L F S R,. d q d q d q d q d q d q d q d q sout DFF DFF DFF DFF DFF DFF DFF DFF clk rst 11.23

11.4 (Counter) (counter),, :, : ( r i p p l e c o u n t e r ) : :,

11.4 (Counter) 8 module counter_up(clk, rst, cnt); input clk, rst; output [7:0] cnt; reg [7:0] cnt; always @(posedge clk or negedge rst) begin if(!rst) cnt <= 0; else cnt <= cnt + 1; module 11.26

11.4 (Counter) 8 11.26 11.26

11.4 (Counter) Enable ( ac t i v e h i g h ) 8,. Enable en= 1, en= 0. Mode (mode=1) (mode=0) 8 /,. 11.13 11.14 8 (load=1) 8 /,.

11.4 (Counter) 1 / 1 0 ( f r e q u e n c y d i v i d e r ) module frq_div(mclk, rst, clk_div); input rst, mclk; output clk_div; reg [3:0] cnt; reg clk_div; always @(posedge mclk or posedge rst) begin if(!rst) begin cnt <= 0; clk_div <= 0; else begin if(cnt == 9) begin cnt <= 0; clk_div <= 1'b1; else begin clk_div <= 1'b0; cnt <= cnt + 1; module 11.27

11.4 (Counter) 1 / 1 0 ( f r e q u e n c y d i v i d e r ) 11.27 Duty cycle 50% 1/10,.

11.5 (FSM) ( F i ni t e S t at e M ac h i ne; F S M ) Moore : Mea l y : Mealy Next state logic ( ) State register ( ) Output logic ( ) 11.28

11.5 (FSM) 11.3 2 Gray Johnson One-hot 0 000 000 0000 00000001 1 001 001 0001 00000010 2 010 011 0011 00000100 3 011 010 0111 00001000 4 100 110 1111 00010000 5 101 111 1110 00100000 6 110 101 1100 01000000 7 111 100 1000 10000000

11.5 (FSM) ( F S M ) V eri l og. F S M, F S M. F S M parameter. define define, F S M. parameter F S M. F S M. F S M,.

11.5 (FSM) ( F S M ) 11.28 F S M 3 ( n e x t s t a t e l o g i c, s t a t e r e g i s t e r, o u t p u t l o g i c ) a l w a y s a s s i g n. FSM,.., t r a n s p a r e n t ( s t a t e o s c i l l a t i o n ). N e x t s t a t e l o g i c c a s e, F S M d e f a u l t.

11.5.1 Moore FSM 4 F S M

11.5.1 Moore FSM module fsm_ex1(clk, rst_n, go, ws, rd, ds); input clk, rst_n, go, ws; output rd, ds; parameter IDLE = 2'b00, READ = 2'b01, DLY = 2'b10, DONE = 2'b11; reg [1:0] state, next; assign always @(posedge clk or negedge rst_n) //State Register if(!rst_n) state <= IDLE; else state <= next; always @(state or go or ws) begin //Next State Logic next = 2'bx; case(state) IDLE : if(go) next = READ; else next = IDLE; READ : next = DLY; DLY : if(!ws) next = DONE; else next = READ; DONE : next = IDLE; case // Output Logic assign rd =((state==read) (state==dly)); assign ds =(state==done); module 11.28(a)

11.5.1 Moore FSM always module fsm_ex2(clk, rst_n, go, ws, rd, ds); input clk, rst_n, go, ws; output rd, ds; parameter IDLE = 2'b00, READ = 2'b01, DLY = 2'b10, DONE = 2'b11; reg [1:0] state, next; reg rd, ds; always @(posedge clk or negedge rst_n) //State Register if(!rst_n) state <= IDLE; else state <= next; 11.28(b)

11.5.1 Moore FSM //Next State and Output Logic always @(state or go or ws) begin next = 2'bx; rd = 1'b0; ds = 1'b0; case(state) IDLE : if(go) next = READ; else next = IDLE; READ : begin rd = 1'b1; next = DLY; DLY : begin rd = 1'b1; if(!ws) next = DONE; else next = READ; DONE : begin ds = 1'b1; next = IDLE; case module 11.28(b)

11.5.1 Moore FSM module fsm_ex3(clk, rst_n, go, ws, rd, ds); input clk, rst_n, go, ws; output rd, ds; // parameter IDLE = 2'b00, READ = 2'b01, DLY = 2'b10, DONE = 2'b11; reg [1:0] state, next; reg rd, ds; always @(posedge clk or negedge rst_n) //State Register if(!rst_n) state <= IDLE; else state <= next; always @(state or go or ws) begin // Next State Logic next = 2'bx; case(state) IDLE : if(go) next = READ; else next = IDLE; READ : next = DLY; DLY : if(!ws) next = DONE; else next = READ; DONE : next = IDLE; case 11.28(c)

11.5.1 Moore FSM //Output Logic and output register always @(posedge clk or negedge rst_n) if(!rst_n) begin ds <= 1'b0; rd <= 1'b0; else begin ds <= 1'b0; rd <= 1'b0; case(next) READ: rd <= 1'b1; DLY : rd <= 1'b1; DONE: ds <= 1'b1; case module 11.28(c)

11.5.1 Moore FSM 11.28 (a), (b) 11.28 (c)

11.5.1 Moore FSM Moore FSM,. reset out=0 ST0 out=1 ST1 bypass out=3 ST3 ST2 out=2 11.17 Moore FSM.

11.5.2 Mealy FSM 0 1 din_bit : 0 1 0 1 1 1 0 1 0 0 1 1 0 1 0 0 dout_bit : 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 reset start 0/0 1/0 rd0_once 0/0 1/0 rd1_once 0/1 0/0 1/0 0/0 1/0 1/1 rd0_twice rd1_twice

11.5.2 Mealy FSM module seq_det_mealy(clk, rst, din_bit, dout_bit); input clk, rst, din_bit; output dout_bit; reg [2:0] state_reg, next_state; // parameter parameter parameter parameter parameter start = 3'b000; rd0_once = 3'b001; rd1_once = 3'b010; rd0_twice = 3'b011; rd1_twice = 3'b100; 11.29

11.5.2 Mealy FSM //Next State Logic always @(state_reg or din_bit) begin case(state_reg) start : if (din_bit == 0) next_state <= rd0_once; else if(din_bit == 1) next_state <= rd1_once; else next_state <= start; rd0_once : if(din_bit == 0) next_state <= rd0_twice; else if(din_bit == 1) next_state <= rd1_once; else next_state <= start; rd0_twice : if(din_bit == 0) next_state <= rd0_twice; else if(din_bit == 1) next_state <= rd1_once; else next_state <= start; rd1_once : if(din_bit == 0) next_state <= rd0_once; else if(din_bit == 1) next_state <= rd1_twice; else next_state <= start; rd1_twice : if(din_bit == 0) next_state <= rd0_once; else if(din_bit == 1) next_state <= rd1_twice; else next_state <= start; default : next_state <= start; case 11.29

11.5.2 Mealy FSM //State Register always @(posedge clk or posedge rst) begin if(rst == 1) state_reg <= start; else state_reg <= next_state; //Output Logic assign dout_bit =(((state_reg == rd0_twice) &&(din_bit == 0) (state_reg == rd1_twice) &&(din_bit == 1)))? 1 : 0; module 11.29

11.5.2 Mealy FSM 11.29

11.5.2 Mealy FSM din_bit : 0 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 detect_out : 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1/0 reset start st4 0/0 0/0 st1 0/0 1/0 0/1 0/0 1/0 1/0 st3 1/0 st2

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