Vidyalankar S.E. Sem. III [INFT] Analog and Digital Circuits Prelim Question Paper Solution

. (a). (b) S.E. Sem. III [INFT] Analog and Digital Circuits Prelim Question Paper Solution Practical Features of OpAmp (A 74) i) Large voltage gain (of the order of 2 0 5 ) ii) Very high input resistance ( M to 0 M) iii) Low output resistance (0 to 00 ) iv) Non zero output offset voltage (as high supply voltage) v) High CMRR (80 20 db) vi) Small bandwidth (5 Hz approximately since the gain bandwidth product is a constant) vii) Finite slew rate (5 V/sec.) ~ V in Expression for output of basic integrator Fig.(a) The expression for output V 0 can be obtained by writing K c L equation at node V 2. I in = I B2 + I c Since I B2 = 0 I in = I c Vin V2 dvc CF R dt ( V C = V 2 V 0 ) Vin V2 d(v2 V 0) CF R dt However, V = V 2 = 0, because A is very large. Vin dv 0( ) CF R dt Zi i (s) R R F C F R 0 M = R V cc -V CC Fig. (a) : Practical Integrator R L Zi i (s) V 0 = Vdt in RC F 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln

: S.E. ADC Gain (db) 00 Basic integrator response 80 60 40 20 0 f Rf db R 0 f Ideal response of practical integrator RF db 3dB Ri 0 2 f 0 3 f 0 4 f 0 5 f Fig. (b) : Frequency response of basic and practical integrator Integrate both sides with respect to time t. Vin d dt C F ( V 0) R dt V0 Vindt (A) RC F The equation (A) shows that output voltage is directly proportional to time constant R F C F.. (c) (i) Supply voltage rejection ratio The power supply rejection ration PSRR is the ratio of the change in input offset voltage to the corresponding change in one powersupply voltage, with all remaining power voltages held constant (ii) CMRR : F When same input voltages are applied to the two terminals, the opamp is said to be working in common mode. Since opamp amplifies only the difference, no common mode signal appear at the output. But due to some imperfections in the opamp, some common mode signal appears at the output and that voltage gain. A c = V oc / V c A d = V od / V d CMRR is defined as the ratio of differential gain to common mode gain and is usually expressed in db. CMRR = 20 log 0 A d / A c db Usually high values of CMRR is preferred and it is a function of frequency. It decreases as frequency increases. f c Actual response of practical integrator Relative frequency 2 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln

Prelim Question Paper Solution (iii) Slew rate Slew rate is the maximum rate of charge of output voltage with respect to time. It is expressed in volts/sec. Ideally, an opamp should have infinite slew rate. For 74, slew rate is 0.5 Volts/sec. Let, V = V sint dv o dt o S = m = V. Cost m dv dt o max = V 2f V m max m S = 2f max V max Volts/seconds. Slew rate is a large signal phenomenon. A large signal is one whose amplitude is comparable to the power supply voltages. Slew rate is caused by current limiting and saturation of internal stages of the opamp. When a high frequency large signal is applied, the resulting current is the maximum current available to charge the compensation capacitance network. The capacitor require a finite amount of time to charge and discharge. The rate dvc I at which voltage across the capacitor rises is dt c. If slew rate is exceeded, distortion will happen. Thus slew rate limiting is caused by capacitor charging rate, in which voltage across the capacitor is the output voltage. V in. (d) Error Correcting Codes An efficient method would be not only to detect the code but also to correct it. The most popular error correcting code is the Hamming Code. It was discovered by R.W. Hamming in 950. The basic of hamming code is, it uses Parity bit, set for even parity over a selected bits. The parity bits are placed at bit positions which are powers of 2 i.e. 2 0, 2, 2 2, 2 n. The 7 bit hamming code format is given as follows. 2 0, 2, 2 2, 2 n where D = data bits D 7 = MSB, D 3 = LSB Total 4 data bits are present. P = Parity bits P 4, P 2, P total 3 bits. This is also called (7, 4) hamming code. Normally hamming code is represented by (n, k), where n = total number of bits and k = Total number of data bit. m = n k = Number of Parity bits. In our case n = 7, k = 4, m = n k = 7 4 = 3. C o/p 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln 3

: S.E. ADC 2. (a) Working : Let us consider 4 Data Bits (D, D2, D3, D4). We introduce 3 additional party bits (P, P2, P3). The parity bits are paired along with the data bits to form a 7 bit number. This 7 bit number is transmitted as a group. (T7, T6, T5, T4, T3, T2, T) Transmitted Bit T 7 T 6 T 5 T 4 T 3 T 2 T Data Bit D 4 D 3 D 2 D Parity Bit P 3 P 2 P Group X X X X Group 2 X X X X Group 3 X X X X If we assume that there is an error in only one bit position, then each bit is a member of more than groups. Hence the error bit can be detected easily. Consider a Case D4 D3 D2 D = 0 If we consider odd parity D 4 = D 3 = D 2 = 0 D = P = (To make the combination D, D2 and D4 Odd parity) P2 = 0 (To make the combination D, D3 and D4 Odd Parity) P3 = (To make the combination D2, D3 and D4 Odd Parity) Output = 0 0 Y A BC ABD ABCD Y A B C ABD ABCD (De-Morgaon Law : BC B C ) Express it in standard SOP form : () Find the missing literal for each term : Y = A B C ABD ABCD B,C,D A,C,D A,B,D C no missing literal (2) AND each term with (missing literal + its complement) Y = A(B B)(C C)(D D) B(A A)(C C)(D D) C(A A)(B B)(D D) ABD(C C) ABCD (3) Simplify the expression to get the standard SOP Y = A(B B)(CD CD CD CD) B(A A)(CD CD CD CD) C(A A)(BD BD BD BD) ABCD ABCD ABCD = A[(BCD BCD BCD BCD) BCD BCD BCD BCD] B[(ACD ACD ACD ACD) ACD ACD ACD ACD] C[(ABD ABD ABD ABD) ABD ABD ABD ABD] ABCD ABCD ABCD = ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD 4 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln

Prelim Question Paper Solution = ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD CD CD CD CD CD AB 00 0 0 AB 00 AB 0 AB AB 0 y = C A B Step : Logic diagram, y = C A B C B A 2 3 Step 2 : AND-OR-NOT into NAND-NAND logic Replace entry OR by a bubbled OR entry invertes by a NAND inverter to get NAND-NAND logic C B A Step 3 : Draw circuit using only NAND gates C B A 0 4 2 5 3 0 3 7 5 2 8 9 0 2 6 3 4 0 y y y = A B C 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln 5

: S.E. ADC 2. (b) For a 2-bit comparator, each input word is 2-bit long. The truth table of a 2-bit comparator is shown in table. Table : Truth table for a 2-bit comparator. Inputs Outputs A A 0 B B 0 A < B A = B A > B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 K-maps : For A < B AAB 0 0 AB B B 0 A A 0 00 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 (a) K-map for output A < B ABB 0 0 The K-maps for the three outputs and corresponding simplified expressions are shown in figure (a), (b) and (c) A < B = AAB AB ABB 0 0 0 0 For A < B B B 0 AABB 0 0 AABB 0 0 A A 0 00 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AABB 0 0 (b) K-map for output A = B AABB 0 0 6 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln

For A > B Simplified expression : A > B = ABB 0 0 AAB 0 0 A B ABB 0 0 B B 0 A A 0 00 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 AB (c) K-map for output A > B Simplification for output A = B : Refer the K-map for output A = B shown in Fig.(b) Prelim Question Paper Solution The expression for A = B is given by (A = B) = AA 0BB 0 AA 0BB 0 AA 0BB 0 AA 0BB 0 = AB 0 0 (AB AB) AB 0 0(AB 0 AB) = (ABA B ) (A0B0 A0B 0) = (A B ) (A B ) where = EX-NOR 0 0 AAB 0 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln 7

: S.E. ADC Logic diagram for a two bit comparator : The logic diagram for the 2-bit digital comparator is shown in figure. 3. (a) Fig.: Logic diagram for 2-bit comparator. Monostable Multivibrator using 555 Timer The monostable multivibrator has only one stable state and one quasi stable state and it requires triggering. It is often called as oneshot multivibrator. It is a pulse generating circuit in which the duration of the pulse is determined by the RC network connected externally to the timer circuit. The following figure shows the arrangement for monostable multivibrator. (a) Operation Monostable multivibrator has one quasi-stable (unstable) state and one stable state. In the stable state output is at ground potential (0V). This is because the Flip Flop output holds the transistor Q ON [Because SET(s) is low] and thus capacitor C is shorted out to ground. 8 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln

Prelim Question Paper Solution (b) Circuit diagram V CC R A 8 4 6 7 IC 555 5 (c) Waveforms However upon application of a negative trigger pulse to pin 2, and when this Trigger Input Output W/F Capacitor voltage C 0.0 F (C) negative trigger pulse goes below 3 V CC. The lower comparator (LC) output (s) becomes HIGH. Thus Q will be 0 and output will be high. This Q will make transistor Q OFF and short circuit across capacitor (C) is released. The capacitor C now starts charging up towards V CC through R A. 3 2 Output Fig. (a) : Pin diagram monostable multivibrator T Trigger input V CC V 3 CC 0 + V CC t p V CC V CC V CC 2 = V 3 CC Fig. (b) : Input and output waveforms 0 V V CC 0 V 0 V 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln 9

: S.E. ADC However when the voltage across the capacitor equals 2 3 V CC. Comparator (UC) output switches from low to high, [R = ] which in turn drives the output to its low state via the output of the Flip Flop. At the same time, the output of the Flip Flop turns transistors Q ON and hence capacitor C rapidly discharges through the transistor. The output of the monostable remains low until a trigger pulse is again applied. Then the cycle repeats. Fig. (b) shows the trigger input, output voltage and capacitor voltage waveforms. 3. (b) Master Slave JK Flip Flop : ) Figure shows the master slave JK flip flop. 2) It is a combination of a clocked JK latch and clocked SR latch. 3) The clocked JK latch as the master and the clocked SR latch acts as the slave. 4) Master is positive level triggered. But due to the presence of the inverter in the clock line, the slave will respond to the negative level. 5) Hence when the clock = 0 (low level) the slave is active and the master is inactive. Fig. : Master slave JK FF 6) Table gives truth table of master slave JK flip flop. Table : Truth table of master slave JK FF Case Inputs Outputs Remark CLK J K Q n+ Q n+ I 0 0 Q n Q n No change II () 0 0 Q n Q n No change III () 0 0 Reset IV () 0 0 Set V () Q n Q n Toggle Operation : We will discuss the operation of the master slave JK FF with reference to its truth table. We must always remember one important thing that in the positive half cycle of the clock, the master is active and in the negative half cycle, the slave is active. This is shown in figure 2. 0 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln

Prelim Question Paper Solution Case I : Clock = x, J = K = 0 i) For clock =, the master is active, slave inactive. As J = K = 0. Outputs of master i.e. Q and Q will not change. Hence the S and R inputs to the slave will remain unchanged. ii) As soon as clock = 0, the slave becomes active and master is inactive. But since the S and R inputs have not changed, the slave outputs will also remain unchanged. The outputs will no change if J = K = 0 Case II : Clock =, J = K = 0 This condition has been already discussed in case I. Case III: Clock =, J = 0 and K = Clock = : Master active, slave inactive. Outputs of the master become Q = 0 and Q =. That means S = 0 and R = Clock = 0 : Slave active, master inactive. Outputs of the slave become Q = 0 and Q = Again if clock = : Master active, slave inactive. Even with the changed outputs Q = 0 and Q = fed back to master, its output will Q = 0 and Q =. That means S = 0 and R =. Hence with clock = 0 and slave becoming active, the outputs of slave will remain Q = 0 and Q =. Thus we get a stable output from the Master slave. Case IV : CLK =, J =, K = 0 Clock = : Master active, slave inactive. Outputs of master become Q = and Q = 0 i.e. S =, R = 0. Clock = 0 : Master inactive, slave active. Outputs of slave become Q = and Q = 0. Again if clock = then it can be shown that the outputs of the slave are stabilized to Q = and Q = 0. Fig. 2 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln

: S.E. ADC Case V : CLK =, J =, K = Clock J K Master output Q or S Slave output Q or R Slave output Q Fig. 3 : Waveforms of master slave JK flip flop Clock = : Master active, slave inactive. Outputs of master will toggle. So S and R also will be inverted. Clock = 0 : Master inactive, slave active. Outputs of the slave will toggle. These changed output are returned back to the master inputs. But since clock = 0, the master is still inactive. So it does not respond to these changed outputs. This avoids the multiple toggling which leads to the race around condition. Thus the master slave flip flop will avoid the rave around condition. The waveforms for the master slave flipflop are shown in figure 3. Observations from the waveforms : We can make the following important observations from the waveforms of the master slave JK FF. The slave always follows the master, after a delay of half cycle clock period. The multiple toggling or the race around condition is successfully avoided. 2 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln

4. (a) Prelim Question Paper Solution Bidirectional shift register : ) If a binary number is shifted left by one position then it is equivalent to multiplying the original number by 2. Similarly if a binary number is shifted right by one position then it is equivalent to dividing the original number by 2. 2) Hence if we want to use the shift register to multiply and divide the given binary number, then we should be able to move the data in either left or right direction. 3) Such a register is called as a bi-directional register. A four bit bi-directional shift register is shown in figure. 4) There are two serial inputs namely the serial right shift data input D R and the serial left shift data input D L alongwith a Mode select input (M). Serial shift right input D R CLK CLR Fig.: A 4-bit bi-directional shift register Serial shift left input D L 5) Operation : With M = : Shift right operation i) If M =, then the AND gates, 3, 5 and 7 are enabled whereas the remaining AND gates 2, 4, 6 and 8 will be disabled. ii) Hence the data at D R (shift right input) is shifted to right bit by bit from FF-3 to FF-0 on the application of clock pulses. iii) Thus with M = we get the serial right shift operation. With M = 0 : Shift left operation i) When the mode control M is connected to 0 then the AND gates 2, 4, 6 and 8 are enabled while, 3, 5, 7 are disabled. ii) Hence the data at D L (shift left input) is shifted left bit by bit from FF-0 to FF-3 on application of the clock pulses. iii) Thus with M = 0 we get the serial left shift operation. iv) Note that M should be changed only when CLK = 0, otherwise the data stored in the register may be altered. Applications of Shift Registers : ) For temporary data storage 2) For multiplication and division 3) As a delay line 4) Serial to parallel coverter. 5) Parallel to serial converter 6) Ring counter 7) Twisted ring counter or Johnson counter 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln 3

: S.E. ADC 4. (b) 5. (a) Features of VHDL (Derived from Capablities) VHDL has powerful constructs VHDL language supports hierarchy(i.e modelled using a set of interconnected components) VHDL is not case sensitive VHDL supports both synchronous and asynchronous timing models. Concurrency timing and clocking can be modeled using VHDL VHDL is target independent VHDL supports design library VHDL has flexible design methodologies i.e. TOP DOWN, BOTTOM UP, MIXED The logical behavior and timing behavior of the design can be modeled using VHDL. VHDL is not technology specific i.e. VHDL is not dependent on the specific manufacturer i.e. XILINX or LATTICE. VHDL s technology specific feature allows to specify components from various vendors VHDL also allows the user to specify his own data type and component. Stability/Instability factors I = f(i,v, ) C CO BE I CO is temperature dependent, I CO increases with temperature, it doubles for every 0C rise in temperature. V BE is temperature dependent, V BE decreases with temperature, it decreases by 2.5 mv/c. varies from device to device, also increases by % for every C rise in temperature. Hence with changes in I CO, V BE and, I C of a transistor can change. The change in I C with respect to above three parameters are measured in terms of stability / instability factor. Lower the value of these parameters, better the stability of the biasing circuit. a) Temperature stability factor S I /S It is defined as the ratio of the change in the collector current to the change in the leakage current, keeping and V BE constant. S I = IC,, V BE constant. I CO b) Voltage stability factor S V /S It is defined as the ratio of the change in the collector current to the change in the base emitter voltage keeping I CO and constant. IC S V = V, I CO, constant. BE 4 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln

Prelim Question Paper Solution c) stability factor S /S It is defined as the ratio of the change in the collector current to the change in the value of, keeping I CO and V BE constant. 5. (b) S = I C, I CO, V BE constant. the total change in I C is given by I C = SI I CO + SV V BE + S Expression for S I By definition, I S I = C ICO I C = B,, V BE constant. In a transistor, I + ( + ) I CBO I CBO I CO I C = I B + ( + ) I CO Differentiate with respect to I C IB ICO = ( ) IC IC IB = ( + ) IC SI S I = IB I F (A, B, C, D) = m (0,, 5, 7, 8, 3, 4,7) Truth table : D 0 D D 2 D 3 AB 0 2 3 AB 4 5 6 7 AB 8 9 0 A B 2 3 4 5 D 0 = AB AB = B(AA) D 0 = B D = A B AB AB = A(BB)AB = A AB D = AB D 2 = A B D 3 = AB C The variables C, D are applied to select lines S, S 0 respectively. 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln 5

: S.E. ADC Realization using gates B D 0 6. (a) C THE INVERTING AMPLIFIER The inverting amplifier circuit is as shown in Figure. R R R V I + (a) (b) Fig. : Inverting amplifier and its circuit model for analysis Analysis : Referring to the equivalent circuit of (b), we have v p = 0 () To find V N : Let V 0 be grounded R2 V N = VI (2) (R R 2) Now consider only V 0 be present in the circuit, R V N 2 = V0 (3) (R R ) 2 By superposition principle, V = V V N A N N2 R 2 = VI V0 (RR) 2 (RR) 2 Now v0 a(vp v N) yields V 0 = a VI V0 R R 2 R2 R V0 Solving for ratio and rearranging, V I + R V V D D 2 D 3 + 4 : MUX S S 0 D + + av D V V N R (4) (5) F V 6 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln

Prelim Question Paper Solution V0 R2 A = = V I R (6) R2 R a The above equation reveals that the circuit of figure (a) is an amplifier with gain A. However, the gain A is negative indicating that the polarity of V 0 will be opposite to that of V I. Hence, the circuit is referred to as inverting amplifier. 6. (b) IDEAL CHARACTERISTICS OF OPAMP An ideal opamp exhibits the following electrical characteristics. (a) Infinite voltage gain (b) Infinite input resistance R i, so that any signal source can drive it and there is no loading of the preceding stage. (c) Zero output resistance R 0, so that output can drive an infinite number of other devices. (d) Zero offset voltage, hence can be direct coupled. (e) Infinite BW, so that frequencies from 0 to Hz can be amplified without attenuation. (f) Infinite CMRR, so that common mode noise is zero. (g) Infinite slew rate, so that output voltage changes simultaneously with input. 6. (c) Introduction to SE\NE 555 Timer IC The 555 timer is a highly stable device used to produce a delay of few microseconds to several hours. It is used in applications such as oscillators, pulse generators, ramp and square wave generators, astable and monostable multivibrators, traffic light control and burglar alarms, DC to DC conveter, Digital logic probes, Analog frequency meter, temperature measurement and control, voltage regulator etc. Features of Timer IC 555 ) It is available in 8 pin metal can, an 8 pin mini DIP. or a 4 pin DIP. package. 2) It operates on supply voltage between +5V to +8V. 3) Adjustable duty cycle. 4) It can be used to provide a delay time from few microseconds to several hours. 5) Capacity to source or sink current of 200 ma. 6) Output can drive TTL, CMOS logic families. 7) It has high temperature stability and is designed to operate in the temperature range of 55C to 25C. 8) It is basically operated in two modes. i.e. either as a monostable (one shot) multivibrator or as an astable (free running) multivibrator. 9) 555 timer is reliable, low cost, easy to design like general purpose OP-AMP 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln 7

: S.E. ADC Block Diagram 8 + V CC Threshold V CC Control 0 Discharge Function of each pin of 555 Timer Pin : Ground : All voltages are measured with respect to this terminal Pin 2 : Trigger : When the trigger terminal voltage goes below /3 V cc, the lower comparator output switches high, flip flop is set, Q = 0,the output of timer becomes high, the discharge transistor turns off, the external timing capacitor starts charging. Pin 3 : Output : There are two ways a load can be connected to output terminal. () Between pin no. 3 and supply voltage. (2) Between pin no. 3 and ground. 555 2 V CC 6 5 Trigger 7 8 5 k 2/3 V CC UC 5 k /3 V CC LC 5 k output = (V CC ) I Q Ground RL Sourcing current R S Q n V ref Q 2 buffer Inverter Functional Block Diagram of 555 IC Timer V CC 8 3 4 Reset 3 Output I output = 0 Sinking current RL When the output is low, the load current flows through the load connected between pin 3 and V CC into the output terminal and is called sink current. However, when the output is low, the current flowing through the grounded load is zero for this reason the load connected between pin 3 and V CC is called 8 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln

6. (d) Prelim Question Paper Solution normally ON load and that connected between pin 3 and ground is called normally OFF load. Similarly when the output is high current through normally ON load connection will be zero. Since both the pins are at equipotential. Whereas the output terminal supplies current to the normally OFF load this current is called the source current. The maximum value of sink or source current is 200 ma. T Flip Flop to D Flip Flop Conversion Step : Write the truth table : The truth table is as given in Table. Table : Truth table for T FF to D FF conversion Inputs Output D Previous state Next state Q n+ T Q n 0 0 0 0 0 0 0 0 Step 2 : K maps simplification and logic diagram : The K map is shown in Figure (a) and the logic diagram is given in Figure (b). For output T Q n D 0 0 0 0 D Q T = DQn DQn T = D Qn (a) K map for D output n D Q n D T Given T FF CLK (b) Logic diagram of T to D flip flop conversion Q Q D flip flop Outputs 3/Engg/SE/Pre Pap/203/INFT/ADC_Soln 9