Beyond Si: Opportunities and Challenges for CMOS Technology Based on High-Mobility Channel Materials T.P. Ma Yale University Acknowledgments: Abigail Lubow, Xiao Sun, Shufeng Ren
Switching Speed of CMOS Transistor Intrinsic Speed ~ Id/Qsw I d = W/L µ C (Vg V T ) 2 = W/L µ C V 2 W: Channel Width L: Channel Length µ: Carrier Mobility Dielectric Constant C: Inversion Cap ~ /tox Vg: Gate Voltage VT: Threshold Voltage Oxide Thickness
Iddq (A / um / stage) Measured CMOS Inverter Speed vs Id (65 nm Node Si Technology) Intrinsic Speed ~ Id/Qsw 1E-6 Baseline PDSOI esige SOI 1E-7 1E-8 2.5 3.0 3.5 4.0 4.5 5.0 Inverter Delay (ps)
Channel Length Evolution
The silicon transistor in manufacturing 45 nm technology 20 nm Gate Length generation
Gate Oxide Scaling
Microprocessor Speed (1971-2010)
90, 65, 45 nm Generation Gate Oxide
Tunneling current increases exponentially with decreasing oxide thickness Taur, IEEE Spectrum, July 1999
Source: Intel webpages
Chip Power Density with Scaling 1000 Exponential Rise of Power Density Nuclear reactor Rocket nozzle Sun s surface Watts/cm 2 100 10 i386 Hot plate i486 Pentium Pentium III Pentium II Pentium Pro Pentium 4 1 1.5m 1m 0.7m 0.5m 0.35m 0.25m 0.18m 0.13m 0.1m 0.07m From New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies Fred Pollack, Intel Corp. Micro32 conference key note - 1999.
Clock Speed (MHz) Microprocessor Clock Speed leveled off between 90 and 45nm node Cooling costs are limiting clock speeds. 10 4 1.0E+04 Source: Intel 10 3 1.0E+03 10 2 1.0E+02 1990 1995 2000 2005 2010
Switching Speed of MOS Transistor Speed Increases with I d = W/L µcv 2 Dielectric constant where C = /d Oxide thickness To Increase C: Decrease d Increase ( = k o ) High-k dielectrics
Intel News Release 1/27/2007 Intel's Transistor Technology Breakthrough Represents Biggest Change to Computer Chips In 40 Years; Intel embraces high-k gate dielectrics for 45 nm C SANTA CLARA, Calif., Jan. 27, 2007 In one of the biggest advancements in fundamental transistor design, Intel Corporation today revealed that it is using two dramatically new materials to build the insulating walls and switching gates of its 45 nanometer (nm) transistors. Hundreds of millions of these microscopic transistors or switches will be inside the next generation Intel Core 2 Duo, Intel Core 2 Quad and Xeon families of multi-core processors. The company also said it has five early-version products up and running - - the first of fifteen 45nm processor products planned from Intel.
Si CMOS Innovation Will Continue: up to 2020 2007 2009 2012 2015 2018 2021 Physical Gate length 37 nm 25 nm 18 nm 13 nm 9 nm 6 nm Ultra thin SOI High k gate dielectric Double-Gate CMOS FinFET doped channel raised source/drain Strained Si, Ge, SiGe Gate buried oxide halo depletion layer isolation Silicon Substrate buried oxide isolation Silicon Substrate Source Drain In general, growing power dissipation and increasing process variability will be addressed by introduction of new materials and device structures, and by design innovations in circuits
Switching Speed of CMOS Transistor Intrinsic Speed ~ Id/Qsw I d = W/L µ C (Vg V T ) 2 = W/L µ C V 2 W: Channel Width L: Channel Length µ: Carrier Mobility Dielectric Constant C: Inversion Cap ~ /tox Vg: Gate Voltage VT: Threshold Voltage Oxide Thickness
Beyond-Silicon CMOS: (Beyond 2020) High-Mobility Channels Carbone Nanotubes (CNTs) Graphene III-V Semiconductors
CNTs as High-mobility Materials 1D, quasi-ballistic transport faster small m*, high mobility (Courtesy Jia Chen) Si (p): Si (n): InSb (n): NT (p ): Mobility at RT 450 cm 2 /Vs 1,500 cm 2 /Vs 77,000 cm 2 /Vs >100,000 cm 2 /Vs! Dürkop, et al., Nano Letters (2004)
Ids (A) Ids(A) CNT Transistor Characteristics (Courtesy Jia Chen, IBM) -6 Before Doping 10 10-6 Post Doping 10-8 10-10 10-12 Vds (V) -0.1-0.2-0.3-0.4-0.5 S=200 mv/dec 10-8 10-10 10-12 Vds (V) -0.1-0.2-0.3-0.4-0.5 S=85mV/dec -1.6-0.8 0.0 0.8 1.6 Vgs (V) I on improved by 2 orders of magnitude Leakage completely suppressed S decreased from 200 to 85 mv/dec dopant : ( C H ) O SbCl 2 5 3 6-1.6-0.8 0.0 0.8 1.6 Vgs(V) Pd + + + SbCl 6 - Interface Dipole J. Chen, et al Appl. Phys. Lett. 2005 + + SbCl 6 - F M > F M, favors h + injection, suppresses e - injection
1998 1998 Source Nanotube The evolution of CNT-FETs 2001 2001 2002 2002 SiO 2 Drain CNT-FET logic gate Top-gated CNTFET 2004 (Courtesy Jia Chen) 2006 2006 Self-aligned and doped CNTFET Fully-integrated CMOS circuit
Carbon Nanotube: W 200nm Unlikely to Succeed Si as Mainstream CMOS Channel, Due to Difficulties with Selective Growth of CNT on Si Placement of CNTs on Selected Sites Low-resistance Contacts Process Integration
Beyond-Silicon CMOS: (By 2020) High-Mobility Channels Carbone Nanotubes Graphene III-V Semiconductors
What is graphene? Single sheet of 2d carbon atoms arranged in a honeycomb lattice 2.5Å Figure from Ishigami et al. Figures from Geim et al. 0 d: Fullerenes Smalley (1985) 1 d: Nanotubes Iijima (1991) 2 d: Graphene Andre Geim (2004) 3 d: Graphite
Hall Mobility Measured in Top-gate Graphene MOSFET Avouris et.al., IEDM Dec. 2010
Back-Gate Graphene MOSFET (IBM-MIT Group) Y.Q. Wu et.al, IEDM, Dec. 2010
Output Characteristics of IBM Graphene MOSFET with L=70nm Vbg: 0-25V Y.Q. Wu et.al, IEDM, Dec. 2010
Cross-section of Front-Gate Graphene MOSFET (IBM-MIT) Y.Q. Wu et.al, IEDM, Dec. 2010
Transfer Characteristics of Graphene MOSFET (IBM-MIT) Y.Q. Wu et.al, IEDM, Dec. 2010
Graphene MOSFET (Columbia Group) Measured Modeled for R=0
Graphene: Unlikely to Succeed Si as Mainstream CMOS Channel, Due to Difficulties with Growth of High-quality Graphene on Si Adequate Bandgap for CMOS Logic (Too much off current) Low-resistance Contacts Process Integration Competition against III-V channels
Beyond-Silicon CMOS: (By 2020) High-Mobility Channels Carbone Nanotubes Graphene III-V Semiconductors
Properties of Si, Ge, GaAs, InGaAs, and InAs Si Ge GaAs In 0.53 Ga 0.47 As InAs E g (ev) 1.1 0.66 1.4 0.75 0.35 µ n (cm 2 /v- s) 1,350 3,900 4,600 >8,000 40,000 µ p (cm 2 /v- s) 480 1,900 500 350 <500 m*/m o 0.165 0.12 0.067 0.041 0.024
Drift velocity (cm/s) Drift velocity vs. electric field 10 8 10 7 10 6 theory Ge In 0.53 Ga 0.47 As InP GaAs Si theory InAs breakdown field 10 5 10 2 10 3 10 4 10 5 10 6 Electric field (V/cm) (From Jerry Woodall)
Effect of Density of States High electron mobility in III-V semiconductor is primarily due to low effective mass Which gives rise to low density of states Which negatively impacts the drive current
Inversion electron concentration (#/cm 3 ) Inversion Electron Spatial Distribution EOT=2nm 2.5E+20 Si 2E+20 Ge 1.5E+20 1E+20 5E+19 GaAs InGaAs Si Nen(x) Ge Nen(x) GaAs Nen(x) InAs Nen(x) InGaAs Nen(x) 0 InAs 0 1 2 3 4 5 6 7 8 9 10 Distance from SiO 2- semiconductor interface (nm)
Capacitance (F/cm2) 1nm EOT p-si, p-gaas, InGaAs, InAs 0.000003 Si 0.0000025 0.000002 0.0000015 0.000001 GaAs InAs Si Tox=1nm GaAs Tox=1nm InGaAs Tox=1nm InAs Tox=1nm 0.0000005 Id = W/LµCV 2-3 -2-1 0 1 2 Volts (V) 0
Capacitance (F/cm2) 0.5nm EOT p-si, p-gaas, InGaAs and InAs 6.00E-06 5.00E-06 Si 4.00E-06 3.00E-06 2.00E-06 GaAs Si Tox=0.5nm GaAs Tox=0.5nm InGaAs Tox=0.5nm InAs Tox=0.5nm 1.00E-06 InAs Id = W/LµCV 2 0.00E+00-3 -2-1 0 1 2 Volts (V)
N-Channel EOT=1nm m (cm /V- s) C inv m *C inv Si 1350 2.73E - 6 3.68E - 3 1 Ge 3600 2.73E - 6 9.84E - 3 2.67 GaAs 8000 1.78E - 6 1.42E - 2 3.86 InGaAs 11200 1.66E - 6 1.86E - 2 5.05 InAs 30000 1.32E - 6 3.95E - 2 10.7 2 EOT=0.5nm m (cm/v- s) C inv m *C inv Si 1350 4.82E - 6 6.51E - 3 1 Ge 3600 4.62E - 6 1.66E - 2 2.55 GaAs 8000 2.55E - 6 2.04E - 2 3.13 InGaAs 11200 2.18E - 6 2.44E - 2 3.75 InAs 30000 1.64E - 6 4.93E - 2 7.57 Id ~ µcinv Id ratio Id ratio
Id~mu*Cinv Comparison of Id in N-Channel Si, Ge, GaAs, InGaAs, and InAs N-Channel 6.00E-02 5.00E-02 InAs 4.00E-02 InAs InGaAs 3.00E-02 2.00E-02 GaAs InGaAs GaAs Ge Si 1.00E-02 Ge 0.00E+00 Si 0 0.5 1 1.5 2 2.5 3 EOT (nm)
Peide Ye, et.al, IEDM, 12-2009
TiN/Al 2 O 3 /GGO/In 0.53 Ga 0.47 As/InP MOSFET Raynien Kwo and Minghwei Hong, MRS Fall Meeting, 12-2009 Output Characteristics t TiN = 160nm, t Al2 O 3 =2nm, t GGO =5nm, W/L=10/1μm I d,max =1.05 ma/mm @V g =2V,V d =2V g m,max =714 ms/mm @ V d =2V, V g =0.85V V th ~0.3V, m FE =1306 cm 2 /V.s, f t ~18 GHz Sub-threshold swing~ 104 mv/dec 41
Performance Trend: Laterally Scalable Kwo and Hong, MRS Fall Meeting, 12-2009 Si NMOSFET 32nm node L g ~18nm (0.018μm) I d,sat ~1.5 ma/mm Estimated Performance for L g =0.5mm L g 20mm 10mm 8mm 4mm 2mm 1mm 0.5mm I d,sat (ma/mm) g m,max (ms/mm) June 23, 2008 60 104 140 263 506 1050 34 56 81 152 320 714 DRC ~2mA/mm ~1.4mS/mm
InGaAs Quantum Well FET (Intel-IQE)
InGaAs Quantum Well FET Long Channel (Intel-IQE)
InGaAs Quantum Well FET Short Channel (Intel-IQE)
Most Promising Post-Silicon CMOS: High-Mobility III-V MOSFET s Challenges (Research Opportunities): Gate dielectrics on III-V Growth of III-V on Si P-channel drive current (hole mobility) Process integration
Problem with III-V PMOSFET Low Hole Mobility!! Si Ge GaAs In 0.53 Ga 0.47 As InAs E g (ev) 1.1 0.66 1.4 0.75 0.35 µ n (cm 2 /v- s) 1,350 3,900 4,600 7,800 40,000 µ p (cm 2 /v- s) 480 1,900 500 350 <500 m*/m o 0.165 0.12 0.067 0.041 0.024 CMOS requires very fat PMOSFET!!
Novel Solution All N-Channel CMOS Logic!! (Unipolar Logic)
Conventional CMOS Inverter output
Unipolar CMOS Inverter Based on Double-gate NMOSFETs No current path between VDD and Ground in either steady state
Unipolar 2-Input NOR Gate Same structure can serve as NAND, AND, OR, simply by exchanging A,B with ~A,~B; and exchanging GND with Vdd.
Unipolar CMOS for TFT Difficulty in realizing P-N FET pairs - ZnO, IGZO - Amorphous Si - Many organic systems Large disparity in electron/hole mobility in many TFT s
Example of TFT with IGZO on Polyimide N.C. Su, et al, IEEE EDL,,VOL.31, NO.7, JULY 2010
Transistor Characteristics of IGZO TFT N.C. Su, et al, IEEE EDL,,VOL.31, NO.7, JULY 2010
Dual-Rail Logic NAND Gate Based on IGZO TFT V A V DD V out TaN HfLaO V B V A VB
Dual-Rail Logic NAND Gate Based on Double Gate Design
Summary Conventional Si CMOS scaling will end III-V semiconductors are most promising One major challenge for III-V CMOS: * P-Channel (low hole mobility) Unipolar CMOS a possible solution TFT technology may also benefit from Unipolar CMOS