Chapter 5 igital systems digital system is any machine that processes information encoded in the form of digits. Modern digital systems use binary digits, encoded as voltage levels. Two voltage levels, representing logical values true and false, are manipulated by electronic logic gates according to the formal mathematical rules of oolean algebra. The logic gates implement digital circuits that perform all of the algorithms necessary to make the computer work. digital computer is therefore nothing more than a sufficiently large assembly of logic gates, with appropriate connections between them. 5. oolean algebra oolean algebra is a mathematical formalism for describing logical relations between variables. oolean variables have one of two possible values, either true or false. In digital circuit design they are denoted as and, respectively. 5.. Negation, conjunction and disjunction The three main operations of oolean algebra are negation, conjunction, and disjuntion. X X Y X + Y ( not X ) is the negation of X, true only if X is false. ( X and Y ) is the conjunction of X and Y, true only if both X and Y are true. ( X or Y ) is the disjunction of X and Y, true if either X or Y (or both) are true. Negation is sometimes written as x or x, conjunction as x ^ y or xy ( logical product ), and disjunction as x _ y ( logical sum ). truth table presents a oolean operator or function as a list of input value(s) vs. the output value(s). NOT X X N X Y X Y OR X Y X + Y When appearing together in a oolean equation, logical has higher precedence than +. oth are commutative (the order of inputs has no effect on the result). 25
5..2 Other logical operations In adition to and and or, two other operations are particularly useful. X Y ( X exclusive-or Y ), also written X 6 Y or X Y Y, is true only when X and Y are different. inary arithmetic [ecs. 3., 3.2] depends heavily on this function, which is equivalent to modulo-2 addition and subtraction. The negation of exclusive-or is also useful in the detection of signed overflow. X Y ( X equivalent Y or X exclusive-nor Y ), also written X, Y, is true only when X and Y are the same. oth exclusive-or and equivalence are commutative. XOR X Y X Y XNOR X Y X Y 5.2 Canonical, disjunctive, and conjunctive forms truth table is the canonical form of a oolean function. It is the most basic definition of the function, and identifies it uniquely. Each row of a truth table defines the output for a specific combination of input variable values. Each row has a corresponding minterm which is the conjunction of the row s input variables, where those whose value should be are negated. minterm is true if and only if the inputs match the values specified by its row. The disjunction of all minterms for which the functions s output is true uniquely defines the function and is called the canonical disjunctive normal form of the function. C minterm maxterm C + + C (a) C + + C (b) C + + C (c) C + + C (d) C + + C (e) C + + C (f) C + + C (g) C + + C (h) =( + C) disjunctive normal form = C (a) + C (b) + C (d) + C (e) + C (g) + C (h) conjunctive normal form = ( + + C ) (c) ( + + C ) (f) Each row also has a corresponding maxterm which is the disjunction of the row s input variables, where those whose value should be are negated. maxterm is false if and only if the inputs match the values specified by its row. The conjunction of all maxterms for which the functions s output is false also uniquely defines the function and is called the canonical conjunctive normal form of the function. 26
5.3 implifying oolean expressions everal simplifying substitutions can be made anywhere in a oolean expression. P P involution P P P + P identity P P + domination P P P P + P P idempotency P P P + P complementation (contradiction, tautology) P ( + R) (P )+(P R) P +( R) (P + ) (P + R) distributivity P (P + ) P P +(P ) P absorption (P ) P + (P + ) P e Morgans s laws 5.3. e Morgan s laws N is only when both of its inputs are. OR is only when both of its inputs are. Either can be transformed into the other by negating the inputs and output. The resulting equivalences are called e Morgan s laws. P (P + ) P + (P ) OR N negative logic OR X Y X + Y X Y X Y X + Y (X + Y ) 5.3.2 Karnaugh maps Representing the function as a multi-dimensional truth table facilitates finding a minimal expression for it. that is not yet part of a group is chosen, and a rectangluar group of s formed around it covering as much of the table as possible. The inputs that correspond to the s in the group are then considered. P P = = = + pair of adjacent s in the group must share a single input variable whose value is irrelevant, and which can be disregarded. ny remaining inputs must be either or. minterm is constructed from only these relevant inputs by negating any whose value must be and then forming a conjunction. The process repeats until all s in the function belong to at least one group. The disjunction of the resulting minterms completely defines the function, and is the minimal disjunctive normal form of the function. (urther optimisation may be possible if additional primitive oolean operations are available, such as exclusiveor [ec. 5..2].) s should always be combined into a group, even if that means groups overlap, as the resulting function will be simpler. 27
P R P = = = + minimal R = = = + correct, but not minimal Multiple variables can share a single axis, but adjacent rows and columns must always differ from their neighbours in exactly one input. Labelling the multi-variable axes with a minimum-change code (e.g., Gray code [ec...]) guarantees this property. C C C P P = C, =, R = C = C + + C C R Rows and columns wrap horizontally and vertically. The first and last element in a column or row have the outside edge of the table in common, and are adjacent to each other. C = 5. igital circuits Logical operations in oolean expressions correspond to logic gates in digital circuits. Variables in oolean expressions correspond to signals connecting gates together. If a variable x is true, we say that the corresponding signal X is active or asserted. If a variable x is false, we say that the corresponding signal X is inactive or de-asserted. signal encodes one bit of information as a voltage level. Most digital circuits use a lower voltage to represent and a higher voltage to represent. The state of a signals can therefore also be described as high or low. In positive logic the binary digits and are interpreted as oolean values false and true, respectively. Positive logic therefore has signals that are active high. signal that is asserted is represented by. In negative logic the opposite interpretation is made. Negative logic has signals that are active low. signal that is asserted is represented by. Various conventions are used to indicate an active low signal, including appending N (for negative ) to its name ( ENLEN ), or writing a bar over its name ( ENLE ). 28
given signal can have multiple interpretations, mixing positive and negative logic at the same time. oth interpretations are simultaneously correct, but the preferred interpretation depends on context. In signed addition, CRRY is a positive logic, active-high signal. In signed subtraction, the exact same signal is called ORROW and is a negative logic, activelow signal. 5.. Gates, signals and busses Eight gates are omni-present in digital circuits. basic oolean logical operations Y X X = Y NOT inverter, negates a signal X X = N logical conjunction X X = + OR logical disjunction X X = XOR logical exclusive-or oolean logical operations with inverted outputs Y X X = Y buffer, copies input signal to output X X =( ) NN N with inverted output X X =( + ) NOR OR with inverted output X X = XNOR XOR with inverted output circle on an output indicates that the signal is inverted as it leaves the gate. Inputs are sometimes marked with a similar circle, indicating that the signal is inverted as it enters the gate (or, equivalently, that it is interpreted internally as an active-low signal). ignal connections are indicated with lines. When two signal lines cross, there is no connection between them unless a dot is placed at the point where they intersect. usses (data, address, etc.) can be represented with a single line (sometimes thicker than normal) with a tick mark indicating how many individual, parallel signals are contained within it. no connection 2 3 LOGIC connected to LOGIC 5.5 Combinational logic circuits Combinational logic is stateless. Outputs are a pure function of the inputs. 5.5. Logical bitwise operations The LU works with word-sized data, consisting of N bits arranged in parallel. Placing N copies of a simple gate in parallel transforms the oolean logical operation into a bit-wise operation working on the N bits of an entire word at the same time. 29
X X N- X N-2 X X N N ~X N- ~X N-2 ~X ~X ~X & ll the logic functions required from the LU can be implemented this way. Choosing between the many results is necessary if the LU is to generate a single output. multiplexer produces one value by choosing among N input values. Like any other logic circuit, a single-bit version can be paralelled to make a N-bit multiplexer. 2-way multiplexer uses a -bit number EL to control which one of two inputs or is connected the output Y. -way multiplexer uses a 2-bit number EL to control which one of four inputs,, C or is connected to the output Y. MUX 2! EL Y 9 > = Y= >; 9 > = Y= >; Y =(EL )+(EL ) MUX 2! EL Y MUX! EL C Y x x x x x x x x x x x x x x x x x x x x x x x x x= don t care Y= Y= Y=C Y= MUX! EL Y C The idea generalises to multiplexers where a M-bit number selects which one of 2 M input signals is connected to the output signal. If the inputs are N-bit busses, the device is a N-bit, 2 M -way multiplexer. EL EL EL & EL & MUX 2! Y C Y Y Y Y 2 2 Y 2 OP OP examples of functional block symbols for various multiplexers NOT N OR XOR 6 6 6 6 6 LU-OUT 5.5.2 rithmetic operations dding two single-bit values and requires a single XOR gate to generate the sum. Generating the carry out C requires an additional N gate. This two-gate half adder circuit is insufficient for multi-bit addition because it ignores carry in. C = C = everal more gates are needed to add three single-bit values, and. The sum output should be if an odd number of inputs are. The carry out should be if two or more inputs are. C 3
C I C O =( )+( )+(C IN )+(C IN ) =( )+( )+( ) =( )+( ( + )) The disjunctive normal form of the full adder is not optimal. The sum output is better implemented as a three-way exclusive-or. The cary output can be implemented with one fewer gates by noting that ( )+( ( + )) = ( )+( ( )), and that has already been computed for the sum (and is therefore available free of charge ). C IN = =( )+( ( )) optimised logic logic circuit functional block Instead of writing the entire adder circuit each time it is used, an abstract functional block symbol is defined to represent it. When a gate input changes there is a small propagation delay before the corresponding change occurs at the output. The number of levels of gates in a complex circuit determines its overall propagation delay. ull adders have three levels of gates, and therefore approximately three gate delays of propagation delay. (Even building the disjunction normal form of the circuit cannot escape this because of the inverters required on some of the inputs.) Placing N full adders in parallel creates a N-bit binary adder. N N- N- N-2 N-2 N N N- N-2 dding another level of abstraction, a functional block is defined to represent the entire N- bit adder as a single symbol within the circuit hierarchy. The carry out of any bit position is not available until three gate delays after its inputs have stabilised. ince the carry out of stage n is connected to the carry in to stage n +, the carry ripples through the adder from right to left, taking three gate delays per bit. The sum and carry from the most significant bit can take up to 3N gate delays to become stable. This circuit is called a ripple carry adder. N ubtraction ubtraction is performed by inverting the subtrahend (forming the one s complement) and setting the carry in to, indicating not borrow [ec. 3.2]. 3
a + b, /U = s = a + b +, /U = s = a + b + c, /U = a + b + c, /U = 3 3 2 2 3 3 2 2 /U /U C/ 3 2 add and subtract (without carry) 3 2 add-with-carry and subtract-with-carry Connecting the carry in to /U performs the operation without carry or borrow. Connecting it to the carry flag of the PR [ec..3] allows the operation to be continued over multiple words, but requires the progammer to set the carry appropriately before operating on the least significant word. Providing both behaviours requires an additional 2-way multiplexer, selecting carry in appropriately. hift and rotation Logical shifts move a word linearly left or right. Zeroes are shifted in to the word to fill the empty spaces. its that are shifted out of the word are either lost, or can (for single-bit shifts) be moved into the carry flag. logical shift left logical shift right rithmetic shifts are similar, but preserve the sign bit when shifting to the right. rithmetic left shifts are logical left shifts that also check for signed overflow [ec. 3.]. arithmetic shift right (positive) arithmetic shift right (negative) Rotation is a circular movement of bits. its that are moved out of the word on one side are copied back in on the opposite side. Many architectures place the lsb and msb immediately adjacent to each other. rotate left rotate right 32
rchitectures with single-bit rotations can insert the carry flag between them; rotation shifts a bit from the carry flag into the word at one end, and shifts a bit out of the word into the carry flag at the other end. rotate left through carry C C rotate right through carry 5.6 equential logic circuits equential logic has outputs that depend not only on the present inputs but also on the sequence of past inputs. equential logic is stateful (remembering the input history), whereas combinational logic is stateless. gated transparent latch copies its input to its output while the gate input G is high. When G is low, the output remains stable and independent of. Latches are = latch G level-triggered. One way to construct a latch is to use feedback with a (combinational) 2-to- multiplexer. G equential logic depends on propagation delay to resolve apparent contradictions and ambiguities resulting from feedback. Two latches in series, the first with an inverted gate signal, create a -type flip-flop. is sampled on the rising edge of a clock signal, and the output is the most-recently sampled value of. G latch G latch = lip-flops are edge-triggered, and are a fundamental component of synchronous logic. 5.6. ynchronous logic ynchronous logic uses a global clock to synchronise changes in state. everal flip-flops in parallel, with a single shared clock, create a register. 3 3 2 2 Registers placed between combinational circuits hold input values steady between rising edges of the clock, giving combinational logic time to settle before the next clock cycle begins. Introducing feedback into a synchronous circuit creates a state machine, such as a counter. = 3 3 2 2 = -bit synchronous binary counter...5 CLK 2 3 2 3 5 6 7 8 9 2 3 5 33