High Performance Silicon Gate CMOS

Similar documents
With LSTTL Compatible Inputs High Performance Silicon Gate CMOS

High Performance Silicon Gate CMOS

High Performance Silicon Gate CMOS

High Performance Silicon Gate CMOS

High Performance Silicon Gate CMOS

High Performance Silicon Gate CMOS

MC74HC04A. Hex Inverter. High Performance Silicon Gate CMOS

MC74HC00A. Quad 2 Input NAND Gate. High Performance Silicon Gate CMOS

High Performance Silicon Gate CMOS

High Performance Silicon Gate CMOS

FACT DATA 5-1 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

FACT DATA 5-1 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

MC74VHC08. Quad 2-Input AND Gate

High Performance Silicon Gate CMOS

High Performance Silicon Gate CMOS

MC74LVX00. Quad 2-Input NAND Gate. With 5 V Tolerant Inputs

74HC00. Quad 2-Input NAND Gate. High-Performance Silicon-Gate CMOS

74HCT32. Quad 2 Input OR Gate with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS

NL17SHT08. 2-Input AND Gate / CMOS Logic Level Shifter

74HC32. Quad 2 Input OR Gate. High Performance Silicon Gate CMOS

Schmitt Trigger Inputs Outputs Source/Sink 24 ma ACT132 Has TTL Compatible Inputs. ORDERING INFORMATION

NL27WZ14. Dual Schmitt Trigger Inverter

MC74HC04A. Hex Inverter. High Performance Silicon Gate CMOS

High Performance Silicon Gate CMOS

SEMICONDUCTOR TECHNICAL DATA

SEMICONDUCTOR TECHNICAL DATA

NL17SH02. Single 2-Input NOR Gate

Figure 1. Pinout: 16 Lead Packages Conductors (Top View) ORDERING INFORMATION Figure 2. Logic Symbol PIN ASSIGNMENT

SEMICONDUCTOR TECHNICAL DATA

SEMICONDUCTOR TECHNICAL DATA

MC74VHC132. Quad 2 Input NAND Schmitt Trigger

MC74LVX32. Quad 2-Input OR Gate. With 5 V Tolerant Inputs

MC74HC08A. Quad 2-Input AND Gate High Performance Silicon Gate CMOS

High Performance Silicon Gate CMOS

NL17SV16. Ultra-Low Voltage Buffer

74HC of 8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS

MC74HC86A. Quad 2 Input Exclusive OR Gate. High Performance Silicon Gate CMOS

MC74VHC14. Hex Schmitt Inverter

MC74HC132A. Quad 2 Input NAND Gate with Schmitt Trigger Inputs. High Performance Silicon Gate CMOS

MC74HC32A. Quad 2-Input OR Gate. High Performance Silicon Gate CMOS

NL37WZ07. Triple Buffer with Open Drain Outputs

NL27WZ00. Dual 2 Input NAND Gate L1 D

MC74AC132, MC74ACT132. Quad 2 Input NAND Schmitt Trigger

MC74AC138, MC74ACT of 8 Decoder/Demultiplexer

MC74VHC540. Octal Bus Buffer. Inverting

SEMICONDUCTOR TECHNICAL DATA

MC74VHC00. Quad 2-Input NAND Gate

MC74VHC1GT00. Single 2-Input NAND Gate/ CMOS Logic Level Shifter. LSTTL Compatible Inputs

SN54/74LS145 1-OF-10 DECODER/DRIVER OPEN-COLLECTOR 1-OF-10 DECODER/ DRIVER OPEN-COLLECTOR FAST AND LS TTL DATA 5-240

NL27WZ08. Dual 2-Input AND Gate. The NL27WZ08 is a high performance dual 2 input AND Gate operating from a 1.65 V to 5.5 V supply.

SN74LS132MEL. Quad 2 Input Schmitt Trigger NAND Gate LOW POWER SCHOTTKY

MC14070B, MC14077B CMOS SSI. Quad Exclusive OR and NOR Gates

High Performance Silicon Gate CMOS

NL17SZ08. Single 2-Input AND Gate

SN74LS74AMEL LOW POWER SCHOTTKY

MC74VHCT86A/D. Quad 2-Input XOR Gate / CMOS Logic Level Shifter with LSTTL Compatible Inputs

NL27WZ14. Dual Schmitt-Trigger Inverter

SN74LS157MEL. Quad 2 Input Multiplexer LOW POWER SCHOTTKY

NL27WZ08. Dual 2-Input AND Gate. The NL27WZ08 is a high performance dual 2 input AND Gate operating from a 1.65 V to 5.5 V supply.

NLU1G00 Single 2-Input NAND Gate The NLU1G00 MiniGate is an advanced high speed CMOS 2 input NAND gate in ultra small footprint. The NLU1G00 input and

SEMICONDUCTOR TECHNICAL DATA

SN74LS157MEL LOW POWER SCHOTTKY

with LSTTL Compatible Inputs

SN74LS42MEL. One of Ten Decoder LOW POWER SCHOTTKY

74HC244 Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver

SN74LS145MEL. 1 of 10 Decoder/Driver Open Collector LOW POWER SCHOTTKY

MC74VHC1GT08 2-Input AND Gate/CMOS Logic Level Shifter

MC74HCT366A. Hex 3-State Inverting Buffer with Common Enables and LSTTL Compatible Inputs. High Performance Silicon Gate CMOS

MC74HCT14A. Hex Schmitt-Trigger Inverter with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS

MC74HC08A. Quad 2 Input AND Gate High Performance Silicon Gate CMOS

MC Bit Magnitude Comparator

MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10173L AWLYYWW

The MC10107 is a triple 2 input exclusive OR/NOR gate. P D = 40 mw typ/gate (No Load) t pd = 2.8 ns typ t r, t f = 2.

MC74VHC574. Octal D Type Flip Flop with 3 State Output. ON Semiconductor

MC74HC244A Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver

MC74LCX138MEL. With 5 V Tolerant Inputs

NE522 High Speed Dual Differential Comparator/Sense Amp

MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620

74VHC08 Quad 2-Input AND Gate

MC74VHC00. Quad 2-Input NAND Gate

MARKING DIAGRAMS ORDERING INFORMATION VHC139 AWLYYWW SOIC 16 D SUFFIX CASE 751B VHC 139 AWLYWW TSSOP 16 DT SUFFIX CASE 948F

MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620

LOW POWER SCHOTTKY. MODE SELECT TRUTH TABLE ORDERING INFORMATION GUARANTEED OPERATING RANGES OPERATING MODE

MC74HC00A. Quad 2 Input NAND Gate. High Performance Silicon Gate CMOS

SN74LS125A, SN74LS126A. Quad 3 State Buffers LOW POWER SCHOTTKY. LS125A LS126A TRUTH TABLES ORDERING INFORMATION

MC74VHCT244A. Octal Bus Buffer/Line Driver with 3-State Outputs

NL27WZ00. Dual 2-Input NAND Gate. The NL27WZ00 is a high performance dual 2 input NAND Gate operating from a 1.65 V to 5.5 V supply.

MC74AC109, MC74ACT109. Dual JK Positive Edge Triggered Flip Flop

MARKING DIAGRAMS LOGIC DIAGRAM DIP PIN ASSIGNMENT TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10161L AWLYYWW

LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION

MC74HCT138A. 1 of 8 Decoder/ Demultiplexer with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS

NLSV2T Bit Dual-Supply Inverting Level Translator

74HCT245. Octal 3-State Noninverting Bus Transceiver with LSTTL-Compatible Inputs. High-Performance Silicon-Gate CMOS

MARKING DIAGRAMS LOGIC DIAGRAM DIP PIN ASSIGNMENT ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10138L AWLYYWW

MARKING DIAGRAMS ORDERING INFORMATION Figure 1. Pin Assignment VHCT139A AWLYYWW SOIC 16 D SUFFIX CASE 751B VHCT139A AWLYWW

Dual 4-Input AND Gate

Triple 3-Input NOR Gate

NL27WZU04. Dual Unbuffered Inverter

LOW POWER SCHOTTKY. MARKING DIAGRAMS GUARANTEED OPERATING RANGES ORDERING INFORMATION. SN74LS37xN AWLYYWW PDIP 20 N SUFFIX CASE 738

LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION PLASTIC N SUFFIX CASE 648

Transcription:

SEIONDUTOR TEHNI DT High Performance Silicon Gate OS The 54/74H4 is identical in pinout to the S4, S04 and the H04. The device inputs are compatible with Standard OS outputs; with pullup resistors, they are compatible with STT outputs. The H4 is useful to square up slow input rise and fall times. Due to hysteresis voltage of the Schmitt trigger, the H4 finds applications in noisy environments. Output Drive apability: 0 STT oads Outputs Directly Interface to OS, NOS and TT Operating oltage Range: 2 to 6 ow Input urrent: µ High Noise Immunity haracteristic of OS Devices In ompliance With the JEDE Standard No. 7 Requirements hip omplexity: 60 ETs or 5 Equivalent Gates 2 3 OGI DIGR 2 4 Y Y2 4 4 4 4 N SUIX PSTI PGE SE 646 06 D SUIX SOI PGE SE 75 03 ORDERING INORTION 54HXXJ 74HXXN 74HXXD 74HXXDT J SUIX ERI PGE SE 632 08 DT SUIX TSSOP PGE SE 948G 0 eramic Plastic SOI TSSOP 3 5 6 Y3 UNTION TBE 4 5 9 8 0 Y4 Y5 Y = Pin 4 = Pin 7 = GND Inputs H Outputs Y H 6 3 2 Y6 Pinout: 4 ead Packages (Top iew) 6 Y6 5 Y5 4 Y4 4 3 2 0 9 8 2 3 4 5 6 7 Y 2 Y2 3 Y3 GND 0/95 otorola, Inc. 995 RE 7

54/74H4 ÎÎ XIU RTINGS* Symbol Parameter alue Unit ÎÎ ÎÎ D Supply oltage (Referenced to GND) 0.5 to + 7.0 ÎÎ in D Input oltage (Referenced to GND) 0.5 to + 0.5 ÎÎ out D Output oltage (Referenced to GND) 0.5 to + 0.5 ÎÎ I ÎÎ in D Input urrent, per Pin ± 20 m ÎÎ I ÎÎ out D Output urrent, per Pin ± 25 m ÎÎ I ÎÎ D Supply urrent, and GND Pins ± 50 m ÎÎ ÎÎ P D Power Dissipation in Still ir, Plastic or eramic DIP 750 mw SOI Package 500 TSSOP Package Tstg 450 Storage Temperature Range 65 to + 50 ÎÎ ÎÎ T ead Temperature, mm from ase for 0 SecondsÎÎ ÎÎ Plastic DIP, SOI or TSSOP Package 260 ÎÎ eramic DIP 300 * aximum Ratings are those values beyond which damage to the device may occur. unctional operation should be restricted to the Recommended Operating onditions. Derating Plastic DIP: 0 mw/ from 65 to 25 eramic DIP: 0 mw/ from 00 to 25 SOI Package: 7 mw/ from 65 to 25 TSSOP Package: 6. mw/ from 65 to 25 or high frequency or heavy load considerations, see hapter 2 of the otorola High Speed OS Data Book (D29/D). REOENDED OPERTING ONDITIONS Symbol Parameter in Î ax Unit D Supply oltage (Referenced to GND) in, out D Input oltage, Output oltage (Referenced to Î Î 0 Î GND) T Operating Temperature Range, ll Package Types 55 Î + 25 Î tr, tf Î Input Rise/all Time = Î Î (igure ) = 0 No imit* ns 0 No imit* * When in = 50%, I > m = 0 No imit* This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. or proper operation, in and out should be constrained to the range GND (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or ). Unused outputs must be left open. OTORO 2 High Speed OS ogic Data D29 Rev 6

54/74H4 D HRTERISTIS (oltages Referenced to GND) Symbol Parameter ondition T+ max T+ min T max T min Hmax Note 2 Hmin Note 2 OH O aximum Positive Going Input Threshold oltage inimum Positive Going Input Threshold oltage aximum Negative Going Input Threshold oltage inimum Negative Going Input Threshold oltage aximum Hysteresis oltage inimum Hysteresis oltage inimum High evel Output oltage aximum ow evel Output oltage out = out = out = out = out = or out = or in T min in T min in T+ max in T+ max Iout 2.4m Iout 4.0m Iout 5.2m Iout 2.4m Iout 4.0m Iout 5.2m Guaranteed imit 55 to 25 85 25 Unit Iin aximum Input eakage urrent in = or GND ± ±.0 ±.0 µ I aximum Quiescent Supply urrent (per Package) in = or GND Iout = 0µ.50 2.5 3.5 4.20.0.5 2.3 0.9.4 2.6 0.3 0.5 0.9.2.20.65 0 0.20 0.25 0.50.9 4.4 5.9 2.48 3.98 5.48 0.26 0.26 0.26.50 2.5 3.5 4.20 0.95.45 2.95 0.95.45 5 2.65 0.3 0.5 0.9.2.20.65 0 0.20 0.25 0.50.9 4.4 5.9 2.34 3.84 5.34 0.33 0.33 0.33.50 2.5 3.5 4.20 0.95.45 2.95 0.95.45 5 2.65 0.3 0.5 0.9.2.20.65 0 0.20 0.25 0.50.9 4.4 5.9 2.20 3.70 5.20.0 0 40 µ. Information on typical parametric values along with frequency or heavy load considerations can be found in hapter 2 of the otorola High Speed OS Data Book (D29/D). 2. Hmin > (T+ min) (T max); Hmax = (T+ max) (T min). High Speed OS ogic Data D29 Rev 6 3 OTORO

54/74H4 HRTERISTIS ( = 50p, Input tr = tf = 6ns) Symbol tph, tph tth, tth Parameter aximum Propagation Delay, Input or B to Output Y (igures and 2) aximum Output Transition Time, ny Output (igures and 2) Guaranteed imit 55 to 25 85 25 Unit in aximum Input apacitance 0 0 0 p NOTE: or propagation delays with loads other than 50 p, and information on typical parametric values, see hapter 2 of the otorola High Speed OS Data Book (D29/D). 75 30 5 3 75 27 5 3 95 40 9 6 95 32 9 6 Typical @ 25, = 5.0 PD Power Dissipation apacitance (Per Inverter)* 22 p * Used to determine the no load dynamic power consumption: PD = PD 2 f + I. or load considerations, see hapter 2 of the otorola High Speed OS Data Book (D29/D). 0 55 22 9 0 36 22 9 ns ns tf tr INPUT 90% 50% 0% GND tph tph OUTPUT Y 50% 0% 90% tth tth igure. Switching Waveforms TEST POINT DEIE UNDER TEST OUTPUT * *Includes all probe and jig capacitance igure 2. Test ircuit OTORO 4 High Speed OS ogic Data D29 Rev 6

54/74H4 T, TYPI INPUT THRESHOD OTGE (OTS) 4 3 2 (T+) (T ) 2 3 4 5 6, POWER SUPPY OTGE (OTS) Htyp Htyp = (T+ typ) (T typ) igure 3. Typical Input Threshold, T+, T versus Power Supply oltage Y (a) Schmitt Trigger Squares Up Inputs With Slow Rise and all Times (b) Schmitt Trigger Offers aximum Noise Immunity H H in T+ T in T+ T GND GND OH OH out out O O igure 4. Typical Schmitt Trigger pplications High Speed OS ogic Data D29 Rev 6 5 OTORO

54/74H4 OUTINE DIENSIONS J SUIX ERI DIP PGE SE 632 08 ISSUE Y -B- -T- SETING PNE 4 8 7 -- G N D 4 P J 4 P 0.25 (0.00) T S 0.25 (0.00) T B S NOTES:. DIENSIONING ND TOERNING PER NSI Y, 982. 2. ONTROING DIENSION: INH. 3. DIENSION TO ENTER O ED WHEN ORED PRE. 4. DIESNION Y NRROW TO 0.76 (0.030) WHERE THE ED ENTERS THE ERI BODY. DI B D G J N INHES IN X 0.750 0.785 0.245 0.280 55 0.200 0.05 0.020 0.055 0.065 00 BS 0.008 0.05 25 70 0.300 BS 0 0.020 5 0.040 IIETERS IN X 9.05 9.94 6.23 7. 3.94 5.08 0.39 0.50.40.65 2.54 BS 0.2 0.38 3.8 4.3 7.62 BS 0 5 0.5.0 4 8 7 H G D N B SETING PNE N SUIX PSTI DIP PGE SE 646 06 ISSUE J NOTES:. EDS WITHIN 3 (0.005) RDIUS O TRUE POSITION T SETING PNE T XIU TERI ONDITION. 2. DIENSION TO ENTER O EDS WHEN ORED PRE. 3. DIENSION B DOES NOT INUDE OD SH. 4. ROUNDED ORNERS OPTION. INHES IIETERS DI IN X IN X 0.75 0.770 8.6 9.56 B 0.240 0.260 6.0 6.60 45 85 3.69 4.69 D 0.05 0.02 0.38 0.53 0.040 0.070.02.78 G 00 BS 2.54 BS H 0.052 0.095.32 2.4 J 0.008 0.05 0.20 0.38 5 35 2.92 3.43 0.300 BS 7.62 BS 0 0 0 0 N 0.05 0.039 0.39.0 OTORO 6 High Speed OS ogic Data D29 Rev 6

54/74H4 OUTINE DIENSIONS D SUIX PSTI SOI PGE SE 75 03 ISSUE SETING PNE 4 G 7 8 B P 7 P D 4 P 0.25 (0.00) T B S S 0.25 (0.00) B R X 45 J NOTES:. DIENSIONING ND TOERNING PER NSI Y, 982. 2. ONTROING DIENSION: IIETER. 3. DIENSIONS ND B DO NOT INUDE OD PROTRUSION. 4. XIU OD PROTRUSION 5 (0.006) PER SIDE. 5. DIENSION D DOES NOT INUDE DBR PROTRUSION. OWBE DBR PROTRUSION SH BE 27 (0.005) TOT IN EXESS O THE D DIENSION T XIU TERI ONDITION. DI B D G J P R IIETERS IN X 8.55 8.75 3.80 4.00.35.75 0.35 0.49.25.27 BS 0.050 BS 0.25 0.008 0.25 0.004 7 0 6.20 0.228 0.50 0.00 9 0 0 5.80 0.25 INHES IN X 0.337 0.344 50 57 0.054 0.068 0.04 0.09 0.06 0.049 0.009 0.009 7 0.244 0.09 DT SUIX PSTI TSSOP PGE SE 948G 0 ISSUE O 5 (0.006) T 5 (0.006) T 0 (0.004) T SETING PNE U U S 2X /2 PIN IDENT. S D 4 G 4X RE 0 (0.004) T U S S 8 7 B U H N J J N DETI E DETI E 0.25 (0.00) ÇÇÇ ÉÉÉ ÇÇÇ SETION N N W NOTES:. DIENSIONING ND TOERNING PER NSI Y, 982. 2. ONTROING DIENSION: IIETER. 3. DIENSION DOES NOT INUDE OD SH, PROTRUSIONS OR GTE BURRS. OD SH OR GTE BURRS SH NOT EXEED 5 (0.006) PER SIDE. 4. DIENSION B DOES NOT INUDE INTERED SH OR PROTRUSION. INTERED SH OR PROTRUSION SH NOT EXEED 0.25 (0.00) PER SIDE. 5. DIENSION DOES NOT INUDE DBR PROTRUSION. OWBE DBR PROTRUSION SH BE 0.08 (0.003) TOT IN EXESS O THE DIENSION T XIU TERI ONDITION. 6. TERIN NUBERS RE SHOWN OR REERENE ONY. 7. DIENSION ND B RE TO BE DETERINED T DTU PNE W. IIETERS INHES DI IN X IN X 4.90 5.0 93 0.200 B 4.30 0 69 77.20 0.047 D 0.05 5 0.002 0.006 0.50 0.75 0.020 0.030 G 0.65 BS 0.026 BS H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J 0.09 6 0.004 0.006 9 0.30 0.007 0.02 9 0.25 0.007 0.00 6.40 BS 0.252 BS 0 8 0 8 High Speed OS ogic Data D29 Rev 6 7 OTORO

54/74H4 otorola reserves the right to make changes without further notice to any products herein. otorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does otorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different applications. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. otorola does not convey any license under its patent rights nor the rights of others. otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the otorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use otorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold otorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that otorola was negligent regarding the design or manufacture of the part. otorola and are registered trademarks of otorola, Inc. otorola, Inc. is an Equal Opportunity/ffirmative ction Employer. How to reach us: US/EUROPE: otorola iterature Distribution; JPN: Nippon otorola td.; Tatsumi SPD JD, Toshikatsu Otsuki, P.O. Box 2092; Phoenix, rizona 85036. 800 44 2447 6 Seibu Butsuryu enter, 3 4 2 Tatsumi oto u, Tokyo 35, Japan. 03 352 835 X: RX0@email.sps.mot.com TOUHTONE (602) 244 6609 HONG ONG: otorola Semiconductors H.. td.; 8B Tai Ping Industrial Park, INTERNET: http://design NET.com 5 Ting ok Road, Tai Po, N.T., Hong ong. 852 26629298 OTORO ODEINE 8 54/74H4/D High Speed OS ogic Data D29 Rev 6