CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp12 CMPEN 411 L17 S.1
This Lecture Reading Dynamic sequential circuits - Reading assignment Rabaey, et al, 7.3, 7.7 Timing issues, Intro to datapath design Next lecture - Reading assignment Rabaey, et al, 10.1-10.3.3; 11.1-11.2 Intro to datapath design - Reading assignment Rabaey, et al, 11.1-11.2 Adder design - Reading assignment Rabaey, et al, 11.3 Sp12 CMPEN 411 L17 S.2
Last Lecture: Static MS ET Implementation Master Slave I 2 T 2 I 3 I 5 T 4 I 6 Q Q M D I 1 T 1 T 3 I 4! Sp12 CMPEN 411 L17 S.3
Dynamic ET Flipflop master slave! D T 1 master transparent slave hold! C 1 Q M I 1 T I 2 Q 2! C 2 t su = t hold = t c-q = master hold slave transparent t pd_tx zero 2 t pd_inv + t pd_tx Sp12 CMPEN 411 L17 S.4
Pseudostatic Dynamic Latch Robustness considerations limit the use of dynamic FF s coupling between signal nets and internal storage nodes can inject significant noise and destroy the FF state leakage currents cause state to leak away with time internal dynamic nodes don t track fluctuations in V DD that reduces noise margins A simple fix is to make the circuit pseudostatic Q M Q! Add above logic added to all dynamic latches Sp12 CMPEN 411 L17 S.5
Dynamic ET FF Race Conditions! D T 1 C 1 Q M I 1 T I 2 Q 2! C 2 0-0 overlap race condition t overlap0-0 < t T1 + t I1 + t T2! 1-1 overlap race condition t overlap1-1 < t hold Sp12 CMPEN 411 L17 S.6
Fix 1: Dynamic Two-Phase ET FF Keep clock non-overlap large enough, but with 4 clock singals to route 1 2 D T 1!1 C 1 Q M I 1 T I 2 Q 2!2 C 2 master transparent slave hold 1 2 t non_overlap master hold slave transparent Sp12 CMPEN 411 L17 S.7
Fix 2: C 2 MOS (Clocked CMOS) ET Flipflop A clock-skew insensitive FF Master Slave M 2 M 6 D! M 4 M 3 Q M C 1! M 8 M 7 C 2 Q M 1 M 5! Sp12 CMPEN 411 L17 S.8
C 2 MOS (Clocked CMOS) ET Flipflop A clock-skew insensitive FF Master Slave M 2 M 6 D! off off M 4 M 3 on on Q M C 1! on on M 8 M 7 off off C 2 Q M 1 M 5 master transparent slave hold! master hold slave transparent Sp12 CMPEN 411 L17 S.9
C 2 MOS FF 0-0 Overlap Case Clock-skew insensitive as long as the rise and fall times of the clock edges are sufficiently small M 2 M 6 D 0 0 M 4 Q M C 1 M 8 C 2 Q M 1 M 5!! Sp12 CMPEN 411 L17 S.10
C 2 MOS FF 1-1 Overlap Case M 2 M 6 D Q M 1 1 C 1 M 3 M 7 C 2 Q M 1 M 5!! Sp12 CMPEN 411 L17 S.11
Fix 3: True Single Phase Clocked (TSPC) Latches Negative Latch Positive Latch In Q In Q hold when = 1 transparent when = 0 transparent when = 1 hold when = 0 Sp12 CMPEN 411 L17 S.12
Embedding Logic in TSPC Latch PUN A B In Q Q PDN A B Sp12 CMPEN 411 L17 S.13
TSPC ET FF Master Slave D on on on on Q off off Q M off off master transparent slave hold master hold slave transparent Sp12 CMPEN 411 L17 S.14
Choosing a Clocking Strategy Choosing the right clocking scheme affects the functionality, speed, and power of a circuit Two-phase designs + robust and conceptually simple - - need to generate and route two clock signals have to design to accommodate possible skew between the two clock signals Single phase designs + only need to generate and route one clock signal + supported by most automated design methodologies + don t have to worry about skew between the two clocks - have to have guaranteed slopes on the clock edges Sp12 CMPEN 411 L17 S.15
Review: Sequential Definitions Use two, level sensitive latches of opposite type to build one master-slave flipflop that changes state on a clock edge (when the slave is transparent) Static storage static uses a bistable element with feedback to store its state and thus preserves state as long as the power is on - Loading new data into the element: 1) cutting the feedback path (mux based); 2) overpowering the feedback path (SRAM based) Dynamic storage dynamic stores state on parasitic capacitors so the state held for only a period of time (milliseconds); requires periodic refresh dynamic is usually simpler (fewer transistors), higher speed, lower power but due to noise immunity issues always modify the circuit (by adding a feedback loop on the output) so that it is pseudostatic Sp12 CMPEN 411 L17 S.16
Timing Classifications Synchronous systems All memory elements in the system are simultaneously updated using a globally distributed periodic synchronization signal (i.e., a global clock signal) Functionality is ensure by strict constraints on the clock signal generation and distribution to minimize - Clock skew (spatial variations in clock edges) - Clock jitter (temporal variations in clock edges) Asynchronous systems Self-timed (controlled) systems No need for a globally distributed clock, but have asynchronous circuit overheads (handshaking logic, etc.) Hybrid systems Synchronization between different clock domains Interfacing between asynchronous and synchronous domains Sp12 CMPEN 411 L17 S.17
Review: Synchronous Timing Basics In D R1 Q Combinational logic D R2 Q t 1 t c-q, t su, t hold, t cdreg t plogic, t cdlogic Under ideal conditions (i.e., when t 1 = t 2 ) T t c-q + t plogic + t su t 2 Sp12 CMPEN 411 L17 S.18 t hold t cdlogic + t cdreg Under real conditions, the clock signal can have both spatial (clock skew) and temporal (clock jitter) variations skew is constant from cycle to cycle (by definition); skew can be positive (clock and data flowing in the same direction) or negative (clock and data flowing in opposite directions) jitter causes T to change on a cycle-by-cycle basis
Sources of Clock Skew and Jitter in Clock Network 1 clock generation PLL 4 power supply 2 3 clock drivers interconnect 6 capacitive load 7 capacitive coupling Skew manufacturing device variations in clock drivers interconnect variations environmental variations (power supply and temperature) 5 temperature Jitter clock generation capacitive loading and coupling environmental variations (power supply and temperature) Sp12 CMPEN 411 L17 S.19
Positive Clock Skew Clock and data flow in the same direction In D R1 1 Q t 1 > 0 Combinational logic T T + delay 3 R2 D Q t 2 2 4 T : + t hold T + t c-q + t plogic + t su so T t c-q + t plogic + t su - t hold : > 0: Improves performance, but makes t hold harder to meet. If t hold is not met (race conditions), the circuit malfunctions independent of the clock period! Sp12 CMPEN 411 L17 S.20 t hold + t cdlogic + t cdreg so t hold t cdlogic + t cdreg -
Negative Clock Skew Clock and data flow in opposite directions In D R1 Q t 1 Combinational logic T delay R2 D Q t 2 1 T + 3 2 < 0 4 T : T + t c-q + t plogic + t su so T t c-q + t plogic + t su - t hold : t hold + t cdlogic + t cdreg so t hold t cdlogic + t cdreg - < 0: Degrades performance, but t hold is easier to meet (eliminating race conditions) Sp12 CMPEN 411 L17 S.21
Clock Jitter Jitter causes T to vary on a cycle-bycycle basis In R1 Combinational logic t T -t jitter +t jitter T : T - 2t jitter t c-q + t plogic + t su so T t c-q + t plogic + t su + 2t jitter Jitter directly reduces the performance of a sequential circuit Sp12 CMPEN 411 L17 S.22
Combined Impact of Skew and Jitter Constraints on the minimum clock period ( > 0) In D 1 R1 Q t 1 > 0 Combinational logic T T + R2 D Q t 2 6 12 -t jitter T t c-q + t plogic + t su - + 2t jitter t hold t cdlogic + t cdreg 2t jitter > 0 with jitter: Degrades performance, and makes t hold even harder to meet. (The acceptable skew is reduced by jitter.) Sp12 CMPEN 411 L17 S.23
Clock Distribution Networks Clock skew and jitter can ultimately limit the performance of a digital system, so designing a clock network that minimizes both is important In many high-speed processors, a majority of the dynamic power is dissipated in the clock network. To reduce dynamic power, the clock network must support clock gating (shutting down (disabling the clock) units) Clock distribution techniques Balanced paths (H-tree network, matched RC trees) - In the ideal case, can eliminate skew - Could take multiple cycles for the clock signal to propagate to the leaves of the tree Clock grids - Typically used in the final stage of the clock distribution network - Minimizes absolute delay (not relative delay) Sp12 CMPEN 411 L17 S.24
H-Tree Clock Network If the paths are perfectly balanced, clock skew is zero Clock Can insert clock gating at multiple levels in clock tree Can shut off entire subtree if all gating conditions are satisfied Idle condition Clock Gated clock Sp12 CMPEN 411 L17 S.25
Clock Grid Network Distributed buffering reduces absolute delay and makes clock gating easier, but is sensitive to variations in the buffer delay Clock main clock buffer local logic area secondary clock buffers The secondary buffers isolate the local clock nets from the upstream load and amplify the clock signals degraded by the RC network decreases absolute skew gives steeper clocks Only have to bound the skew within the local logic area Sp12 CMPEN 411 L17 S.26
DEC Alpha 21164 (EV5) Example 300 MHz clock (9.3 million transistors on a 16.5x18.1 mm die in 0.5 micron CMOS technology) single phase clock 3.75 nf total clock load Extensive use of dynamic logic 20 W (out of 50) in clock distribution network Two level clock distribution Single 6 inverter stage main clock buffer at the center of the chip Secondary clock buffers drive the left and right sides of the clock grid in m3 and m4 Total equivalent driver size of 58 cm!! Sp12 CMPEN 411 L17 S.27
Sp12 CMPEN 411 L17 S.28 Secondary Clock Buffers
Clock Skew in Alpha Processor Absolute skew smaller than 90 ps The critical instruction and execution units all see the clock within 65 ps Sp12 CMPEN 411 L17 S.29
ASIC example Sp12 CMPEN 411 L17 S.30
Microprocessor example Sp12 CMPEN 411 L17 S.31
Dealing with Clock Skew and Jitter To minimize skew, balance clock paths using H-tree or matched-tree clock distribution structures. If possible, route data and clock in opposite directions; eliminates races at the cost of performance. The use of gated clocks to help with dynamic power consumption make jitter worse. Shield clock wires (route power lines V DD or GND next to clock lines) to minimize/eliminate coupling with neighboring signal nets. Use dummy fills to reduce skew by reducing variations in interconnect capacitances due to interlayer dielectric thickness variations. Beware of temperature and supply rail variations and their effects on skew and jitter. Power supply noise fundamentally limits the performance of clock networks. Sp12 CMPEN 411 L17 S.32
Clock Skew Scheduling 16 12 Minimum clock period with zero skew 16 16 12 A C Sp12 CMPEN 411 L17 S.33
Clock Skew Scheduling i j k 16 12 1 T = 15 pulse at i,k tight pulse at j max 16 C 12 Sp12 CMPEN 411 L17 S.34
Clock Scaling Sp12 CMPEN 411 L17 S.35
Next Lecture and Reminders Next lecture Intro to datapath design - Reading assignment Rabaey, et al, 11.1-11.2 Adder design - Reading assignment Rabaey, et al, 11.3 Sp12 CMPEN 411 L17 S.36