ARITHMETIC COMBINATIONAL MODULES AND NETWORKS

ARITHMETIC COMBINATIONAL MODULES AND NETWORKS 1 SPECIFICATION OF ADDER MODULES FOR POSITIVE INTEGERS HALF-ADDER AND FULL-ADDER MODULES CARRY-RIPPLE AND CARRY-LOOKAHEAD ADDER MODULES NETWORKS OF ADDER MODULES REPRESENTATION OF SIGNED INTEGERS: 1. sign-and-magnitude 2. two s-complement 3. ones -complement ADDITION AND SUBTRACTION IN TWO S COMPLEMENT ARITHMETIC-LOGIC UNITS (ALU) COMPARATOR MODULES AND NETWORKS MULTIPLICATION OF POSITIVE INTEGERS

ADDITION OF POSITIVE INTEGERS 2 CONVENTIONAL RADIX-2 NUMBER SYSTEM: RANGE: 0 to 2 n 1 x = (x n 1,..., x 0 ) x, x = n 1 x i 2 i i=0 integer

ADDER MODULES FOR POSITIVE INTEGERS 3 x y n n c out ADDER c in n z Figure 10.1: ADDER MODULE. x + y + c in = 2 n c out + z

A HIGH-LEVEL SPECIFICATION OF ADDER MODULE 4 INPUTS: x = (x n 1,..., x 0 ), x j {0, 1} y = (y n 1,..., y 0 ), y j {0, 1} c in {0, 1} OUTPUTS: z = (z n 1,..., z 0 ), z j {0, 1} c out {0, 1} FUNCTIONS: z = (x + y + c in ) mod 2 n c out = 1 if (x + y + c in ) 2 n 0 otherwise

EXAMPLE for n=5 5 x y c in z c out 12 14 1 (12 + 14 + 1) mod 32 = 27 0 because (12 + 14 + 1) < 32 19 14 1 (19 + 14 + 1) mod 32 = 2 1 because (19 + 14 + 1) > 32

CARRY-RIPPLE ADDER IMPLEMENTATION 6 y n-1 x n-1 y i x i y 0 x 0 c out =c n c i+1 c i c 1 Full Adder Full Adder Full Adder = c in c 0 z n-1 z i z 0 Figure 10.2: CARRY-RIPPLE ADDER MODULE. DELAY OF CARRY-RIPPLE ADDER t p (net) = (n 1)t c + max(t z, t c ) t c = Delay(c i c i+1 ) t z = Delay(c i z i )

HIGH-LEVEL SPECIFICATION OF FULL-ADDER 7 x i + y i + c i = 2c i+1 + z i INPUTS: x i, y i, c i {0, 1} OUTPUTS: z i, c i+1 {0, 1} FUNCTION: z i = (x i + y i + c i ) mod 2 c i+1 = 1 if (x i + y i + c i ) 2 0 otherwise

FULL-ADDER IMPLEMENTATION 8 x i y i c i c i+1 z i 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 z i = x i y ic i x iy i c i x iy ic i x i y i c i c i+1 = x i y i x i c i y i c i

FULL ADDER TWO-LEVEL IMPLEMENTATION 9 x i y i x i y i x i x i y i c i y i x i y i c i c i z i x i y i x i c c i+1 i y i c i c i+1 x i y i c i (a) Figure 10.3: IMPLEMENTATIONS OF FULL-ADDER MODULE: a) TWO-LEVEL.

ALTERNATIVE IMPLEMENTATION 10 ADDITION mod 2 SUM IS 1 WHEN NUMBER OF 1 S IN INPUTS (including the carry-in) IS ODD: z i = x i y i c i CARRY-OUT IS 1 WHEN (x i + y i = 2) or (x i + y i = 1 and c i = 1): c i+1 = x i y i INTERMEDIATE VARIABLES PROPAGATE GENERATE (x i y i )c i p i = x i y i g i = x i y i HALF-ADDER x i y i g i p i 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0

IMPLEMENTATION WITH HALF-ADDERS 11 FA EXPRESSIONS IN TERMS OF p is, g is and c is z i = p i c i c i+1 = g i p i c i x i y i Half Adder (HA) p i HA z i g i c i c i+1 (b) x i y i p i g i z i c i c i+1 (c) Figure 10.3: IMPLEMENTATIONS OF FULL-ADDER MODULE: b) MULTILEVEL GATE NETWORK WITH XORs, ANDs and OR; c) WITH XORs and NANDs.

WORST-CASE DELAY 12 y n-1 x n-1 y i x i y 0 x 0 c out =c n c i+1 c i c 1 Full Adder Full Adder Full Adder = c in c 0 z n-1 z i z 0 Figure 10.2: CARRY-RIPPLE ADDER MODULE. WORST-CASE DELAY t p = t xor + 2(n 1)t nand + max(2t nand, t xor )

CHARACTERISTICS OF FULL-ADDER IN cmos FAMILY 13 Input [standard loads] c i 1.3 x i 1.1 y i 1.3 Size: 7 [equivalent gates] From To Propagation delays t plh t phl [ns] [ns] c i z i 0.43 + 0.03L 0.49 + 0.02L x i z i 0.68 + 0.04L 0.74 + 0.02L y i z i 0.68 + 0.04L 0.74 + 0.02L c i c i+1 0.36 + 0.04L 0.40 + 0.02L x i c i+1 0.73 + 0.04L 0.71 + 0.02L y i c i+1 0.37 + 0.04L 0.64 + 0.02L L: load on the gate output

CARRY-LOOKAHEAD ADDER IMPLEMENTATION 14 FASTER IMPLEMENTATION ADDITION AS A TWO-STEP PROCESS: 1. DETERMINE THE VALUES OF ALL THE CARRIES 2. SIMULTANEOUSLY COMPUTE ALL THE RESULT BITS

CARRY-LOOKAHEAD ADDER MODULE 15 x n y n c out = c c n 0 = c in Carry Generator c n-1 x y c 1 n n Sum Generator z n Figure 10.4: CARRY-LOOKAHEAD ADDER MODULE.

SWITCHING EXPRESSIONS 16 INTERMEDIATE CARRIES: c i+1 = g i p i c i BY SUBSTITUTION, c 1 = g 0 p 0 c 0 c 2 = g 1 p 1 c 1 = g 1 p 1 g 0 p 1 p 0 c 0 c 3 = g 2 p 2 c 2 = g 2 p 2 g 1 p 2 p 1 g 0 p 2 p 1 p 0 c 0 c 4 = g 3 p 3 g 2 p 3 p 2 g 1 p 3 p 2 p 1 g 0 p 3 p 2 p 1 p 0 c 0

17 g 3 g 2 CLG-4 p 3 p 2 g 1 p 1 g 0 p 0 c 0 G P p 3 p2 p 1 p 0 c 4 c 3 c 2 c 1 (a) Figure 10.5: CARRY-LOOKAHEAD ADDER: a) 4-BIT CARRY-LOOKAHEAD GENERATOR WITH P and G OUTPUTS (clg-4).

18 y 3 x 3 y 2 x 2 y 1 x 1 y 0 x 0 g p g p g p g p 3 3 2 2 1 1 0 0 c 4 G P CARRY LOOKAHEAD GENERATOR (CLG-4) c 0 c c c p 3 p 2 p 1 p 3 2 1 0 y i x i z 3 z 2 z 1 z 0 (b) Figure 10.5: CARRY-LOOKAHEAD ADDER: b) 4-BIT MODULE (cla-4); (clg-4). t p (x 0 c 4 ) = t pg + t CLG 4 t p (c 0 c 4 ) = t CLG 4 t p (x 0 P, G) = t pg + t CLG 4 t p (x 0 z 3 ) = t pg + t CLG 4 + t XOR

MODULE PROPAGATE AND GENERATE SIGNALS 19 P = 1: c in PROPAGATED BY THE MODULE G = 1: c out = 1 GENERATED BY THE MODULE, IRRESPECTIVE OF c in P = G = 1 if x + y = 2 4 1 0 otherwise 1 if x + y 2 4 0 otherwise c out = G P c in P = p 3 p 2 p 1 p 0 G = g 3 p 3 g 2 p 3 p 2 g 1 p 3 p 2 p 1 g 0

NETWORKS OF ADDER MODULES 20 ITERATIVE (CARRY-RIPPLE) ADDER NETWORK x = (x (3), x (2), x (1), x (0) ) x (3) = (x 15, x 14, x 13, x 12 ) x (2) = (x 11, x 10, x 9, x 8 ) x (1) = (x 7, x 6, x 5, x 4 ) x (0) = (x 3, x 2, x 1, x 0 ) where x = 2 12 x (3) + 2 8 x (2) + 2 4 x (1) + x (0)

16-BIT CARRY-RIPPLE ADDER 21 x (3) y (3) x (2) y (2) x (1) y (1) x (0) y (0) 4 4 4 4 4 4 4 4 c out= c16 4-bit adder c 12 4-bit adder c 8 4-bit adder c 4 4-bit adder c in = c 0 4 4 4 4 z (3) z (2) z (1) z (0) Figure 10.6: 16-BIT CARRY-RIPPLE ADDER NETWORK USING 4-BIT ADDER MODULES.

CARRY-LOOKAHEAD ADDER NETWORK 22 carries from CLG-4 modules c 28 c 24 c 20 c 16 c 12 c 8 c 4 x 7 4 y 7 4 x 6 4 y 6 4 x 5 4 y 5 4 x 4 4 y 4 4 x 3 4 y 3 4 x 2 4 y 2 4 x 1 4 y 1 4 x 0 4 y 0 4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 c 0 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 z 7 z 6 z 5 z 4 z 3 z 2 z 1 z 0 G 7 P 7 G 6 P 6 G 5 P 5 G 4 P 4 G 3 P 3 G 2 P 2 G 1 P 1 G 0 P 0 c 32 CLG-4 CLG-4 c 28 c 24 c 20 c 16 c 12 c 8 c 4 critical path carries to CLA-4 modules Figure 10.7: 32-BIT CARRY-LOOKAHEAD ADDER USING cla-4 AND clg-4 MODULES. PROPAGATION DELAY: t p (net) = t P G + 2t clg 4 + t add

CLA ADDER (cont.) 23 c 4 = G 0 P 0 c 0 c 8 = G 1 P 1 G 0 P 1 P 0 c 0 c 12 = G 2 P 2 G 1 P 2 P 1 G 0 P 2 P 1 P 0 c 0 c 16 = G 3 P 3 G 2 P 3 P 2 G 1 P 3 P 2 P 1 G 0 P 3 P 2 P 1 P 0 c 0 P 0 = p 3 p 2 p 1 p 0 G 0 = g 3 g 2 p 3 g 1 p 3 p 2 g 0 p 3 p 2 p 1

REPRESENTATION OF SIGNED INTEGERS AND BASIC OPERATIONS 24 TWO COMMON REPRESENTATIONS: - SIGN-AND-MAGNITUDE (SM) - TRUE-AND-COMPLEMENT (TC)

SIGN-AND-MAGNITUDE (SM) SYSTEM 25 x REPRESENTED BY PAIR (x s, x m ) sign: magnitude: x s = RANGE OF SIGNED INTEGERS 0 if x 0 1 if x 0 x m total number of bits: n sign: 1 magnitude: n 1 (2 n 1 1) x 2 n 1 1 TWO REPRESENTATIONS OF ZERO: x s = 0, x m = 0 (positive zero) x s = 1, x m = 0 (negative zero)

TWO S-COMPLEMENT SYSTEM 26 NO SEPARATION BETWEEN THE REPRESENTATION OF SIGN AND REPRESENTATION OF MAGNITUDE SIGNED INTEGER x REPRESENTED BY POSITIVE INTEGER x R MAP 2: BINARY REPRESENTATION OF x R x R = n 1 x i2 i, 0 x R 2 n 1 i=0 MAP 1: TWO S COMPLEMENT x R = x mod 2 n BY DEFINITION OF mod, FOR x < 2 n : equivalent to x R = x if x 0 2 n x if x < 0 FOR UNAMBIGUOUS SYMMETRICAL REPRESENTATION x max 2 n 1 1 x -4-3 -2-1 0 1 2 3 x R 4 5 6 7 0 1 2 3

27 Signed integer x Two s-complement system Map 1 Positive integer x R Conventional binary code Map 2 Bit-vector x Figure 10.8: SIGNED INTEGER REPRESENTED BY POSITIVE INTEGER.

28-1 x 0 +1-3 -2 13 14 15 0 x R 1 2 3 +2 +3-4 12 4 +4-5 -6 11 10 9 8 7 6 5 +6 +5-7 Complement forms -8 +7 True forms Figure 10.9: TWO S COMPLEMENT REPRESENTATION FOR n = 4.

MAPPING IN TWO S-COMPLEMENT SYSTEM 29 x x R x 0 0 00...000 1 1 00...001 2 2 00...010 - - - True forms - - - (positive) - - - x R = x 2 n 1 1 2 n 1 1 01...111 2 n 1 2 n 1 10...000 (2 n 1 1) 2 n 1 + 1 10...001 - - - - - - Complement forms - - - (negative) 2 2 n 2 11...110 x R = 2 n x 1 2 n 1 11...111

EXAMPLE 10.2: MAPPINGS FOR 4 x 3 30 x x R x 3 3 011 2 2 010 1 1 001 0 0 000-1 7 111-2 6 110-3 5 101-4 4 100

CONVERSE MAPPING 31 x = x R if x R 2 n 1 1 (x 0) x R 2 n if x R 2 n 1 (x < 0) IN TERMS OF BIT VECTOR (x n 1, x n 2,..., x 1, x 0 ) i) For x R < 2 n 1, bit x n 1 is 0 and x 0. x = x R = 0 2 n 1 + n 2 x i2 i i=0 ii) For x R 2 n 1 bit x n 1 is 1 and x < 0. x = x R 2 n = (1 2 n 1 + n 2 x i2 i ) 2 n = 1 2 n 1 + n 2 x i2 i i=0 i=0 COMBINING BOTH CASES x = x n 1 2 n 1 + n 2 x i2 i i=0

32 8-BIT EXAMPLES: x = x n 1 2 n 1 + n 2 x i2 i i=0 x x 01000101 0 + 69 = 69 11000101 128 + 69 = 58 SIGN DETECTION: x 0 if x n 1 = 0 x < 0 if x n 1 = 1

ONES -COMPLEMENT SYSTEM 33 x R = x mod C ONES -COMPLEMENT SYSTEM: C = 2 n 1 the ones -complement system symmetrical, with the range (2 n 1) x 2 n 1; two representations for zero, namely x R = 0 and x R = 2 n 1; the sign also detected by the most-significant bit x 0 if (x n 1 = 0) or (x R = 2 n 1)

MAPPING IN ONES -COMPLEMENT SYSTEM 34 x x R x 0 0 00...000 1 1 00...001 2 2 00...010 - - - True forms - - - (positive) - - - x R = x 2 n 1 1 2 n 1 1 01...111 (2 n 1 1) 2 n 1 10...000 - - - - - - Complement forms 2 2 n 3 11...101 (negative) 1 2 n 2 11...110 x R = 2 n 1 x 0 2 n 1 11...111

ADDITION IN TWO S COMPLEMENT SYSTEM 35 TO GET COMPUTE z = x + y z R = (x R + y R ) mod 2 n CORRECT IF 2 n 1 (x + y) 2 n 1 1 PROOF: CONSIDER (x R + y R ) mod 2 n AND SHOW THAT IT CORRESPONDS TO z R BY DEFINITION OF THE REPRESENTATION, THEREFORE, x R = x mod 2 n and y R = y mod 2 n (x R + y R ) mod 2 n = (x mod 2 n + y mod 2 n ) mod 2 n BY DEFINITION OF REPRESENTATION = (x + y) mod 2 n = z mod 2 n z mod 2 n = z R

2 s COMPLEMENT ADDITION: A SUMMARY 36 1. ADD x R AND y R (use adder for positive operands) 2. PERFORM THE mod OPERATION DOES NOT DEPEND ON THE RELATIVE MAGNITUDES OF THE OPERANDS AND ON THEIR SIGNS (simpler than in S+M) EXAMPLES OF ADDITION FOR C=64 and 32 x, y, z 31 Signed Representation Two s-complement Signed operands addition result x y x R y R (x R + y R ) mod 64 = z R z 13 9 13 9 22 mod 64 = 22 22 13-9 13 55 68 mod 64 = 4 4-13 9 51 9 60 mod 64 = 60-4 -13-9 51 55 106 mod 64 = 42-22

THE mod OPERATION 37 Let w R = x R + y R. Then z R = w R mod 2 n = x R, y R < 2 n w R < 2 2 n w R if w R < 2 n w R 2 n if 2 n w R < 2 2 n Since w R < 2 2 n w = (w n, w n 1,..., w 0 ) w R = < 2 n if w n = 0 2 n if w n = 1 Case 1. w R < 2 n. Then w R mod 2 n = w R (w n 1,..., w 0 ). Case 2. w R 2 n w R mod 2 n = w R 2 n (1, w n 1,..., w 0 ) (1, 0,..., 0) = (w n 1,..., w 0 ) CONCLUSION: w R mod 2 n = (w n 1,..., w 0 )

38 mod OPERATION PERFORMED BY DISCARDING MOST-SIGNIFICANT BIT OF w 2 S COMPLEMENT ADDITION: RESULT CORRESPONDS TO OUTPUT OF ADDER, DISCARDING THE CARRY-OUT z = ADD(x, y, 0) x y n n c out discard ADDER 0 n z Figure 10.10: TWO S-COMPLEMENT ADDER MODULE.

EXAMPLES OF 2 S COMPLEMENT ADDITION 39 Bit-level Positive Signed computation representation values n = 4 x = 1011 x R = 11 x = 5 y = 0101 y R = 5 y = 5 w = 10000 w R = 16 z = 0000 z R = 0 z = 0 n = 8 x = 11011010 x R = 218 x = 38 y = 11110001 y R = 241 y = 15 w = 111001011 w R = 459 z = 11001011 z R = 203 z = 53

CHANGE OF SIGN IN TWO S COMPLEMENT SYSTEM 40 z = x z R = (2 n x R ) mod 2 n x = 0: since z = x = 0 we have z R = x R = 0. Moreover, x > 0: since z = x is negative, Moreover, x is positive so that Substitute: z R = 2 n x R. x < 0: since z = x is positive, Moreover, x is negative so that Substitute: z R = 2 n x R. z R = (2 n 0) mod 2 n = 0 z R = 2 n z = 2 n x x R = x z R = z = x x R = 2 n x = 2 n + x

CHANGE OF SIGN (cont.) 41 DIRECT SUBTRACTION 2 n x R COMPLEX EXAMPLE: 2 8 100000000 x R 01011110 10100010 INSTEAD, USE 2 n = (2 n 1) + 1 z R = (2 n 1 x R ) + 1 THE COMPLEMENT WITH RESPECT TO 2 n 1: COMPLEMENT EACH BIT OF x x R = 17 010001 63 x R 111111 010001 101110

CHANGE-OF-SIGN OPERATION 42 TWO-STEP OPERATION: 1. COMPLEMENT EACH BIT OF x denoted x. 2. ADD 1 (set carry-in c 0 = 1) DESCRIPTION: EXAMPLE FOR n = 4, x = 3: z = ADD(x, 0, 1) x 1101 x = 3 x 0010 0 0000 c 0 1 z 0011 z = 3

SUBTRACTION IN TWO S COMPLEMENT SYSTEM 43 z = x y = x + ( y) z R = (x R + (2 n 1 y R ) + 1) mod 2 n THE CORRESPONDING DESCRIPTION z = ADD R (x, y, 1) EXAMPLE: x 01100000 y 00110001 y 11001110 1 z 00101111 SUMMARY OF 2 S COMPLEMENT OPERATIONS OPERATION 2 s COMPLEMENT SYSTEM z = x + y z = ADD(x, y, 0) z = x z = ADD(x, 0, 1) z = x y z = ADD(x, y, 1)

OVERFLOW DETECTION IN ADDITION 44 OVERFLOW result exceeds most positive or negative representable integer 2 n 1 z 2 n 1 1 - BOTH OPERANDS SAME SIGN, RESULT OPPOSITE SIGN v = x n 1y n 1z n 1 x n 1 y n 1 z n 1 x>0 y>0 z>0 x>0 y>0 z<0 Overflow x<0 y<0 z<0 x<0 y<0 z>0 Overflow 0 2 n 2 n-1 Figure 10.11: OVERFLOW IN TWO S-COMPLEMENT SYSTEM.

TWO S COMPLEMENT ARITHMETIC UNIT 45 INPUTS: x = (x n 1,..., x 0 ), x j {0, 1} y = (y n 1,..., y 0 ), y j {0, 1} c in {0, 1} F = (f 2, f 1, f 0 ) OUTPUTS: z = (z n 1,..., z 0 ), z j {0, 1} c out, sgn, zero, ovf {0, 1} FUNCTIONS: F Operation 001 add add z = x + y 011 sub subtract z = x y 101 addc add with carry z = x + y + c in 110 cs change sign z = x 010 inc increment z = x + 1 sgn = 1 zero = 1 ovf = 1 if z < 0, 0 otherwise (the sign) if z = 0, 0 otherwise if z overflows, 0 otherwise

46 x n-1 x 0 K x x y n n K x COMPL X K y COMPL Y f 2 f 1 f 0 n (0...0) n n Combinational network c in 0 1 MUX K MX n K x K y K MX c 0 c n ADDER c 0 c n-1 n n z n-1 n c out ovf zero sgn z Figure 10.12: IMPLEMENTATION OF TWO S-COMPLEMENT ARITHMETIC UNIT.

CONTROL OF TWO S-COMPLEMENT ARITHMETIC OPERATIONS 47 OPERATION IDENTIFIED BY BIT-VECTOR F = (f 2, f 1, f 0 ) COMPLEMENT OPERATION a = compl(b, K): CONTROL SIGNALS: a i = b i if K = 0 b i if K = 1 Operation Op-code Control Signals f 2 f 1 f 0 z K x K y K MX add 001 add(x, y, 0) 0 0 1 sub 011 add(x, y, 1) 0 1 1 addc 101 add(x, y, c in ) 0 0 1 cs 110 add(x, 0, 1) 1 d.c. 0 inc 010 add(x, 0, 1) 0 d.c. 0 K x = f 2 f 1 K y = f 1 K MX = f 0 c 0 = f 1 f 2 f 0 c in

ALU MODULES AND NETWORKS 48 ARITHMETIC-LOGIC UNIT module realizing set of arithmetic and logic functions Why build ALUs? 1. Use in many different applications 2. alu modules used in processors: function selected by control unit

TYPICAL EXAMPLE OF ALU 49 Control (S) Function zero z = 0 add z = (x + y + c in ) mod 16 sub z = (x + y + c in ) mod 16 exsub z = (x + y + c in ) mod 16 and z = x y or z = x y xor z = x y one z = 1111 a denotes the integer represented by vector a,, and are applied to the corresponding bits

4-bit ALU 50 x y 4 4 P 4 - BIT ALU 3 S G c in 4 z Figure 10.13: 4-bit ALU.

NETWORKS OF ALU MODULES 51 MODULE HAS NO CARRY-OUT SIGNAL cannot be used directly in an iterative (carry-ripple) network carry-out signal implemented as c out = G P c in carry-skip network

16-bit ALU 52 x 3 y 3 x 2 y 2 x 1 y 1 x 0 y 0 4 4 3 4 4 4 4 4 4 P 3 G 3 4 - BIT ALU P 2 G 2 4 - BIT ALU 3 P 1 G 1 4 - BIT ALU 3 P 0 G 0 4 - BIT ALU 3 S c 0 4 4 c 8 4 4 z 3 z 2 z 1 z 0 G 3 P 3 G 2 P 2 G 1 P 1 G 0 P 0 c 16 P G CLG-4 c 12 c 8 c 4 Figure 10.14: 16-bit alu.

COMPARATOR MODULES 53 HIGH-LEVEL DESCRIPTION OF AN n-bit COMPARATOR: INPUTS: x = (x n 1,..., x 0 ), x j {0, 1} y = (y n 1,..., y 0 ), y j {0, 1} c in {G,E,S} OUTPUT: z {G,E,S} FUNCTION: z = x and y the integers represented x and y G if (x > y) or (x = y and c in = G) E if (x = y) and (c in = E) S if (x < y) or (x = y and c in = S) IMPLEMENTATION OF 4-bit COMPARATOR MODULE c in = (c G in, c E in, c S in), c G in, c E in, c S in {0, 1} z = (z G, z E, z S ), z G, z E, z S {0, 1}

54 S 3 x 3 E 3 y 3 G 3 E 3 S 2 x y c G in c E in c S in 4 4 COMPARATOR MODULE zg ze zs x 2 y 2 x 1 y 1 E 2 E 1 E 3 G 2 E 3 E 2 S 1 E 3 E 2 G 1 zg ze (a) zs x 0 E 0 E 3 E 2 E 1 S 0 y 0 E 3 E 2 E 1 G 0 (b) c G in c E in c S in E 3 E 2 E 1 E 0 cg in E 3 E 2 E 1 E 0 c E in E 3 E 2 E 1 E 0 c S in Figure 10.15: 4-BIT COMPARATOR MODULE: a) block diagram; b) gate-network implementation.

BINARY-LEVEL DESCRIPTION 55 S i = x iy i E i = (x i y i ), i = 0,..., 3 G i = x i y i z G = G 3 + E 3 G 2 + E 3 E 2 G 1 + E 3 E 2 E 1 G 0 + E 3 E 2 E 1 E 0 c G in z E = E 3 E 2 E 1 E 0 c E in z S = S 3 + E 3 S 2 + E 3 E 2 S 1 + E 3 E 2 E 1 S 0 + E 3 E 2 E 1 E 0 c S in

ITERATIVE COMPARATOR NETWORK 56 x 3 y 3 x 2 y 2 x 1 y 1 x 0 y 0 z G z E z S COMPARATOR MODULE COMPARATOR MODULE COMPARATOR MODULE 4 4 COMPARATOR MODULE G c in = 0 E c in = 1 S c = 0 in Figure 10.16: 16-BIT ITERATIVE COMPARATOR NETWORK.

TREE COMPARATOR NETWORK 57 x 3 y 3 x 2 y 2 x 1 y 1 x 0 y0 4 4 COMPARATOR MODULE 0 1 0 COMPARATOR MODULE 0 1 0 COMPARATOR MODULE 0 1 0 COMPARATOR MODULE 0 1 0 z G z E z S z G z E z S z G z E z S z G z E z S g 3 s 3 g 2 s 2 g 1 s 1 g 0 s 0 4 4 COMPARATOR MODULE 0 1 0 z G z E z S Figure 10.17: 16-BIT TREE COMPARATOR NETWORK.

TREE COMPARATOR (cont.) 58 z G = z E = z S = 1 if g > s 0 otherwise 1 if g = s 0 otherwise 1 if g < s 0 otherwise g and s are the integers represented by the vectors g and s, respectively.

MULTIPLIERS 59 n m bits multiplier: 0 x 2 n 1 (the multiplicand) 0 y 2 m 1 (the multiplier), 0 z (2 n 1)(2 m 1) (the product). The high-level function: Since y i is either 0 or 1, we get z = x y z = x( m 1 y i2 i ) = m 1 xy i2 i i=0 i=0 xy i = 0 if y i = 0 x if y i = 1

MULTIPLICATION BIT MATRIX 60 x 7 y 0 x 6 y 0 x 5 y 0 x 4 y 0 x 3 y 0 x 2 y 0 x 1 y 0 x 0 y 0 x 7 y 1 x 6 y 1 x 5 y 1 x 4 y 1 x 3 y 1 x 2 y 1 x 1 y 1 x 0 y 1 x 7 y 2 x 6 y 2 x 5 y 2 x 4 y 2 x 3 y 2 x 2 y 2 x 1 y 2 x 0 y 2 x 7 y 3 x 6 y 3 x 5 y 3 x 4 y 3 x 3 y 3 x 2 y 3 x 1 y 3 x 0 y 3 x 7 y 4 x 6 y 4 x 5 y 4 x 4 y 4 x 3 y 4 x 2 y 4 x 1 y 4 x 0 y 4 x 7 y 5 x 6 y 5 x 5 y 5 x 4 y 5 x 3 y 5 x 2 y 5 x 1 y 5 x 0 y 5 Multiplier implementation: m arrays of n and gates m 1 n-bit adders

61 sum_in x_bit y_bit x_bit y_bit x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 y0 c_out sum_in Half Adder sum_out x_bit y_bit c_out OR Module MH Half Adder sum_out c_in MH MF MF MF MF MF MF MH y 2 y 1 MF MF MF MF MF MF MF MH c_out Full Adder c_in MF MF MF MF MF MF MF MH y 3 sum_out Module MF y 4 (a) MF MF MF MF MF MF MF MH y 5 MF MF MF MF MF MF MF MH p 13 p 12 p 11 p 10 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 (b) Figure 10.18: IMPLEMENTATION OF AN 8 6 MULTIPLIER: a) PRIMITIVE MODULES; b) NETWORK.

MULTIPLIER DELAY 62 delay of the buffer which connects signal y 0 to the n and gates delay of the and gate delay of the adders t adders = t c (n 1) + t s + (t c + t s )(m 2) If t s = t c, we get t adders = (n + 2(m 2))t s = (n + 2m 4)t s FOR THE 8 6 CASE: t adders = (8 + 12 4)t s = 16t s

EXAMPLE OF NETWORKS WITH STANDARD ARITHMETIC MODULES 63 Inputs: a[3], a[2], a[1], a[0], b[3], b[2], b[1], b[0] {0,..., 2 16 1} e = (e 3, e 2, e 1, e 0 ), e i {0, 1} Outputs: c[3], c[2], c[1], c[0] {0,..., 2 17 1} d {0, 1, 2, 3} f {0, 1} Function: f = d = c[i] = 1 if at least one e j = 1 0 otherwise, j = 0, 1, 2, 3 i if e i is the highest priority event 0 if no event occurred a[i] + b[i] if e i is the highest priority event 0 otherwise

MODULAR IMPLEMENTATION 64 CONSISTS OF a priority encoder to determine the highest-priority event; an adder; two selectors (multiplexers) to select the corresponding inputs to the adder; a distributor (demultiplexer) to send the output of the adder to the corresponding system output; and an or gate to determine whether at least one event has occurred.

65 e 3 e 2 e 1 e 0 a[3] a[2] a[1] a[0] b[3] b[2] b[1] b[0] PRIORITY ENCODER 2 SELECTOR SELECTOR ADDER DISTRIBUTOR 2 f d c[3] c[2] c[1] c[0] Figure 10.19: NETWORK IN EXAMPLE 10.5