Introduction to Digital Logic Missouri S&T University CPE 2210 Subtractors

Introduction to Digital Logic Missouri S&T University CPE 2210 Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and Technology cetinkayae@mst.edu http://web.mst.edu/~cetinkayae/teaching/cpe2210fall2016 9 November 2016 rev. 16.0 2014 2016 Egemen K. Çetinkaya

Introduction Half-subtractor Full-subtractor Outline 1 s complement representation 2 s complement representation Overflow Summary 2

Digital Logic Systems Overview Combinatorial logic circuits for no memory systems Boolean algebra to mathematically design/analyze logic gates are building blocks Sequential logic circuits for memory systems Finite State Machines to mathematically design/analyze flip-flops and latches store memory flip-flops and latches are building blocks of sequential logic Sequential logic circuits (aka controllers) combine combinatorial circuits storage elements (e.g. registers) 3

Digital Systems Components analog phenomena electric signal A2D digital data digital data sensors and other inputs Digital System D2A electric signal actuators and other outputs digital data digital data Transducer: sensor + actuator Not all sensors/actuators require A2D/D2A conversion Digital system can be implemented: microprocessor readily available, cheap, easy to program, easy to reprogram custom circuit smaller, faster, consume less power 4

Digital Systems Paths Digital systems have two paths: datapath circuit control circuit Datapath circuit store data manipulate data transfer data from one part to another Control circuit controls the operation of datapath circuit 5

Registers Shifters Adders Comparators Counters/timers Datapath Components Building Block examples Multiplexer/demultiplexers Decoders/encoders ALUs: Arithmetic Logic Units 6

Overview subtract two N-bit numbers E.g.: 2-bit subtractor subtracts two 2-bit numbers 4-bit subtractor subtracts two 4-bit numbers Block diagram: 4-bit subtractor a3 b3 a2 b2 a1 b1 a0 b0 wi a b wi a b wi a b wi a b wi a3 a2 a1 a0 b3 b2 b1 b0 FS FS FS FS 4-bit subtractor wi w o s w o s w o s w o s w o s3 s2 s1 s0 w o s3 s2 s1 s0 7

Subtract Operation Compute sum, add carry to next column Lets add A=1010 and B=0111-1st column 0 1 0 1 10 0 1 1 1-2nd c olumn 0 1 10 1 0 1 0 0 1 1 1-3 r d c olumn 0 1 1 0 1 0 0 1 1 1-4th c olumn 0 1 0 1 0 1 1 minuend 0 1 1 1 subtrahend 1 1 1 0 1 1 0 0 1 1 difference 8

Half-Subtractor Subtracts two bits, generates two output bits Inputs: minuend and subtrahend Outputs: difference and borrow Lets try to design the circuit: 9

Half-Subtractor Subtracts two bits, generates two output bits Inputs: minuend and subtrahend Outputs: difference and borrow Lets try to design the circuit: Next steps? 10

Half-Subtractor Subtracts two bits, generates two output bits Inputs: minuend and subtrahend Outputs: difference and borrow Lets try to design the circuit: Next steps? Capture the function Create equations Implement as a circuit 11

Half-Subtractor Subtracts two bits, generates two output bits Inputs: minuend and subtrahend Outputs: difference and borrow Lets try to design the circuit: Next steps? Create equations D = b a + ba = b a b a D B 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 13

Half-Subtractor Subtracts two bits, generates two output bits Inputs: minuend and subtrahend Outputs: difference and borrow Lets try to design the circuit: Next steps? Implement as a circuit D = b a + ba = b a B = b a a b a b Halfsubtractor B D B D 15

Comparison Half-Adder vs. Half-Subtractor HA operation: a+b s = a b co = ab HS operation: b a D = a b B = b a a b a b a b a b Half-adder (HA) co s Halfsubtractor B D co s B D 16

Full-Subtractor Subtracts three bits, generates two output bits Inputs: minuend, subtrahend, and borrow in Outputs: difference and borrow out Lets try to design the circuit: 17

Full-Subtractor Subtracts three bits, generates two output bits Inputs: minuend, subtrahend, and borrow in Outputs: difference and borrow out Lets try to design the circuit: Next steps? 18

Full-Subtractor Subtracts three bits, generates two output bits Inputs: minuend, subtrahend, and borrow in Outputs: difference and borrow out Lets try to design the circuit: Next steps? Capture the function Pay attention: we are doing b a Bi that is the difference (D) Bo=1 if b<(a+bi) b a Bi D Bo 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 20

Full-Subtractor Subtracts three bits, generates two output bits Inputs: minuend, subtrahend, and borrow in Outputs: difference and borrow out Lets try to design the circuit: Next steps? Create equations D=b a Bi+b abi +ba Bi +babi D=b (a Bi+aBi )+b(a Bi +abi) D=b (a Bi)+b(a Bi) D=b a Bi b a Bi D Bo 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 21

Full-Subtractor Subtracts three bits, generates two output bits Inputs: minuend, subtrahend, and borrow in Outputs: difference and borrow out Lets try to design the circuit: Next steps? b a Bi D Bo 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 Create equations D=b a Bi Bo=b a Bi+b abi +b abi+babi Bo=b (a Bi+aBi )+abi(b +b) Bo=b (a Bi)+aBi 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 0 0 0 1 22

Full-Subtractor Subtracts three bits, generates two output bits Inputs: minuend, subtrahend, and borrow in Outputs: difference and borrow out Lets try to design the circuit: Next steps? Create equations D=b a Bi Bo=b (a Bi)+aBi b a Bi D Bo 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 23

Comparison Full-Adder vs. Full-Subtractor FA operation: a+b+c s = a b c co = ab + ac + bc FS operation: b a Bi D = b a Bi Bo = b (a Bi) + abi a b ci a b Bi Full adder (FA) (FS) c o s B o D 25

Negative Number Representation So far we dealt with positive numbers How do we go on representing negative numbers? 26

Number Systems Representation Type Explanation positive x > 0 negative x < 0 non-negative x 0 non-positive x 0 signed (in computing) represents both negative and positive numbers unsigned (in computing) represents only non-negative numbers 27

LSB: Least Significant Bit right-most bit MSB: Most Significant Bit higher-order bit left-most bit Example: LSB MSB Number Systems Representations 1 0 1 0 1 1 0 1 28

Unsigned numbers: Number Systems Unsigned Numbers all bits represent the magnitude of a number Example: LSB MSB 1 0 1 0 1 1 0 1 magnitude 29

Signed numbers: Number Systems Signed Numbers left most bit represents the sign MSB is shifted one bit to right Example: what is the value? sign bit: 0 for positive numbers, 1 for negative numbers LSB MSB 1 0 1 0 1 1 0 1 sign magnitude 30

Signed numbers: Number Systems Signed Numbers left most bit represents the sign MSB is shifted one bit to right Example: what is the value? 45 sign bit: 0 for positive numbers, 1 for negative numbers LSB MSB 1 0 1 0 1 1 0 1 sign magnitude 31

Number Systems Signed and Magnitude Examples Egemen K. Çetinkaya 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 32

Number Systems Signed and Magnitude Examples Egemen K. Çetinkaya +2 2 +0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 33

Number Representation Range representing signed vs. unsigned numbers? E.g. 4-bit signed-magnitude example? 1 1 1 1 0 1 1 1 E.g. 4-bit unsigned-magnitude example? 0 0 0 0 1 1 1 1 34

Number Representation Range representing signed vs. unsigned numbers? E.g. 4-bit signed-magnitude example? 1 1 1 1 0 1 1 1 Range from (2 n 1 1) to +(2 n 1 1), 7 to +7 E.g. 4-bit unsigned-magnitude example? 0 0 0 0 1 1 1 1 Range from 0 to +(2 n 1) 0 to 15 35

Signed Numbers and Complements There are two types of complements r s complement of N = r n N radix complement or true complement N is the number, r is the base, n is the digits (r 1) s complement of N = r n r m N diminished-radix or radix-minus-one complement N is the number, r is the base, n is the integer digits, m is the fraction digits E.g. for number 22.1 in base 10 10s complement: 10 2 22.1 = 100 22.1 = 77.9 9s complement: 10 2 10 1 22.1 = 100 0.1 22.1 = 77.8 36

Binary Complements Two s complement (2 s complement) r s complement of N = r n N One s complement (1 s complement) (r 1) s complement of N = r n r m N E.g. for number unsigned 101 in base 2 1 s complement: 2 3 2 0 101 = 1000 1 101 = 010 2 s complement: 2 3 101 = 1000 101 = 011 1 s complement is bits flipped of original number 2 s complement is 1 s complement + 1 37

3-bit True and Complement Forms Example Complement representation are for negative numbers Number 011 010 001 000 100 101 110 111 38

3-bit True and Complement Forms Example Complement representation are for negative numbers Number 011 010 001 000 100 101 110 111 Unsigned 39

3-bit True and Complement Forms Example Complement representation are for negative numbers Number 011 3 010 2 001 1 000 0 100 4 101 5 110 6 111 7 Unsigned 40

3-bit True and Complement Forms Example Complement representation are for negative numbers Number Unsigned Signed and magnitude 011 3 010 2 001 1 000 0 100 4 101 5 110 6 111 7 41

3-bit True and Complement Forms Example Complement representation are for negative numbers Number Unsigned Signed and magnitude 011 3 +3 010 2 +2 001 1 +1 000 0 +0 100 4 0 101 5 1 110 6 2 111 7 3 42

3-bit True and Complement Forms Example Complement representation are for negative numbers Number Unsigned Signed and magnitude 011 3 +3 010 2 +2 001 1 +1 000 0 +0 100 4 0 101 5 1 110 6 2 111 7 3 1 s complement (of signed value) 43

3-bit True and Complement Forms Example Complement representation are for negative numbers Number Unsigned Signed and magnitude 1 s complement (of signed value) 011 3 +3 +3 (no change) 010 2 +2 +2 (no change) 001 1 +1 +1 (no change) 000 0 +0 +0 (no change) 100 4 0 0 (111) 101 5 1 1 (110) 110 6 2 2 (101) 111 7 3 3 (100) 44

3-bit True and Complement Forms Example Complement representation are for negative numbers Number Unsigned Signed and magnitude 1 s complement (of signed value) 2 s complement (of signed value) 011 3 +3 +3 (no change) +3 (no change) 010 2 +2 +2 (no change) +2 (no change) 001 1 +1 +1 (no change) +1 (no change) 000 0 +0 +0 (no change) +0 (no change) 100 4 0 0 (111) 4 (100) 101 5 1 1 (110) 1 (111) 110 6 2 2 (101) 2 (110) 111 7 3 3 (100) 3 (101) 46

Negating Numbers Using Complements To represent negative value of a positive number 1- you can represent using 1 s complement take the positive value, including the sign bit (which is 0) flip all bits to obtain 1 s complement representation E.g.: represent 6 in 1 s complement using 4-bit 6 is 0110 using 4-bits, 6 is 1001 in 1 s complement form 2- you can represent using 2 s complement once 1s complement is calculated, add 1 to the result E.g.: represent 6 in 2 s complement using 4-bit 6 is 0110 using 4-bits, 6 is 1001 in 1 s complement form 1010 is 2s complement of 6 (added 1 to 1 s complement) 47

Notes About Complements Complement of a complement is original value E.g.: 2 s complement of 101 is 111 E.g.: 2 s complement of 111 is 101 2 s complement of 1000000 0 in decimal will be the number itself: 1000000 0 2 s complement of 0000000 0 in decimal will be the number itself: 0000000 0 2 s complement of 1111111 1 in decimal will be: 1 1 s complement have 2 zero values hard to design a zero-detector using 1 s complement 48

Number Representation Range representing signed vs. unsigned numbers? E.g. 3-bit unsigned-magnitude example? Range: from 0 to +(2 n 1), 0 to 7 E.g. 3-bit signed-magnitude example? 1 s complement range: from (2 n 1 1) to +(2 n 1 1), 3 to +3 0 appears twice 2 s complement range: from (2 n 1 ) to +(2 n 1 1), 4 to +3 0 appears only once 49

Subtraction via 2 s Complements Consider two numbers: N1=11011 and N2=10110 N1: 011011 (27) N2: 110110 (22) D: 101 (5) Values in red representing the sign Instead find 2 s complement of N2=? 50

Subtraction via 2 s Complements Consider two numbers: N1=11011 and N2=10110 N1: 011011 (27) N2: 110110 (22) D: 00101 (5) Instead find 2 s complement of N2=? 1 s complement of N2 is: 110110 101001 2 s complement of N2 is: 101001 + 1 = 101010 51

Subtraction via 2 s Complements N1: 11011 (27) N2: 10110 (22) D: 00101 (5) Instead find 2 s complement of N2 = 01010 Instead of subtracting, add N1 and N2 s complement N1: 11011 (27) N2: 01010 (10) S: 100101 (37 32) Ignoring the end carry, are the results same: D vs S? 52

1 s Complement Addition Example Egemen K. Çetinkaya ( + 5 ) + ( + 2 ) ( + 7 ) 0 1 0 1 + 0 0 1 0 0 1 1 1 ( 5 ) + ( + 2 ) (- 3 ) 1 0 1 0 + 0 0 1 0 1 1 0 0 ( + 5 ) + ( 2 ) ( + 3 ) 0 1 0 1 + 1 1 0 1 10 0 1 0 1 0 0 1 1 ( 5 ) + ( 2 ) ( 7 ) 1 0 1 0 + 1 1 0 1 1 0 1 1 1 1 1 0 0 0 53

2 s Complement Addition Example Egemen K. Çetinkaya + ( + 5 ) ( + 2 ) + 0 1 0 1 0 0 1 0 + ( 5 ) ( + 2 ) + 1 0 1 1 0 0 1 0 ( + 7 ) 0 1 1 1 ( 3 ) 1 1 0 1 ( + 5 ) + ( 2 ) + 0 1 0 1 1 1 1 0 ( 5 ) + ( 2 ) + 1 0 1 1 1 1 1 0 ( + 3 ) 1 0 0 1 1 ( 7 ) 11 0 0 1 ignore ignore 54

Subtraction via 2 s Complements Subtraction via adding 2 s complement A B = A + ( B) A B = A + (2 s complement of B) A B = A + (inverted B + 1) A B N-bit A Adder B cin 1 S 55

Adder/Subtractor Combined Egemen K. Çetinkaya Performs X+Y or X Y depending on value of Add/Sub 56

Logic Gates XOR Gate Output is 1 when both input 1s are odd numbered Symbol: XOR Truth table: x y F 0 0 0 0 1 1 1 0 1 1 1 0 57

Overflow The result of addition or subtraction must fit into: number of allocated bits to represent the resulting number If the result does not fit, then overflow occurs Signed numbers range from (2 n 1 1) to +(2 n 1 1) Unsigned numbers range from 0 to +(2 n 1) Overflow can be determined by: if the sign bits are same but switched in the result if the sign bits are different, there cannot be overflow overflow = c n 1 c n 58

Overflow Examples + ( + 7 ) ( + 2 ) + 0 1 1 1 0 0 1 0 + ( 7 ) ( + 2 ) + 1 0 0 1 0 0 1 0 ( + 9 ) 1 0 0 1 c 4 = 0 c 3 = 1 ( 5 ) 1 0 1 1 c 4 = 0 c 3 = 0 ( + 7 ) + ( 2 ) + 0 1 1 1 1 1 1 0 ( 7 ) + ( 2 ) + 1 0 0 1 1 1 1 0 ( + 5 ) 1 0 1 0 1 c 4 = 1 c 3 = 1 ( 9 ) 10 1 1 1 c 4 = 1 c 3 = 0 59

Half-subtractor: Summary subtracts two bits: minuend and subtrahend generates two output bits: difference and borrow Full-subtractor: subtracts three bits: minuend, subtrahend, and borrow in generates two output bits: difference and borrow out Negative binary numbers can be represented via: 1 s complements: flip all bits including the sign bit 2 s complements: 1s complement + 1 Overflow can be determined by: c n 1 c n 60

References and Further Reading [V2011] Frank Vahid, Digital Design with RTL Design, VHDL, and Verilog, 2nd edition, Wiley, 2011. [BV2009] Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd edition, McGraw-Hill, 2009. [G2003] Donald D. Givone, Digital Principles and Design, McGraw-Hill, 2003. 61

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