igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning i Sequential Logic Circuits November 2002
Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state 2 storage mechanisms positive feedback charge-based
Naming Conventions In our text: alatchislevel level sensitive a register is edge-triggered There are many different naming conventions For instance, many books call edgetriggered elements flip-flops This leads to confusion however
Latch versus Register Latch stores data when clock is low Register stores data when clock rises Clk Clk Clk Clk
Latches Positive Latch Negative Latch In G Out In Out G clk In Out clk In Out Out stable Out follows In Out stable Out follows In
Latch-Based esign N latch is transparent when φ = 0 φ P latch is transparent when φ = 1 N Latch Logic P Latch Logic
Timing efinitions t su t hold t Register ATA STABLE t t c 2 q ATA STABLE t
Characterizing Timing t 2 Clk Clk t C 2 Register t C 2 Latch
Maximum Clock Frequency φ FF s LOGIC t p,comb t clk- + t p,comb + t setup = T Also: t cdreg + t cdlogic > t hold t cd : contamination delay = minimum delay
Positive Feedback: Bi-Stability V i1 V o1 =V i2 V o2 V o1 V i2 V o2 =V i 1 V o1 V 5Vo o1 V i 2 V i1 V o2 V i2 =V o1 A V i25 o1 V 2 C B V i1 = V o2
Meta-Stability i2 5V o1 A i2 5V o1 A V i V i C C d B B V i1 5V o2 d Gain should be larger than 1 in the transition region d V i1 5V o2
Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states Converting into a MUX Forcing the state (can implement as NMOS-only)
Mux-Based Latches Negative latch (transparent when = 0) Positive latch (transparent when = 1) 1 0 0 1 = Clk + Clk In = Clk + Clk In
Mux-Based Latch
Mux-Based Latch M M NMOS only Non-overlapping overlapping clocks
Master-Slave (Edge-Triggered) Register Master Slave 1 0 M 0 1 M Two opposite latches trigger on edge Also called master-slave latch pair
Master-Slave Register Multiplexer-based latch pair I 2 T 2 I 3 I 5 T 4 I 6 M I 1 T 1 I 4 T 3
Clk- elay 2.5 Volt ts 1.5 05 0.5 t c 2 q(lh) t c 2 q(hl) 2 05 0.5 0 0.5 1 1.5 2 2.5 time, nsec
Setup Time 3.0 2.5 3.0 2.5 2.0 M 2.0 I 2 2 T 2 lts Vo 1.5 1.0 lts Vo 1.5 1.0 0.5 I 2 2 T 2 0.5 M 0.0 0.0 2 0.5 0 02 0.2 04 0.4 06 0.6 08 0.8 1 2 0.5 0 02 0.2 04 0.4 06 0.6 08 0.8 1 time (nsec) time (nsec) (a) T setup 5 0.21 nsec (b) T setup 5 0.20 nsec
Reduced Clock Load Master-Slave Register T 1 I 1 T 2 I 3 I 2 I 4
Avoiding Clock Overlap X A B (a) Schematic diagram (b) Overlapping clock pairs
Overpowering the Feedback Loop Cross-Coupled Coupled Pairs NOR-based set-reset S S S R 0 0 R R 1 0 1 0 0 1 0 1 1 1 0 0 Forbidden State
Cross-Coupled Coupled NAN Cross-coupled NANs Added clock V S M 2 M 4 M R 8 M 1 M 3 M 6 S M 5 M 7 R This is not used in datapaths any more, but is a basic building memory cell
Sizing Issues 2.0 3 S 1.5 2 W = 0.5 μm (Volts s) 1.0 0.5 00 0.0 2.0 2.5 3.0 W/L 5 and 6 3.5 4.0 Volts 1 W = 0.6 μm W = 0.7 μm W = 0.8 μm W = 0.9 μm W = 1 μm 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 time (ns) (a) (b) Output voltage dependence on transistor width Transient response
Storage Mechanisms Static ynamic (charge-based)
Making a ynamic Latch Pseudo-Static ti
More Precise Setup Time Clk t t (a) t 1.05t C 2 t C 2 t Su t 2 C t H (b)
Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- ata T Setup-1 Clock T Setup-1 Time t=0 Time
Setup/Hold Time Illustrations Circuit it before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- ata T Setup-1 Clock T Setup-1 Time t=0 Time
Setup/Hold Time Illustrations Circuit it before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- ata T Setup-1 Clock T Setup-1 Time t=0 Time
Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 T Clk- CP ata Clock T Setup-1 Time T Setup-1 t=0 Time
Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay T Clk- Inv1 CP ata Clock T Setup-1 Time T Setup-1 t=0 Time
Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 CP 0 T Clk- Clock ata T Hold-1 Time T Hold-1 t=0 Time
Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 CP 0 T Clk- Clock ata T Hold-1 Time T Hold-1 t=0 Time
Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 CP 0 T Clk- T Hold-1 Time Clock ata T Hold-1 t=0 Time
Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 T Clk- CP 0 Clock ata T Hold-1 Time T Hold-1 t=0 Time
Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M T Clk- Clk- elay Inv1 CP 0 Clock T Hold-1 ata T Hold-1 Time t=0 Time
Other Latches/Registers: C 2 MOS V V M 2 M 6 M 4 X M 8 M 3 C L1 M 7 C L2 M 1 M 5 Master Stage Slave Stage Keepers can be added to make circuit pseudo-staticstatic
Insensitive to Clock-Overlap V V V V M 2 M 6 M 2 M 6 M 4 0 0 X M 8 X 1 M 3 1 M 7 M 1 M 5 M 1 M 5 (a) (0-0) overlap (b) (1-1) overlap
Pipelining a REG a REG log REG Out REG REG log REG Out b REG b REG Reference Pipelined
Other Latches/Registers: t TSPC V V V V Out In In Out Positive latch (transparent when = 1) Negative latch (transparent when = 0)
Including Logic in TSPC V V V V PUN In 1 In 2 In PN In 1 In 2 Example: logic inside the latch AN latch
TSPC Register V V V M 3 M 6 M 9 Y M 2 X M 5 M 8 M 1 M 4 M 7
Pulse-Triggered Latches An Alternative ti Approach Ways to design an edge-triggered sequential cell: Master-Slave Pulse-Triggered Latches Latch ata L1 L2 L ata Clk Clk Clk Clk Clk
Pulsed Latches V V M 3 M 6 V G M 2 G M 5 M P X G M 1 M 4 M N (a) register (b) glitch generation G (c) glitch clock
Pulsed Latches Hybrid Latch Flip-flop (HLFF), AM K-6 and K-7 : P 3 x P 1 M 3 M 6 P M M 2 5 2 M 1 M 4
Hybrid Latch-FF Timing 3.0 2.5 2.0 Volts 1.5 1.0 0.5 0.0 20.5 00 0.0 02 0.2 04 0.4 06 0.6 08 0.8 10 1.0 time (ns)
Latch-Based Pipeline In F C 1 C 2 C 3 G Out Compute F compute G
Non-Bistable Sequential Circuits Schmitt Trigger In Out V ou t V OH VTC with hysteresis V OL Restores signal slopes V M V M+ V in
Noise Suppression using Schmitt Trigger V in V out V M+ V M t 0 t t 0 +t p t
CMOS Schmitt Trigger V M 2 M 4 V in X V out M 1 M 3 Moves switching threshold of the first inverter
Schmitt Trigger Simulated VTC 2.5 2.5 2.0 2.0 1.5 V M1 1.5 X(V) 1.0 V 0.5 V M2 1.0 x (V) k= 1 V k= 2 0.5 k= 3 k= 4 0.0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 V in (V) V in (V) Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of the PMOS device M 4. The width is k* 0.5 m m.
CMOS Schmitt Trigger (2) V M 4 M 3 M 6 In Out M 2 X M 5 V M 1
Multivibrator Circuits R S Bistable Multivibrator flip-flop, Schmitt Trigger T Monostable Multivibrator one-shot Astable Multivibrator oscillator
Transition-Triggered Triggered Monostable In ELAY t d Out t d
Monostable Trigger (RC-based) V In A R B Out C (a) Trigger circuit. In B V M (b) Waveforms. Out t t 1 t 2
Astable Multivibrators (Oscillators) 0 1 2 N-1 3.0 2.5 V 1 V 3 V 5 Ring Oscillator 2.0 Volts 1.5 1.0 0.5 0.0 20.5 0.0 0.5 1.0 1.5 time (ns) simulated response of 5-stage oscillator
Relaxation Oscillator I1 Out 1 I2 Out 2 R C Int T = 2 (log3) RC
Voltage Controller Oscillator (VCO) V M6 V M4 Schmitt Trigger restores signal slopes In M2 I ref M1 I ref V contr M5 M3 Current starved inverter 6 t ph L (n nsec) 4 2 0.0 0.5 1.5 2.5 V contr (V) propagation delay as a function of control voltage
ifferential elay Element and VCO V o 2 V o 1 v 3 in1 in2 v 1 v 2 v 4 V ctrl delay cell 3.0 two stage VCO 2.5 V 1 V 2 V 3 V 4 2.0 15 1.5 1.0 0.5 0.0 2 0.5 0.5 1.5 time (ns) 2.5 3.5 simulated waveforms of 2-stage VCO