Combinational Logic Contents: Combinational and Sequential digital circuits. Design Procedure of combinational circuit. Adders: Half adder and Full adder. Subtractors: Half Subtractor and Full Subtractor. Code converter: BCD to excess-3. 101010101010101010101010101010101010101010101010101010101010101001010101010101010 BCD to 7-segment decoder. Multilevel NAND and NOR circuits. Course Instructor Mohammed Abdul kader Assistant Professor, EEE, IIUC
Combinational and Sequential Logic circuits 110101 101010 Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of logic gates whose outputs at any time are determined directly from the present combination of inputs without regard to previous inputs i.e. it has no memory element to hold the previous inputs/outputs. The outputs of a sequential circuit depend not only on present inputs, but also on past inputs, and the circuit behavior must be specified by a time sequence of inputs and internal states. Sequential circuits employ memory elements in addition to logic gates. 2
Steps in design Procedure 3 The procedure involves following steps: The problem is stated. The number of available input variables and required output variables is determined. The input and output variables are assigned letter symbols. The truth table that defines the required relationships between inputs and outputs is derived. Design Procedure of combinational circuit 110101 101010 The simplified Boolean function for each output is obtained. The logic diagram is drawn. Constraints in practical design method (1) minimum number of gates, (2) minimum number of inputs to a gate, (3) minimum propagation time of the signal through the circuit, (4) minimum number of interconnections and (5) limitations of the driving capabilities of each gate.
Adders Digital computer perform a variety of information-processing tasks. Among the basic functions encountered are the various arithmetic operations. The most basic arithmetic operation is the addition of two binary digits. Half adder: A combinational circuit that performs the addition of two bits is called a half-adder. Adders 110101 101010 Full adder: Combinational circuit that performs the addition of three bits (two significant bits and a previous carry) is a full adder. 4
0+0=0, 0+1=1, 1+0=1, 1+1=10 Half-Adder 110101 101010 The circuits needs two binary input variable: augend (x) and addend (y) bits, and two binary output variable: sum (S) and carry (C). Boolean function representations of Half-adder: Truth Table (a) S=x y+xy [truth table] C=xy (b) S= (x+y) (x +y ) C= xy (c) S = x y +xy [truth table] S= (x y +xy) = (C+x y ) C= xy (d) S = (x+y) (x +y ) C= (x +y ) (e) S= x y, C= xy Inputs Outputs augend addend carry sum x y C S 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 5
Half-Adder 110101 101010 6
Full-Adder 110101 101010 x The circuits needs three binary input variable: augend (x), addend (y) bits and carry yz from previous stage or carry input (z) and two binary output variable: sum (S) and output carry (C). S= x y z+x yz +xy z +xyz C= xy +xz +yz x yz augen d Inputs adden d Input carry Outputs output Carry sum x y z C S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 7
Full-Adder 110101 101010 Implementation of full adder in sum of products S= x y z+x yz +xy z +xyz C= xy +xz +yz 8
Full-Adder 110101 101010 Implementation of full adder with two half-adders and an OR gate S = x y z+x yz +xy z +xyz = xy z +x yz + xyz+ x y z = z (xy +x y) +z ( xy+ x y ) = z (xy +x y) + z (xy +x y) [XOR and XNOR are complement to each other] = z (x y)+ z(x y) yz = z (x y) x C= xy z +x yz+xy [from truth table] = z(xy +x y)+xy = z (x y) +xy 9
Subtractors 110101 101010 Subtractors The subtraction of two binary numbers may be accomplished by taking the complement of the subtrahend and adding it to the minuend. By this way subtraction becomes an addition operation requiring full adders for its implementation. It is possible to implement subtraction with a logic circuits in a direct manner. By this method, each subtrahend bit of the number is subtracted from its corresponding significant minuend bit to form a difference bit. If minuend bit is smaller than the subtrahend bit, a 1 is borrowed from the next significant position. A half-subtractor is a combinational circuit that subtracts two bits and produces their difference. A full-subtractor is a combinational circuit that performs a subtraction between two bits, taking into account that a 1 may have been borrowed by a lower significant stage. 10
Subtractors: Half-Subtractor 110101 101010 x y Half-Subtractor Input Variables: Minuend (x) and subtrahend (y) Output Variables: Borrow (B) and difference (D) B D Minue nd Inputs Subtra hend Borrow Outputs Differe nce x y B D 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 Interesting to note that, inclusion of a not gate can convert a half-adder into half-subtractor D=x y+xy B=x y [truth table] 11
12 Subtractors: Full-Subtractor 110101 101010 Full-Subtractor Input Variables: Minuend (x), subtrahend (y) and previous borrow (z) Output Variables: Output Borrow (B) and difference x (D). yz D= x y z+x yz +xy z +xyz (Similar to full adder) B= x y +x z +yz (similar to full adder except x is complemented) x yz Minuen d Inputs Subtrah end Input Borrow Output Borrow Outputs Differe nce x Y z B D 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 Note: It is possible to convert a full-adder into full-subtractor by merely complementing input x prior to its application to the gates that form the carry output
Subtractors: Full-Subtractor 110101 101010 Implementation of full subtractor with two half-subtractor and an OR gate D = x y z+x yz +xy z +xyz = xy z +x yz + xyz+ x y z = z (xy +x y) +z ( xy+ x y ) = z (xy +x y) + z (xy +x y) [XOR and XNOR are complement to each other] = z (x y)+ z(x y) yz = z (x y) x B= xyz +x y z+x y [from truth table] = z(xy +x y )+x y = z (x y) +x y y x z 13
Code Conversion 110101 101010 Importance of Code Conversion The availability of a large variety of codes for the same discrete elements of information results in the use of different codes by different digital systems. It is sometimes necessary to use the output of one system as the input to another. A conversion circuit must be inserted between the two systems if each uses different codes for the same information. Code Converter A code converter is a combinational circuit that makes the two systems compatible even though each uses a different binary code. Binary Code A Code Converter Binary Code B 14
Code Converter Example: BCD to excess-3 code 110101 101010 BCD to excess-3 code converter Since each code uses four bits to represent a decimal digit, there must be four input variables and four output variables. w= (5,6,7,8,9) x= (1,2,3,4,9) y= (0,3,4,7,8) z= (0,2,4,6,8) Note that four binary variables have 16 combinations, only 10 of which are listed in the truth table. The other 6 is not listed can be considered as don t care. d= (10,11,12,13,14,15) Truth Table 15
Code Converter Example: BCD to excess-3 code (Cont.) 110101 101010 From truth table we obtainedw= (5,6,7,8,9), x= (1,2,3,4,9), y= (0,3,4,7,8), z= (0,2,4,6,8) Don t care conditions, d= (10,11,12,13,14,15) Now using map method to simplify the functions- 16
Code Converter Example: BCD to excess-3 code (Cont.) 110101 101010 Logic Diagram of BCD to excess-3 code converter 17
BCD to Seven-segment Decoder 110101 101010 Exercise: 4-14 A BCD to seven-segment decoder is a combinational circuit that accepts a decimal digit in BCD and generates the appropriate outputs for the selection of segments in a display indicator used for displaying the decimal digit. The seven output of the decoder (a,b,c,d,e,f,g) select the corresponding segments in the display as shown in figure a. The numeric designation chosen to represent the decimal digit is shown in figure b. Design the BCD to seven segment decoder circuit. a: Segment designation b: Numerical designation for display 18
BCD to Seven-segment Decoder 110101 101010 From truth table we obtaineda= (0,2,3,5,6,7,8,9) b= (0,1,2,3,4,7,8,9) c= (0,1,3,4,5,6,7,8,9) d= (0,2,3,5,6,8,9) e= (0,2,6,8) f= (0,4,5,6,8,9) g= (2,3,4,5,6,8,9) Don t care conditions, d= (10,11,12,13,14,15) 19
BCD to Seven-segment Decoder 110101 101010 From truth table we obtaineda= (0,2,3,5,6,7,8,9) b= (0,1,2,3,4,7,8,9) c= (0,1,3,4,5,6,7,8,9) d= (0,2,3,5,6,8,9) e= (0,2,6,8) f= (0,4,5,6,8,9) g= (2,3,4,5,6,8,9) Don t care, d= (10,11,12,13,14,15) CD AB CD AB CD CD AB AB X X X X X X X X X X X X X X X X X X X X X X X X AB a= A+C+B D +BD CD AB b= B +C D +CD c= B +C +D d= A +B D +B C+BC D+CD CD CD AB X X X X X X X X X X X X X X X X X X e= B D +CD f= A+C D +BD +BC g= A+B C+BC +BD 20
BCD to Seven-segment Decoder 110101 101010 D C B A a= A+C+B D +BD b= B +C D +CD c= B +C +D d= A +B D +B C+BC D+CD e= B D +CD f= A+C D +BD +BC g= A+B C+BC +BD a b c d f e 21 g
Truth Table BCD to Seven-segment Decoder 110101 101010 Exercise: 4-12 Design a combinational circuit that detects an error in the representation of a decimal digit in BCD. The output of the circuit must be equal to logic-1 when the inputs contain any one of the six unused bit combinations in the BCD code. B A C E= AB+ AC A B C D E 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 22
Multilevel NAND Circuits 110101 101010 Implementation of basic gates by NAND gate The NAND gate is said to be a universal gate because any digital system can be implemented with it. Combinational circuits and sequential circuits as well can be constructed with this gate because the flip-flop circuit can constructed from two NAND gates connected back to back. NOT gate by NAND gate x x AND gate by NAND gate x y (xy) ((xy) ) = xy OR gate by NAND gate x x (x y ) = x+y y y 23 Lecture materials on "Simplification of Boolean Functions" By- Mohammed abdul kader, Assistant Professor, EEE, IIUC
Multilevel NAND Circuits 110101 101010 Procedure of Boolean function Implementation-Block Diagram method 1. From the given algebric expression, draw the logic diagram with AND, OR and NOT gates. Assume that both the normal and complement inputs are available. 2. Draw a second logic diagram with the equivalent NAND logic, substitute for each AND, OR and NOT gate. 3. Remove any two cascaded inverters from the diagram, since double inversion does not perform a logic function. Remove inverters connected to a single external inputs and complement the corresponding input variable. The new logic diagram obtained is the required NAND gate implementation. 4. The procedure is illustrated in the next slide. 24 Lecture materials on "Simplification of Boolean Functions" By- Mohammed abdul kader, Assistant Professor, EEE, IIUC
Multilevel NAND Circuits 110101 101010 Implementation of F=A(B+CD)+BC with NAND gates 25 Lecture materials on "Simplification of Boolean Functions" By- Mohammed abdul kader, Assistant Professor, EEE, IIUC
Multilevel NAND Circuits 110101 101010 Implementation of F=(A+B ) (CD+E) with NAND gates 26 Lecture materials on "Simplification of Boolean Functions" By- Mohammed abdul kader, Assistant Professor, EEE, IIUC
Multilevel NOR Circuits 110101 101010 Implementation of basic gates by NOR gate The NOR gate is also called universal gate because all basic gates, combinational circuit as well as sequential circuit can be constructed with NOR gate NOT gate by NOR gate x x OR gate by NOR gate x y (x+y) ((x+y) ) = x+y x x 27 AND gate by NOR gate y y (x +y ) = xy Lecture materials on "Simplification of Boolean Functions" By- Mohammed abdul kader, Assistant Professor, EEE, IIUC
Multilevel NOR Circuits 110101 101010 Implementation of F=A(B+CD)+BC with NOR gates 28 Lecture materials on "Simplification of Boolean Functions" By- Mohammed abdul kader, Assistant Professor, EEE, IIUC