Research of Germanium on Insulator

1 Research of Germanium on Insulator Haiyan Jin, visiting scholar Collaborators: Eric Liu and Prof.Nathan Cheung EECS, UC Berkeley The work is supported by the UC Discovery FLCC and IMPACT programs

2 Institute of Microelectronics Peking University, Beijing, China ULSI SOC MEMS Wang Yangyuan Professor and Director of Institute of Microelectronics Professors : 49 Undergraduate students : 60~80/year Graduate students : 40~55/year Seminor Seminar

3 National Key Micrometer/Nanometer Processing Lab Over 10-million USD process and analyzing equipment in a 900m 2 clean room. CMOS, Bipolar, especially MEMS baseline process.

4 OUTLINE Part I State of the art on GeOI An introduction to GeOI Main approaches for GeOI fabrication Part II Our research about GeOI Bulk and Epi Ge wafer are transferred on substrate A new method was presented to extract mobility Mobility and interface trap density are improved Seminor Seminar

5 Part I State of the art on GeOI An introduction to GeOI What is GeOI? GeOI = Ge + OI Si SiO2 Si substrate SOI Ge SiO2 Si substrate GeOI

6 Why GeOI? Advantages of Ge Significantly higher bulk electron and hole mobilities Higher thermal injection velocity Lower Schottky barrier due to smaller Ge band-gap Allowing a smaller VDDV DD Advantages of on-insulator Partially overcoming the high leakage current Potential substrate for FinFET structures

7 Texas Instruments' first IC made by Jack Kilby in 1958 The first transistor was invented in 1947 by William Shockley, John Bardeen and Walter Brattain. The first transistor and IC are all made of Germanium

8 The Myth: Si is the newer technology Identified by Lavoisier in 1787 In 1886, Coca Cola was invented B C N Al Si P Ga Ge As It s the real thing. Germanium. In Sn Sb Identified in 1886

9 Part I State of the art on GeOI An introduction to GeOI Main approaches for GeOI fabrication Ge condensation method Rapid Melt Growth Mechanical and Thermal Ion-Cut

10 Ge condensation method (This method is first presented by S.Nakaharai, MIRAI-ASET, Japan) Planar defects TEM Ge condensation technique: (a) Commercial SOI wafer, (b) SiGe layer is grown epitaxially on an SOI wafer, (c) Oxidation of S, (d) Complete Ge condensation and (e) GeOI wafer after removing surface oxide.

11 Rapid Melt Growth (RMG) LTO (a) Seed windows are etched (d) Ge stripes is covered by LTO (b) Ge is deposited by CVD (c) Ge film is patterned into stripes TEM image of GeOI obtained by RMG Y.Liu et al., Stanford University

12 Mechanical and Thermal Ion-Cut H + (1) R p Si 3 N 4 or SiO 2 Ge wafer Si wafer O 2 plasma Edge initiated cleavage (Mechanical cut) (a) H+ implantation to Ge (dose:6x10 16 /cm 2 ); i) LPCVD Si 3 N 4 on Si ii)thermal SiO 2 on Si (b) Oxygen plasma activation for 15sec (c) Ramp anneal at 200~250 C (2) A 200mm GeOI formed by thermal-cut method (Soitec, France) Anneal at T>270 C (Thermal cut)

13 GeOI device P-Channel Germanium FinFET Based on RMG Jia Feng, et al.(stanford University), EDL, 2007 First Deep Sub-Micron GeOI PMOSFET A.Pouydebasque, et al. (CEA-LETI MINATEC, FRANCE)

14 Advantages of ion-cut method Wafer-scale transfer for all wafer sizes Layout Pattern independent High quality GeOI decided by bulk Ge or Epi-Ge An extension of mature SOI technology

15 Part II Our research about GeOI Bulk and Epi Ge wafers were transferred A new method was presented to extract mobility Mobility and interface trap density are improved

16 Large-area GeOI formed by layer transfer processing 400nm Ge Transferred Germanium 850nm Ox Si substrate 850nm Ox/Si 1 cm Fabrication processes: (1) HF/DIW surface cleaning (pre-bonding cleaning); (2) N 2 plasma activation; (3) Direct bonding; (4) Post-bonding annealing at 220 ; (5)Mechanical-cut or thermal-cut at T>270 C ;

17 Pillow defect The pillow defects of GeOI annealt at various temperature. No Ge wafer surface cleaning is performed before wafer bonding. The origin of pillow defects is usually attributed to contamination on the Germanium wafer surface such as hydrocarbons.

18 Layer Transfer Process Improvement (A) (B) 20 µm 20 µm (A)GeOI sample after 540 C anneal for 90 min without prebonding cleaning B)GeOI sample after 540 C anneal for 90 min with pre-bonding cleaning

19 Plasma surface activation Bonding energy of Ge with (I) SiO2/Si, O2 plasma surface activation; (II) Si3N4/Si, O2 plasma surface activation; (III)SiO2/Si, N2 plasma surface activation.

20 GeOI surface smoothing with CMP GeOI surface can be smoothed down to RMS =0.3nm by CMP (CMP slurry: 0.2µm SiO2 particle mixed with KOH) GeOI substrates are ready for device fabrication

21 The GeOI surface smoothing by CMP 200nm Z[nm] 0.0 25.0 50.0 75.0100.0 RMS:11.8 nm; Ra:9.5 nm Z-range: 87.8 nm (a) as-cut GeOI 0.0 0.20 0.40 0.60 0.80 1.0 X[µm] 200nm (b) after CMP and HF dip Z[nm] 0.0 25.0 50.0 75.0100.0 0.0 0.20 0.40 0.60 0.80 1.0 RMS: 0.3 nm; Ra: 0.23 nm Z-range: 3 nm X[µm]

22 300mm Ge wafers (UMICORE)

23 Surface steps of Epi-Ge wafer AFM image of a Epi-Ge surface

24 Large area Epi-Ge is transferred Epi Ge Si substrate Epi Ge Si substrate donor donor GeOI GeOI 5cm 5cm 3 days furnace annealing 7 days furnace annealing Temperature increases slowly from 120 to 300

25 Part II Our research about GeOI Bulk and Epi Ge wafer are transferred on substrate A new method was presented to extract mobility Mobility and interface trap density are improved

26 Pseudo MOSFET Measurement (4-probe configuration) 1 V 2,3 2 V Ge A 3 4 BOX P + -Si substrate I 1,4 _ V G + Rapid electrical evaluation of semiconductor-oninsulator substrate Extracting interface carrier mobility of GeOI

27 The pseudo-mosfet experimental data Experimental data Theoretical data G=I 1,4 /V 2,3 (Ω 1 ) 0.00056 0.00052 (III) Accumulation (II) Depletion (I) Inversion 0.00048 V FB =-10.2V V T =6.8V G vs VG plot, which shows the accumulation, depletion and inversion regions. In depletion mode, the bulk Ge mobility is extracted by fitting theoretical data with experimental data, which is 143.8cm 2 /V-sec. -30-15 0 15 30 V G (V)

28 In inversion mode, Channel conductance G ch is given by: Gch= fg µn0 Cox (VG-VT) /[1+θ (VG-VT)]

29 Differentiating G ch, we obtain: G ' ch = dg dv ch G = f g µ n0 C ox [ + θ ( V V )] 2 1 G T G G ch ' 0.5 ch = ( ) 0.5 f µ C ( V V ) g n0 ox G T

30 0.04 Experimental data G ch /G'ch0.5 (S 0.5 ) 0.02 0.00 The extraction of the threshold voltage VT; The low field electron mobility at interface was extracted from the slope of the fit lines, which is 87.3cm 2 /V-sec. V T =6.8V Slope=(f g µ n0 C ox ) 0.5 10 20 30 V G (V) Inversion mode µ n0 =87.3cm 2 /V-sec

31 In accumulation mode: G ' ch = dg dv ch G = f g µ p0 C ox [ + θ '( V V )] 2 1 G FB G G ch ' 0.5 ch = ( ) 0.5 f µ C ( V V ) g p0 ox G FB

32 Experimental data G ch /G'ch0.5 (S 0.5 ) 0.02 0.01 0.00 Slope=(f g µ p0 C ox ) 0.5 Accumulation mode V µ p0 =117.5cm 2 FB =-10.2V /V-sec -20-10 V G (V) The extraction of the flatband voltage VFB; The low field hole mobility at interface was extracted from the slope of the fit lines, which is 117.5cm 2 /V-sec.

33 The pseudo-mosfet experimental data Experimental data Theoretical data G=I 1,4 /V 2,3 (Ω 1 ) 0.00056 0.00052 (III) Accumulation (II) Depletion (I) Inversion 0.00048 V FB =-10.2V V T =6.8V G vs VG plot, which shows the accumulation, depletion and inversion regions. In depletion mode, the bulk Ge mobility is extracted by fitting theoretical data with experimental data, which is 143.8cm 2 /V-sec. -30-15 0 15 30 V G (V)

34 I-V of intrinsic point-probe MOSFET in partially depleted GeOI I 1,4 V 2,3 1 2 3 4 I 1,4 =I bulk +I interface I bulk tge I interface GeOI W d (0~W dmax ) 400nm OX V G

35 I1,4 is given by: I 1,4 = + I bulk I int erface In depletion mode: Ibulk >> I int erface I ( t ) Ge wd NGe 2, 3 1,4 = Ibulk + Iint erface = Ibulk = f gqµ p V

36 G = I V = f qµ / 1,4 2,3 g p ( t w ) N Ge d Ge Ge Oxide Si substrate VOX VG w d = 2ε s qn Ge ψ = 2ε s qn Ge ( V G V FB V ox )

37 ( ) 2 A G = BV + C G g p Ge ( t C ) A = f qµ N + ε / Ge s ox B C = 2q = ( f ) µ 2 ε g p s N Ge ( ) 2 ( ) 2 2ε svfb f qµ N ε / C g p Ge s ox qn Ge

38 The pseudo-mosfet experimental data Experimental data Theoretical data G=I 1,4 /V 2,3 (Ω 1 ) 0.00056 0.00052 (III) Accumulation (II) Depletion (I) Inversion 0.00048 V FB =-10.2V V T =6.8V -30-15 0 15 30 V G (V) G vs VG plot, which shows the accumulation, depletion and inversion regions. In depletion mode, the bulk Ge mobility is extracted by fitting theoretical data with experimental data, which is 143.8cm 2 /V-sec.

39 The extraction of interface fixed charge density, Qf Ge BOX p + Si substrate Q f V FB = Φ Ge-Si Q f / C ox The extracted VFB by pseudo- MOSFET is used to obtain Qf The extraction of interface trap density, Qit G=I 1,4 /V 2,3 (Ω 1 ) 0.00057 V G : -30V to +30V V G : +30V to -30V 0.00054 0.00051 0.00048-30 -15 0 15 30 V G (V) Hysteresis behavior is observed when VG is swept along opposite directions. This is attributed to the interface traps between Ge and the buried oxide. The shift of VT is used to obtain interface trap density Oit. Seminor Seminar

40 Current GeOI Summary Interface fixed charge density, Q f ~10 11 q/cm 2 Interface trap density,q it ~10 11 q/cm 2 Interface hole mobility, µ p0 117.5 cm 2 /V-sec Interface electron mobility, µ n0 87.3 cm 2 /V-sec Bulk hole mobility, µ p 143.8 cm 2 /V-sec

41 Part II Our research about GeOI Bulk and Epi Ge wafer are transferred on substrate A new method was presented to extract mobility Mobility and interface trap density are improved

42 The condition of forming gas annealing Gas ratio : 10%H2, 90%N2 Gas flow : 8L/min Temperature : 400 ~600 Time : 10min or 30min at each temperature point Temperature( o C) 600 Temperature increases step by step 500 400 Sample2 fast ramp Sample1 slow ramp 0 50 100 Time (min)

43 Interface trap (Q it ) and Interface charge(q f ) improved through forming gas annealing 100 100 Q f (10 10 q/cm 2 ) 10 1 Q f Slow ramp Fast ramp Q it (10 10 q/cm 2 ) 10 1 Q it Slow ramp Fast ramp 0.1 400 500 600 0.1 400 500 600 T( o C) T( o C) (A) Both interface trap density Qit and interface fixed charge density Qf decrease to 10 10 q/cm 2 after forming gas annealing. (B)

44 Carrier mobility improved through forming gas annealing Mobility(cm 2 /Vs) 500 400 300 200 100 µ pb (Slow ramp) µ pb (Fast ramp) Bulk Mobility (cm 2 /Vs) 450 300 150 µpi (slow ramp) µni (slow ramp) µpi (fast ramp) µni (fast ramp) Interface 0 400 500 600 0 400 500 600 T ( o C) T ( o C) (A) (B) 3X improvement of bulk hole mobility with fast ramp 3X improvement of interface hole mobility with fast ramp 2X improvement of interface electron mobility with slow ramp

45 In Progress Prototype GeOI MOSFET performance with ALD high-k dielectric ( with Prof. J. Chang, UCLA) Demonstrate Strained GeOI layer transfer

46 Conclusion GeOI is a potential next-generation substrate A new pseudo-mosfet methodology is presented to extract bulk mobility of GeOI Mobility and Interface trap is improved by forming gas annealing

47 Thanks!