Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.2 pp. 232-242
Two-stage op-amp
Analysis Strategy Recognize sub-blocks Represent as cascade of simple stages
Total op-amp model Input differential pair Common source stage
DC operating point MOSFET I D [µa] V eff M1 25 0.235 M2 25 0.235 M3 25 0.247 M4 25 0.247 M5 50 0.350 M6 50 0.332 M7 50 0.332 M8 50 0.332
Small signal parameters MOSFET I D [µa] V eff g m [µa/v] r ds M1 25 0.235 208 M2 25 0.235 800kΩ M3 25 0.247 M4 25 0.247 1.43MΩ M5 50 0.350 285 715kΩ M6 50 0.332 M7 50 0.332 M8 50 0.332 400kΩ Note: l n = 0.050 V -1 ; l p = 0.028 V -1
Total op-amp model: Low frequency gain Input differential pair Common source stage ( ) a v1 = g m1 r ds2 r ds4 a v1 = ( 208mA V) ( 800kW 1.43MW) a v1 =106 ( ) a v2 = g m2 r ds5 r ds8 a v2 = ( 285mA V) ( 400kW 715kW) a v2 = 73
Total op-amp model with capacitances Gate of M5 Ê C g = (900mm)(10mm) 4.17E - 4 F Ë m 2 C g = 3.74 pf ˆ Load: scope probe 10pF
Total op-amp model with capacitances f p1 = f p1 = First stage pole 1 2p( r ds2 r ds4 )C g5 1 2p 800kW 1.43MW ( ) 3.74pF ( ) f p1 = 82kHz Second stage pole f p1 = f p1 = 1 2p( r ds5 r ds8 )C L 1 2p 400kW 715kW ( ) 10 pf ( ) f p1 = 61kHz
Open loop transfer function Product of individual stage transfer functions A( jw) = g m1 ( r ds2 r ds4 )g m5 ( r ds5 r ds8 ) 1 + jw2p( r ds2 r ds4 )C g5 ( )C L [ ][ 1 + jw2p r ds5 r ds8 ]
Two-stage op-amp: Simulation Schematic
DC Operating Point Simulation
Bode plot Magnitude, phase on log scales Pole: Root of denominator polynomial
Open loop Bode plot Product of terms : Sum on log-log plot
Open Loop Bode Plot Simulation
Stability example: Closed loop follower Negative feedback: Output connected to inverting input
Unity gain: Why bother? v out = Ê Á Ë R L R L + R S ˆ v in v out = v in No buffer: Voltage divider Signal reduced due to voltage drop across R S With buffer: No current required from source
Lab 9 Problem: Instability Oscillation superimposed on desired output Output for zero input Why? Need...
Controls: ES3011 in 20 minutes General framework A: Forward Gain b: Feedback Factor fraction of output fed back to input
Example: Op-amp, Noninverting Gain A: Forward Gain Op-amp open loop gain V out =A(V + -V - ) Transfer function A(jw) b: Feedback Factor b = R 1 R 1 + R 2
Output v out = A v in -bv 142 4 out 3 Solve for v out /v in Closed Loop Gain ( ) v + - v - v out = Av in - Abv out ( 1 + Ab)v out = Av in v out v in = A 1 + Ab
Op-amp with negative feedback If Ab >> 1 v out A = v in 1 + Ab ª A Ab Æ v out ª 1 v in b Closed loop gain determined only by b Advantage of negative feedback: Open loop gain A can be ugly (nonlinear, poorly controlled) as long as it's large!
Example: Op-amp, Noninverting Gain b: Feedback Factor R 1 b = R 1 + R 2 Closed loop gain v out v in = R 1 + R 2 R 1 = 1 b
Reexamine closed loop transfer function Output with no input: infinite gain Infinite when 1+Ab = 0 Condition for oscillation: 1+Ab = 0 In general A, b functions of w v out v in = A 1 + Ab If there's a frequency w at which 1+Ab = 0: Oscillation at that frequency!
b = 1 Æ v out v in = A 1 + A Use A(jw), solve for 1+A = 0 No thanks! Example: follower A( jw) = g m1 ( r ds2 r ds4 )g m5 ( r ds5 r ds8 ) 1 + jw2p( r ds2 r ds4 )C g5 ( )C L [ ][ 1 + jw2p r ds5 r ds8 ]
Reexamine condition for oscillation 1+Ab = 0 Æ Ab = -1 Magnitude and phase condition: Ab = 1 AND Ab = -180 Easier to get from Bode plot
Look at original Ab for 2 stage op-amp Find w at which Ab = 1; Check Ab -180? Trouble!
Simulation Ab for 2 stage op-amp
Move one pole to lower frequency How? Compensation: Dominant Pole
Need to increase capacitance by 1000X: Compensation: Dominant Pole BAD! Die area cost
Miller Effect Impedance across inverting gain stage G Reduced by factor equal to (1+G)
Math for Miller effect i x = v x - (-Gv x ) Z i x = v x ( 1 + G ) Z v x = Z in = i x Z 1 + G ( ) Impedance across inverting gain stage G Reduced by factor equal to (1+G)
Example: Impedance is capacitive Capacitance multiplied by (1+G) Z in = Z 1+ G ( ) Z = 1 sc Æ Z in = 1 s( 1 4 + 2 G 4 )C 3 C eq Equivalent capacitance higher by factor 1+G Problem for high bandwidth amplifiers Opportunity for compensation...
Miller Compensation Need effect of large capacitance Use Miller effect to multiply small on-chip capacitance to higher effective value Effect of large capacitance without die area cost of large capacitance
New schematic Add C C across 2nd stage
New transfer function
No oscillation! New step response
How stable is new transfer function? Phase margin = Phase lag at Ab = 1 minus (-180 ) "Phase margin"
Dominant pole op-amp model Simpler model with dominant pole from C C
Approximate dominant pole transfer function A(jw) ª g m1 ( r ds2 r ds4 )A 2 1+ jw( r ds2 r ds4 )A 2 C C [ ] A 2 = g m5 ( r ds5 r ds8 )
Depends only on Unity gain frequency Input stage transconductance g m Compensation capacitor C C A(jw) ª g ( m1 r ds2 r ds4 )A 2 w( r ds2 r ds4 )A 2 C C [ ] A(jw) =1 at w T w T ª g m1 C C
I= C dv/dt Slew rate Only limited current I BIAS available to charge, discharge C C
I= C dv/dt fi Slew rate dv dt I BIAS = CC
Summary Op-amp: Stability Compensation Miller effect Phase Margin Unity gain frequency Slew Rate Limiting