Part 6: High Dielectric Constant (k), Gate Electrode, & Channel Materials O 2 gate ide is approaching physical limits Thickness & Current M O S poly-crystalline V Source W Source Contact Insulator n + source + V gate n ++ Poly Gate Contact or Electrode O 2 - Gate ide - - - - - - - - - - - - - - channel p- Wafer Drain Contact Insulator n + drain V Drain + Crystalline L t C oka t t EOT k k t highk highk Frank, Dennard, Nowak, Soloman, Wong & Taur, Proc. IEEE Circuit & Devices, 89 (2001) 259 M. Houssa et al., Materials Science and Engineering R, 51 (2006) 37-85 1 Bandgap versus Dielectric Constant (k) Trend: As k, E g e E e Hik c e e E Hik c Robertson, MRS Bulletin (March 2002) p. 217 Robertson, J. Vac. Sci. Technol. B, 18(3), May/Jun 2000 2 1
Band Offsets: High k on Aspects to Consider: 1. E g 2. E c & E v 3. m eff Recall in Barrier Region: e So: kx J e * 2kx k k 2 m ( V E ) eff m eff e m, J eff e E e Hik c e e E Hik c Robertson, MRS Bulletin (March 2002) p. 217 J g ( kt ) k fleftde Ef frightde E f dk pˆ 1 E where p mg & g & g m k 3 Band diagrams of MOS compare O 2 to high k materials O 2 ; κ~3.9 HfO 2 ; κ~25 PbZr (0.53) Ti (0.47) O 3 κ~200 Low S/C doping Southwick &, IEEE TDMR, 6(2), (2006) 136-145 4 2
Need to consider the Thermodynamics of the materials system Ellingham diagram G vs- Temperature The more negative G is, the more stable the materials system is. Example: Grow Y 2 O 3 on, will steal ygen from Y 2 O 3 to form interfacial layer (IL) of O 2. Why? Y 2 O 3 O 2 Al 2 O 3 G G O2 Y2O3 O more stable than Y O 2 2 3 R. DeHoff, Thermodynamics, (Prentice Hall, 1996) Ch. 11, fig. 11.4 5 Interfacial layer (IL) of O 2 Present for HfO 2 O 2 IL HfO 2 Crystalline Channel TiN E OT n m 3.5 3 2.5 2 1.5 1 0.5 0 EOT WRT t O2 & t HfO2 0 2 4 6 8 10 12 14 t HfO2 nm k t t t, eff, physical highk khighk 6 3
EOT: 7 nm HfO 2 & 1nm O 2 : EOT ~ 2 nm 2 dv d 2 dx dx ok 8 nm HfO 2 : EOT ~ 1.25 nm Southwick &, IEEE TDMR, 6(2), (2006) 136-145 7 - NVM Floating Gate NVM Versus SONOS (O 2-3 N 4 -O 2 -) NVM SONOS Advantages over Floating Gate: Replace poly- floating gate with 3 N 4 Stored charge lies in defect (bound) states below 3 N 4 conduction band Improved endurance - single defect will not cause the discharge/leakage of carriers Can reduce Thickness of TO 3 N 4 thinner than floating gate Poly Carriers not Floating around Minimizes interaction with neighboring memory cells Thus, can scale down memory cell size BL CTL TL BL = Blocking Layer CTL = Charge Trapping Layer TL = Tunnel Layer Todd Wallinger, SONOS Eases Non-Volatile Memory Integration in SoC, Semiconductor International (2007) 8 4
- NVM BL CTL TL BL CTL TL BL TL Flat Band Condition Poly Floating Gate Poly Energy Band Diagram Energy Band Diagram 3 N 4 = CTL Gate stack scaled down in thickness & cell area Todd Wallinger, SONOS Eases Non-Volatile Memory Integration in SoC, Semiconductor International (2007) 9 - NVM Flat Band Condition BL TL Poly 3 N 4 Energy Band Diagram Gate stack scaled down in thickness & cell area Todd Wallinger, SONOS Eases Non-Volatile Memory Integration in SoC, Semiconductor International (2007) 10 5
- NVM Multilayer high k dielectric films for memory applications SONOS (poly O N O ) MANOS (metal Al 2 O 3 N O ) TANOS (/O 2 /N/A 2 O 3 /TaN) Sanghun et al., IEEE TED 52 (2005) 2654.pdf Lee et al., Symposium on VLSI Technology Digest of Technical Papers (2006 11 Low Dielectric Constant (k) Materials What About Low-k Dielectric Materials? What would they be used for? C oka t 12 6
Compare and Contrast following Memory Gate Stacks: Stack #: Metal BL CTL TL -S/C Stack 1: TiN O2 3 N4 O 2 p Stack 2: TiN Al 2 O 3 Ta 2 O 5 HfO 2 p Stack 3: TiN La 2 O 3 ZnO ZrO 2 p 13 14 7
15 16 8
17 18 9
19 MOSFETs Bandgap Engineering of Channel Consider: Bandgap, mobility, effective mass,lattice matching, quantum confinement of carriers Lattice Constants: a = 5.4309 Å a Ge = 5.6577 Å Cullity, Elements of X-ray Diffraction, 2 nd Ed (1978) Appendix 5 From Principles of Electronic Materials and Devices, Third Edition, S.O. Kasap ( McGraw-Hill, 2005) 20 10
MOSFETs Bandgap Engineering of Channel Consider: Bandgap, mobility, effective mass, lattice matching, quantum confinement of carriers Lattice Constants: a = 5.4309 Å a Ge = 5.6577 Å Cullity, Elements of X-ray Diffraction, 2 nd Ed (1978) Appendix 5 IBM RJ Antoniadis et al., Continuous MOFET Performance Inc with Scaling - Strain & Channel Matl (2006) 21 Part 5: Quantum Effects in MOS Devices Quantization: (cont.) 2D gas in channel SOI Gate-all-around (GAA) MOSFET: Gate-All-Around (GAA) MOSFET is an SOI transistor in which the gate ide and the gate electrode are wrapped around the channel region. Fabricated using an SOI CMOS process to which two process steps are added a photolithographic step a wet etch step during which a cavity is formed under previously patterned silicon islands. The remarkable features of this MOSFET are that there are two channels (at the top and the bottom of the silicon film, The entire channel area is surrounded by good-quality gate ide and the gate electrode. Colinge & Colinge, S/C Devices 22 11