NRAM: High Performance, Highly Reliable Emerging Memory

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NRAM: High Performance, Highly Reliable Emerging Memory Sheyang Ning,2, Tomoko Ogura Iwasaki, Darlene Viviani 2, Henry Huang 2, Monte Manning 2, Thomas Rueckes 2, Ken Takeuchi Chuo University 2 Nantero Inc. Santa Clara, CA

Outline l Introduction of NRAM l Single NRAM cell and cell array measurement setup l NRAM characteristics l DC-IV curve l Set and reset program characteristics l Large on/off ratio l High temperature program l High endurance l Conclusion Santa Clara, CA 2

Introduction of NRAM Performance DRAM NRAM Nano-RAM, Carbon nanotube based resistive memory NAND flash Santa Clara, CA 3

Compare with Conventional Memories = good Performance Scalability Endurance Non-volatile = bad DRAM NAND flash NRAM 20 ns pulse [] Single cell 5 nm [2] Single cell 0 2 [3] 000 years@ 85ºC [2] []. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 204, pp. 96 97. [2]. Nantero Presentation for ITRS ERD/ERM, International Technology Roadmap for Santa Clara, CA Semiconductors (ITRS), 203. [3]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837 2844, Sept. 205. 4

Compare with Emerging Memories Material Resistive switching on read ReRAM [] PRAM [2] NRAM [3] Al x O y Ge 2 Sb 2 Te 5 Filament size Phase change Carbon nanotube (CNT) Tunneling current between CNTs Endurance 0 8 0 9 0 2 Current High High Low []. S. Ning et al., Solid-State Electronics, vol. 03, pp. 64 72, Jan., 205. [2]. H. Y. Cheng et al., IEEE Int. Electron Devices Meeting, 203, pp. 30.6. 30.6.4. [3]. S. Ning et al., Symp. on VLSI Tech., 204, pp. 96 97. [4]. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 205, pp. 98-99. Santa Clara, CA 5

Physical Mechanism R cell 800 kω Small distance R cell GΩ Large distance []. S. Ning et al., in VLSI Symp. Tech. Dig., Jun. 204, pp. 20 2. Santa Clara, CA [2]. Nantero presentation, Int. Tech. Roadmap for Semiconductors (ITRS), 203. 6

Physical Mechanism Set: attraction force Reset: repulsive force Electrical induction + Heat caused phonon vibration []. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837 2844, Sept. 205. Santa Clara, CA 7

Outline l Introduction of NRAM l Single NRAM cell and cell array measurement setup l NRAM characteristics l DC-IV curve l Set and reset program characteristics l Large on/off ratio l High temperature program l High endurance l Conclusion Santa Clara, CA 8

Single NRAM Cell and Cell Array Test 40 nm NRAM single cell 6 nm, 4 Mbits NRAM cell array V d NRAM cell WL BL 0 SL 0 BL N SL N V g NRAM cell BL SL Oscilloscope NRAM testchip Set voltage Reset voltage +V Set 0 V 0 V +V Reset []. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837 2844, Sept. 205. Santa Clara, CA [2]. G. Rosendale et al., Proceedings of the European Solid-State Circuits Research Conference (ESSCIRC), Sept. 200, pp. 478 48. 9

Outline l Introduction of NRAM l Single NRAM cell and cell array measurement setup l NRAM characteristics l DC-IV curve l Set and reset program characteristics l Large on/off ratio l High temperature program l High endurance l Conclusion Santa Clara, CA 0

I d (µa) 00 0 0 0 2 0 3 0 4 DC-IV Curve Single cell bi-polar program Set Reset Butterfly curve -3-2 - 0 2 3 V d (V) 0 2 3 V d (V) []. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 204, pp. 96 97. Santa Clara, CA I d (µa) Current vibration due to long term voltage stress on CNTs 5 0 5 0 Same cell, reset curve Trigger voltage

Low Program Current Single cell DC I compliance = 5 µa, 30 µa, and 00 µa Current (A) 0 2 0 4 0 6 0 8 0 0 0 2 00 µa 30 µa 5 µa Set Voltage Reset Single cell AC I peak < 20 µa Reset Current (µa) 40 20 0-20 0 50 00 50 Time (ns) 0.72pJ 0 50 00 50 Time (ns) []. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837 2844, Sept. 205. Santa Clara, CA [2]. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 204, pp. 96 97. 2 Set Current (µa) 20 0-20 -40 0.57pJ Voltage (V) Voltage (V)

Reset Characteristic l Cell array measurement, Reset is driven by both voltage and current BL = 0 V SL=V program WL= V gate Reset BER (a.u.) 2 0 0.6 0.8 0.8 WL=0.4 a.u., SL from 0 to a.u. 0.6 0.4 Santa Clara, CA []. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 205, pp. 98-99. 3

Program voltages (a.u.) Program voltages (a.u.) Set and Reset Voltages l Use incremental pulse programing on single cell 0.8 0.6 0.4 Reset voltage Set voltage (absolute value) 0 6 0 7 0 8 0 9 0 0 0 0 0.2 2 Write cycles 0 6 0 7 0 8 0 9 0 0 0 0 2 Write cycles Cumulative program success l Three randomly chosen NRAM cells 00% 80% 60% 40% 20% 0% Reset []. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837 2844, Sept. 205. Santa Clara, CA 4 cell cell 2 cell 3 Reset voltage (V) Cumulative program success 00% 80% 60% 40% 20% 0% Set cell cell 2 cell 3 Set voltage (V)

l Single cell measurement Large On/Off Ratio > 00 times on/off ratio Possible for multi-level cell (MLC) Resistance (Ω) 0 9 0 8 0 7 0 6 0 5 0 4 Read at V Resistance.3 0 7 Ω 0 5 Ω 0 50 00 50 200 Read cycles []. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 204, pp. 96 97. Santa Clara, CA 5

High Temperature Program l Single cell measurement, stable program voltage at different temperatures Reset failure rate (a.u., log scale) 25 85 25 Reset 0 0.5 Reset voltage (a. u.) 25 85 25 0 0.5 Set voltage (a.u.) Santa Clara, CA []. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837 2844, Sept. 205. 6 Set failure rate (a.u., log scale) Set

Resistance (Ω) High Endurance Single cell Cell array 0 8 5 Reset BER 0 7 HRS.25MΩ 4 Set BER 0 6 0 5 LRS 200kΩ 0 4 0 6 0 7 0 8 0 9 0 0 0 0 2 Write cycles Program BER (a.u.) 3 2 0 0 3 0 4 0 5 0 6 0 7 0 8 Write cycles []. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837 2844, Sept. 205. Santa Clara, CA [2]. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 205, pp. 98-99. 7

High Endurance l Cell array does not wear-out after 0 8 write cycles Set BER (a.u.) Set BER after 0 3 write cycles Set BER after 0 8 write cycles Set voltage 0.8 0.6 0.4 0.2 0.9 0.8 0.7 0.6 0 0.5 2 3 4 5 Verify-set pulses Set BL voltage (a.u.) Reset BER after 0 3 write cycles Reset BER after 0 8 write cycles Reset voltage 2 3 4 5 Verify-reset pulses []. S. Ning et al., Japanese Journal of Applied Physics (JJAP), vol. 55, no. 4S, 206. Santa Clara, CA [2]. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 205, pp. 98-99. 8 Reset BER (a.u.) 0.8 0.6 0.4 0.2 0 0.9 0.8 0.7 0.6 Reset SL voltage (a.u.)

Outline l Introduction of NRAM l Single NRAM cell and cell array measurement setup l NRAM characteristics l DC-IV curve l Set and reset program characteristics l Large on/off ratio l High temperature program l High endurance l Conclusion Santa Clara, CA 9

Conclusion l NRAM is an emerging nonvolatile memory cell which has performance between DRAM and NAND flash. l Compared with other emerging nonvolatile memories, NRAM has competitive characteristics, including, lower program current, large on/off ratio, large endurance, high temperature stability and long retention time. Santa Clara, CA 20

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