Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview

Pole-Zero Analysis of Low-Dropout (LDO Regulators: A Tutorial Overview Annajirao Garimella, Punith R. Surkanti and Paul M. Furth VLSI Laboratory, Klipsch School of Electrical and omputer Engineering New Mexico State University, Las ruces, NM 88003, USA Email: garimella@ieee.org, punith@nmsu.edu and pfurth@nmsu.edu Abstract Analyzing poles and zeros of a circuit is often essential for (a choose the appropriate topology for given specifications, (b understanding the frequency response of the circuit and (c stabilizing the circuit by choosing appropriate frequency compensation techniques. Analyzing poles and zeros of a low-dropout (LDO voltage regulator is often intriguing as (a the voltage/current control loop need to be broken for smallsignal analysis and (b the location of poles move with output load current. The objective of this tutorial is to provide a step-bystep procedure for analyzing poles and zeros in LDO regulators. To this end, two recent state-of-the-art LDO regulators from the literature are analyzed, explaining several intricacies involved. During the process, several frequency compensation techniques are elucidated. Index Terms Frequency compensation, pole-zero analysis, low-dropout (LDO regulators, cascode compensation, current buffers, LHP zero, power-supply rejection (PSR. V S g m R A i = G V Y G R 2 A i = 2 V g V2 m2 gd g mp R2 gs R g V mbu V 3 OUT Fig.. Block-level architecture of LDO with reverse nested Miller ompensation using current buffers. OUT I. INTRODUTION Stability at various loading conditions with improved line and load transient response is often the objective of lowdropout (LDO voltage regulator design [] [9]. A priori knowledge of poles and zeros assists the designer in choosing the correct topology before implementing the transistor level design. Finding the transfer function, and thus poles and zeros, of the voltage and/or current loops of the LDO regulator often helps in developing intuition of the circuit and parameters affecting the loop gain, pole-zero locations, gain-bandwidth product, phase margin and other stability conditions [0], []. In this tutorial, we explain a step-by-step procedure for performing small-signal analysis and deriving the equations of poles and zeros in LDO regulators. Two recent state-of-theart LDO regulators [9], [2] are analyzed. The outline of the paper is as follows: Section II outlines the steps for finding poles and zeros. Section III illustrates pole-zero analysis in a three-stage LDO with reverse nested Miller compensation using current buffers [9]. Sections IV and V laid a background for analyzing poles and zeros of a high PSR current-mode dual loop LDO [2] in Section VI. onclusions are drawn in Section VII. II. STEPS FOR FINDING POLES AND ZEROS The steps for obtaining the D gain, poles and zeros of a LDO regulator are For the given topology, draw the small-signal model 2 Break the corresponding voltage or current loop 3 Apply Kirchhoff s urrent Law (KL at each node 4 Solve the KL equations using symbolic manipulation software to obtain the transfer function 5 Set s (= jω = 0 to find the D gain of the amplifier 6 Factor and solve the numerator to obtain zeros 7 Applying the assumption of widely-separated poles, solve the denominator to obtain the poles, OR applying the assumption of widely-separated poles with a complex pole pair, solve the denominator to obtain the poles III. LDO WITH REVERSE NESTED MILLER OMPENSATION USING URRENT BUFFERS In this section, the three-stage LDO regulator of [9] is chosen as an example and detailed pole-zero analysis is performed. The block-level architecture of the LDO regulator is shown in Fig. and the adapted transistor-level schematic is shown in Fig. 2. This regulator uses with reverse nested Miller compensation using current buffers (RNMB. RNMB allows cancellation of a non-dominant pole with left-half plane (LHP zero, forming a stable LDO with adequate phase margin ( 75 o with improved transient line and load response. Referring to Fig. 2, the first stage is an NMOS foldedcascode differential amplifier (g m formed by transistors M - M 9 and the second stage is an NMOS common-source amplifier (g m2 formed by transistor M 0 with diode-connected transistor load M. The third stage is the power stage (g mp, formed by pass transistor M pass and sampling resistors R f and R f2. The output resistance of the first stage is R and

M 4 V b4 M 5 M gs,pass M PASS VLINE M 6 V b3 V Y R 2 2 M 7 V 2 gd,pass g mp G V V OUT V REF M gm M 2 V R f V FB I LOAD V b M 3 M 8 M 9 M 0 g m2 R f2 GND Break Loop Here Fig. 2. Schematic of the three-stage LDO regulator with reverse nested Miller compensation using current buffers, adpated from [9]. Generation of two LHP zeros using cascode compensation 2 current mirror (as inverting current buffer compensation is highlighted. i2 gd,pass v v Y R 2 2 v 2 v i gd i v S g R - m v S g v mbu G v Y g mg g m2 v R 2 gs,pass g mbu g mp v 2 R F v R FB F2 - Fig. 3. Small-signal model of the LDO regulator of Fig. 2 the lumped parasitic capacitance is. For the pass transistor M P ASS, significant parasitic capacitances gd,p ASS and gs,p ASS are considered for pole-zero analysis. The output resistance of the second stage at node V 2 is R 2 and the lumped parasitic capacitance can be approximated as gs,p ASS. The output resistance of the power stage at node V OUT is and is the output capacitor, either integrated or external capacitor. A. ompensation Network Reverse nested Miller compensation (RNM uses one inner loop and one outer loop [3]. ompensation capacitor is connected from node V OUT to low-impedance input node V of the current mirror formed by transistors M 8 -M 9 with transconductance. The current mirror acts as an inverting current buffer [9], [4] [7], denoted as in Fig.. and form the outer loop of the RNM. The inner loop is between nodes V 2 and V formed by compensation capacitor 2, series resistor R 2 and common-gate cascode transistor M 7, whose transconductance is G. The compensation capacitor 2 and resistor R 2 are connected between V 2 and V Y, where V Y is the source node of the common-gate transistor M 7, whose transconductance is G in Fig.. Transistor M 7 acts as a positive current buffer [9], [4], [8] [22] and the compensation network is popularly known as cascode compensation or Ahuja compensation. B. Small-signal Modeling The feedback is broken between node v F B and gate input of transistor M 2 as shown in Fig. 2. Let v S be the differential TABLE I SMALL-SIGNAL PARAMETERS OF LDO USING RNMB(FIG. 3 g m g m of M, M 2 R r o9 G r o7 (r o5 r o2 gd7 gd9 gs0 g m of M 8 G g m of M 7 g m2, r o0 g m, r o of M 0 R 2 r g o0 m 2 gd0 gs gs,p ASS gs,p ASS g mp, r op 3 g m, r o of M P ASS r op ( R f R f2 RL gd,p ASS * Omitting bulk capacitances for simplicity input voltage between the reference voltage v REF and the feedback voltage v F B. The open-loop small-signal diagram of Fig. 2 from v S to v F B is shown in Fig. 3. The first stage is non-inverting so as to ensure that the overall gain from v REF to is non-inverting. Equations for the small-signal parameters of the regulator of Fig. 3 are given in Table I. The first-stage differential amplifier is represented with voltage-controlled current source (VS g M v S. The output of the first-stage is v. The second-stage is represented with VS g M2 v. The output of the third-stage is. The compensation capacitor 2 and resistor R 2 are connected between v 2 and v Y, where v Y is the source node of the common-gate transistor M 7, whose impedance to ground is

/G. The positive current buffer between v Y and v is represented with VS G v Y. The compensation capacitor is connected between and v, where v is the low impedance node with / as the impedance to ground. The inverting current buffer between v and v is represented with VS v. gd,p ASS is connected between v 2 and, which forms a feedforward path.. Applying Kirchhoff s current law (KL We apply KL at every node in Fig. 3. The set of KL equations are v S = v REF v F B Two LHP zeros are formed, one due to the outer loop and one due to the inner loop, given by ω Z = (6 ω Z2 /R 2 2 (7 From (5 and (7, we see that LHP zero ω Z2 effectively cancels the second pole ω P 2. The third pole ω P 3 is a non-dominant pole situated much after ω GBW. Higher order poles and righthalf plane (RHP zero due to gd,p ASS are neglected. The equations of poles and zeros of the LDO are given in Table II. The gain-bandwidth product is approximated as v = (g m v S v G v Y Z v 2 = ( g m2 v i 2 i gd Z 2 LDO - RNMB I m = ( g mp v 2 i i gd Z out v F B = β β = R F 2 v = R F R F 2 i i 2 v Y = G ( R Z = R Z 2 = R 2 s gs = Z out = D. Pole-Zero Equations s = s R R 2 s gsr 2 s = s i = s ( v i 2 = (v2 v Y = s 2(v 2 v Y R 2 s s 2 R 2 2 i gd = s gd,p ASS ( v 2 Solve the equations in ( so as to eliminate v, v 2,, v, v Y, i, i 2 and i gd to obtain the transfer function A LDO RNMB (s = v F B (s/v S (s using symbolic manipulation software. Assuming that (, 2 and, and the poles are widely separated, small-signal analysis yields the transfer function given by A LDO RNMB (s ( ( sr 2 2 s A D ( ( (2 s ω P ( sr 2 2 s OUT R 2 g mp The open-loop dc loop gain of the regulator is given by A D = βg m R g m2 R 2 g mp, (3 where β is the feedback factor. The dominant pole ω P occurs at the output of the first stage and is given by ω P /R g m2 R 2 g mp (4 The second pole ω P 2 is due to the inner loop compensation network, given by ω P 2 /R 2 2 (5 Fig. 4. ω P3 ω Z2 ω P2 ω Z ω P ω Z3 R e Diagram illustrating pole-zero locations of Fig. 2 (not to scale. ω GBW g m (8 The Phase Margin of LDO can be expressed as P M = 80 o tan ( ωgbw ω P tan ( ωgbw ω Z tan ( ωgbw ω P 3 tan ( g 2 m g 2 mbu g mp R 2 g m As evident from Fig. 4, the LDO regulator s response is similar to that of a single-pole single-lhp-zero response with adequate phase margin ( 75 o, depending on the location ω Z. TABLE II POLE-ZERO EQUATIONS OF LDO WITH RNMB (FIG. 2 Parameter A D ω P ω Z ω P 2, ω Z2 ω P 3 Equation βg m R g m2 R 2 g mp R g m2 R 2 g mp R 2 2 R 2 g mp ω Z3 g mp gd,p ASS IV. SOURE DEGENERATED DIFFERENTIAL AMPLIFIER The schematic of a bipolar differential amplifier with source degeneration is shown in Fig. 5(a. The circuit contains degeneration resistor R DEG and degeneration capacitor DEG. The source degenerated amplifier acts as a band-limited high pass filter whose high-pass corner frequency is defined by / (2πR DEG DEG. (9

Q 3 Q M4 Q 3 Q M4 V IN V OUT Q Q 2 V IN- V IN Q Q 2 V IN- V OUT R i v S g (vs va m R DEG R DEG 2 R DEG 2 v A DEG 2 DEG 2 DEG R DEG 2 2DEG (a (b (c Fig. 5. (a Schematic of the differential amplifier with source degeneration, (b alternate representation, and (c equivalent small-signal model. Resistor R DEG can be represented with two series resistors of value R DEG /2 and similarly, capacitor DEG can be represented with two series capacitors of value 2 DEG with the intermediate nodes as virtual ground as shown in Fig. 5(b. The equivalent small-signal model of the differential amplifier with source degeneration is shown in Fig. 5(c. The amplifier is modeled with a VS (v S v A in series with R DEG /2 and 2 DEG in parallel to ground as shown in Fig. 5(c. Let v S V IN V IN. Resistor and capacitor include any load attached to node V OUT. Applying KL at every node in Fig. 5(c, the set of equations are 0 = (v S va s v A 0 = (v S va 2s DEG v A (0 0.5R DEG Solving (0, we obtain the transfer function. The dc gain and the pole-zero equations of the source degenerated amplifier is given by A D = ( / 0.5R DEG ( ω Z = R DEG DEG (2 ω P = (3 ω P 2 = (4 2 DEG Observing the poles and zeros in (2-(4, depending on the values of R DEG and DEG, zero ω Z is often designed appear first, followed by the first pole ω P, and the second pole ω P 2, as shown in Fig. 6, to obtain the characteristic of a band-limited high pass filter (Fig. 7. ω Z I m Fig. 7. Magnitude and phase plot of source degenerated differential amplifier, shown as an example. output capacitor equivalent series resistance (ESR LHP zero, achieving phase-lead by inserting an LHP zero just before a non-dominant pole. This technique can also be implemented at an internal node of LDO by adding a resistor in series with capacitor to ground as shown in Fig. 8. V S Fig. 8. g m V R (a g m v S (a Phase-lead compensator, (b equivalent small-signal model. The small-signal model of the phase-lead compensator is shown in Fig. 8(b. Fig. 9. Magnitude and phase response of the amplifier with and without compensator, shown as an example. R (b v Fig. 6. ω P2 ω P R e Diagram illustrating pole-zero locations of Fig. 5 (not to scale. Applying KL to the small-signal model and solving the equation, we obtain the transfer function. KL equation is: V. PHASE-LEAD OMPENSATOR ompensation techniques are used to achieve adequate phase margin for improving stability. Most of the compensation techniques introduce an LHP zero to increase phase margin (phase-lead. Often LDOs are compensated with external 0 = g m v S v v s v (5 R /s Assuming the magnitude of and are comparable and R, the D gain and pole-zero equations of the

V LINE I M I M I V I P V SENSE D gmd V SENSE G I (s Q M Q M2 Q V Q V2 V REF G V V B R D Q S gms Q P gmp VOUT V BIAS V SENSE Q g mi R DEG Q 2 g mi V SENSE V BIAS2 V EA Q D gmd FF R FB R ESR I LOAD DEG Q M3 Q M4 V FB R FB2 Q M5 Q M6 EA Fig. 0. Transistor-level schematic of high power-supply rejection (PSR current-mode LDO Regulator, adapted from [2]. v IS Break urrent Loop Here R i,i G I(sv IS i EA v EA v B v S R i,v G V v S R EA EA g md v EA R B B g ms (v B -v ifb v ifb g mp v B vfb i f R FB R FB2 FF R ESR Break Voltage Loop Here Fig.. Small-signal model of high PSR current-mode LDO Regulator in Fig. 0. amplifier with phase-lead compensator are given by A D = g m R (6 ω P = R ( (7 ω P 2 = ( (8 ω Z = (9 where = /(. Observing the expression for the non-dominant pole ω P 2 and LHP zero ω Z in (8, we note that the zero appears approximately one octave before the non-dominant pole. This helps in achieving phase-lead as shown in Fig. 9. VI. HIGH PSR URRENT-MODE DUAL-LOOP LDO Fig. 0 shows the transistor-level schematic of the bipolar current-mode dual-loop LDO of [2] with high power-supply rejection (PSR performance. This LDO contains two feedback loops, a voltage loop and a current loop. The small-signal model and architecture of the LDO is shown in Figs. and 2. The voltage loop is formed by G V with input pair Q V Q V 2, common-emitter transistor Q D ( g md, pass transistor Q P ( g mp with sampling resistors R F B, R F B2. The current loop is formed by sense transistor Q S (g ms with degeneration resistor, high-pass filtering transconductance G I (s implemented with transistors Q Q 2, degeneration i S V REF G i (s G V i EA REA V EA EA g md RB V B B GmS g mp GmS R FB FF R FB2 g ms Fig. 2. Architecture of LDO with both voltage and current loops [2]. resistor R DEG and capacitor DEG, and is fed into the voltage loop. G I (s forms a high-pass filter characteristic with a band limited beyond the unity-gain-frequency of the voltage loop. The purpose of the amplifier Q D is to decouple Q P s large parasitic capacitance from node v EA. Fig. shows the smallsignal model and the places to break the current and voltage loops. Equations of small-signal parameters of the LDO of Fig. are given in Table III. We apply KL at every node in Fig.. The set of KL equations obtained are 0 = i EA G I (s G V v s i EA = v EA R EA v EA /s EA V FB V OUT R ESR 0 = g md v EA v B RB v B s B (20 0 = g ms (v B v if B g mp v B R ESR /s i f g ms (v B v if B = v if B i f = v F B R F B ( v F B s F F i f = v F B R F B2

TABLE III SMALL-SIGNAL PARAMETERS OF LDO IN FIG. G V g m of Q V,Q V 2 R i,v β P NP /G V ( g m of Q,Q 2 sr G I (s DEG DEG 0.5R g DEG m s 2 DEG R i,i β NP N /G I (s g md, r od g m, r o of Q D g ms, r os g m, r o of Q S G ms /g ms g mp, r op g m, r o of Q P g m4, r o4 g m, r o of Q M4 r o6 r o of Q ( M6 R EA 2 r o6g m4 r o4 βnp N /g md β NP N /g md R B (/g md R D r od β P NP /G ms β P NP /g mp B beqp beqs bcqd r op r os R L β F B R F B2 / (R F B R F B2 The pole-zero equations obtained are tabulated in Table IV. The zero ω Z from G I (s precedes the pole at output ω P, as shown in Fig. 3. At higher frequencies, (g m of Q /Q 2 increases and forms a pole ω P 2 with degeneration capacitor DEG. Pole ω P 3 is due to EA at node V EA and zero ω Z2 is due to and EA. Zero ω Z4 is due to R ESR and. Fig. 3. TABLE IV POLE-ZERO EQUATIONS OF LDO REGULATOR OF FIG. 0 Parameter Location Equation A D LDO β F B G V R EA g md R B g mp A D GI (s ω Z G I (s ω P V OUT 0.5R DEG R DEG DEG ω P 2 G I (s 2 DEG ω P 3 V EA EA (R EA ω Z2 V EA ω P 4, ω Z3 V F B ω Z4 V OUT ω Z4 ω Z3 ω P4 ω Z2 ω P3 ω P2 ω P EA F F (R F B R F B2 R ESR ω Z I m R e Diagram illustrating pole-zero locations of Fig. (not to scale. VII. ONLUSIONS In this tutorial, we have analyzed poles and zeros of two state-of-the-art LDO regulators. We outlined the steps for finding poles and zeros and applied those steps to a three-stage LDO and a high PSR LDO. A wide range of compensation techniques were illustrated including RNM using current buffers, phase-lead compensation and current-mode feedback with a high pass filtering characteristic. The derived analytic expressions for poles and zeros help in developing intuition of circuit behavior. REFERENES [] G. A. Rincon-Mora and P. E. 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