GM3(B) Pacino Intel Discrete & UMA Block Diagram

GM() Pacino Intel iscrete & UM lock iagram Screw Hole PG POWR /TT ONNTOR PG R-SOIMM PG, R-SOIMM PG, UIO/MP ST/H blank Page SYSTM RST IRUIT TT HRGR RUN POWR SW +.V_SUS/+V_SUS +V/+.V/+.V PG udio udio SPK conn Jacks x PG PG PG MHZ R II MHZ R II ST-O PG ST-H PG PG PG PG amera + -MI PG USR INTRF PG ST ST IH US. SPI FLSH Mbyts restline MI interface LP K IT PG Merom or Penryn ( Micro-FPG) PG ufg IH-M G X PS/ Touchpad PG PG, MHz FS PG,,,,, PG,,, IR TSOPTR PG Keyboard PG US. x PIx PIx US. PIx US. PIx US. US. iometric PG MHz PI FN & THRML SMS PG PIx GR x (M) PG, IH LOK SLGSPV (QFN-) PG TI M-M US conn x -in- ard Reader R POWR PI XPRSS GFX PG,,,, RGULTOR +.V_RUN/+.V_VP PG RGULTOR +.V_SUS/+.V_RUN /+.V_R_VTT SiI PG PG LVS VG HMI PG VR : PG PU VR / +.V_LW/+V_LW/ +V_LW VG ore Panel onnector PG RT ONN. HMI ONN. LN MM XPRSS-R MINI-R WLN MINI-R WWN MINI-R WPN ONN. PG PG PG PG PG ard Reader ONN. PG QUNT OMPUTR Schematic lock iagram PG PG RJ/Magnetics PG PG Size ocument Number Rev GM PG PG PG ate: Monday, March, Sheet of

Table of ontents PG SRIPTION Schematic lock iagram Front Page - Merom - restline - IHM - RII SO-IMM(P) lock Generator - VG HMI L connector RT ard reader PI interface ard reader & xpress card & card reader conn. SIO Flash/RT WWN/WPN WLN US port ST H & O TP/K/M/IR switch/l FN/Thermal - udio/onn. - ocking onn/q-switch System Reset ircuit - Screw hole & harger lank page.vp &.VRUN.VSUS &.VTT VG power circuit PU_ISL (phase) / ISL.V/V RUN Power Switch IN,att MI P SMUS LOK Power statu & lock diagram POWR PLN +PWR_SR +RT_LL +.V_LW +V_LW +V_LW +.V_LN +V_SUS +.V_SUS +.V_SUS +.V_R_VTT +V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_VP +V_OR +LV +V_MO +V_H +V_LW VOLTG V~+V +.V~+.V +.V +V +V +.V +V +.V +.V +.V +V +.V +.V +.V +.V +.V +.V~+.V +.V +V +V +V PG,,,,,,,,, Power States,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, SRIPTION MIN POWR RT POWR L/HRG POWR LRG POWR LN POWR SLP_S# TRL POWR SLP_S# TRL POWR SOIMM POWR SOIMM POWR SLP_S# TRL POWR SLP_S# TRL POWR SVO POWR LISTOG/IH POWR LISTOG/IH POWR PU OR POWR,., L power source GN PLN PG SRIPTION GN GN_.V GN_/ GN_ GN_R GN_ISL ONTROL SIGNL PU/LISTOG/IH POWR.V_RUN_ON L Power Module Power H Power LWON LWON +V_LW UX_ON SUS_ON.V_SUS_ON R_ON.V_R_VTT_ON RUN_ON.V_RUN_ON RUN_ON.V_RUN_ON.V_RUN_ON IMVP_VR_ON LV_TST_N & NV MO_N# H_N# LO output TIV IN S~S S~S S~S S~S S~S GN LL QUNT OMPUTR Index & Power Status Size ocument Number Rev GM ate: Monday, March, Sheet of

H_#[..] H_ST# H_RQ#[..] H_#[..] T H_ST# H_M# H_FRR# H_IGNN# H_STPLK# H_INTR H_NMI H_SMI# ITP_TI ITP_TMS ITP_TK ITP_TO ITP_TRST# H_RST# ITP_TK H_# H_# H_# H_# LK_PU_ITP# LK_PU_ITP H_#[..] H_RQ#[..] +.V_VP H_#[..] T ITP_TK ITP_TRST# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_RQ# H_RQ# H_RQ# H_RQ# H_RQ# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# Populate ITPFlex for bringup R /F R /F T T T T R R R R /F U J []# S# H L []# NR# L []# PRI# G K []# M []# FR# H N []# RY# F J []# SY# N []# P []# R# F P []# L []# IRR# P []# INIT# P []# R []# LOK# H M ST[]# RST# K RQ[]# RS[]# F H RQ[]# RS[]# F K RQ[]# RS[]# G J RQ[]# TRY# G L RQ[]# HIT# G Y []# HITM# U []# R []# PM[]# W []# PM[]# U []# PM[]# Y []# PM[]# U []# PRY# R []# PRQ# T []# TK T []# TI W []# TO W []# TMS Y []# TRST# U []# R# V []# W []# []# THRML []# []# PROHOT# V ST[]# THRM THRM M# FRR# IGNN# THRMTRIP# _N R JITP./F_N TI TMS TK TO TRST# RST# FO LKN LKP GN GN GN GN GN GN IH STPLK# LINT LINT SMI# M RSV[] N RSV[] T RSV[] V RSV[] RSV[] RSV[] RSV[] RSV[] RSV[] F RSV[] R GROUP R GROUP RSRV ONTROL XP/ITP SIGNLS MLX_- H LK LK[] LK[] H_IRR# H_RST#_L R ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_TK ITP_TI ITP_TO ITP_TMS ITP_TRST# ITP_RST# R H_PROHOT# H_THRM H_THRM H_THRM R R H_THRM P_N +.V_VP ITP_RST# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# H_S# H_NR# H_PRI# H_FR# H_RY# H_SY# H_R# +.V_VP H_INIT# H_LOK# H_RST# H_RS# H_RS# H_RS# H_TRY# H_HIT# H_HITM# ITP_RST# +.V_VP T H_THRM H_THRM +.V_VP LK_PU_LK LK_PU_LK# H_THRM Layout Note: Place couple.uf ecoupling caps with in." ITP connector. VTT VTT VTP R# # PM# PM# PM# PM# PM# PM# N N GN_ GN_ ITPFlex_N.U_N.U_N R +.V_VP H_PROHOT# +.V_SUS R +.V_VP +.V_VP Layout Note: Place R close to PU. H_RST# Layout Note: Place voltage divider within." of GTLRF pin Q R K/F +.V_LW H_THRM Q MMST--F Layout nopte: Place R,R, R, R, R and R close to PU R K/F NW--F_N T H_#[..] H_STN# H_STP# H_INV# H_#[..] H_# H_STN# H_STP# H_INV#, PU_MH_SL, PU_MH_SL, PU_MH_SL R.K_N Voltage Level shift PU_PROHOT# +.V_RUN R M.U H_#[..] T T H_#[..] T T R H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_THRMTRIP#, PU_TST PU_TST.U_N PU_TST _N PU_TST Place close to the PU_TST pin. Make sure PU_TST routing is reference to GN and away from other noisy signal. ITP disable guidelines H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# OMP OMP OMP OMP H_#[..] H_#[..] H_#[..] H_STN# H_STP# H_INV# H_#[..] H_STN# H_STP# H_INV# Note: H_PRTSTP need to daisy chain from IH to IMVP to PU. H_PRSTP#,, H_PSLP# H_PWR# H_PWRGOO H_PUSLP# H_PSI# T PU_TST T PU_TST For the purpose of testability, route these signals through a ground referenced Z = ohm trace that ends in a via that is near a GN via and is accessible through an oscilloscope connection. FS LK SL SL SL Signal Resistor Value onnect To Resistor Placement TI TMS TRST# TK K/F_N ohm +/- % ohm +/- % ohm +/- % ohm +/- % U []# F []# []# G []# F []# G []# []# []# K []# G []# J []# J []# H []# F []# K []# H []# J STN[]# H STP[]# H INV[]# N []# K []# P []# R []# L []# M []# L []# M []# P []# P []# P []# T []# R []# L []# T []# N []# L STN[]# M STP[]# N INV[]# V_PU_GTLRF PU_TST GTLRF PU_TST TST PU_TST TST PU_TST TST F PU_TST TST F PU_TST TST TST R R Q NW--F K/F_N SL[] SL[] SL[] VTT VTT GN GN Within." of the ITP Within." of the ITP Within." of the ITP Within." of the ITP TO Open VTT Within." of the ITP ITP_N R epop +VRUN lose to KM Pin T GRP T GRP T GRP T GRP MLX_- []# Y []# []# V []# V []# V []# T []# U []# U []# Y []# W []# Y []# W []# W []# []# []# STN[]# Y STP[]# INV[]# U []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# STN[]# STP[]# INV[]# OMP[] R MIS OMP[] U OMP[] OMP[] Y PRSTP# PSLP# PWR# PWRGOO SLP# PSI# H_# H_# H_# H_# H_# H_# H_# H_# F H_# H_# H_# H_# H_# H_# F H_# H_# F T T T OMP OMP OMP OMP H_# H_# H_# H_# R./F omp, connect with Zo=.ohm,omp, connect with Zo=ohm, make those traces length shorter than.".trace should be at least mils away from any other toggling signal. QUNT OMPUTR Merom Processor (HOST US) R./F T R./F R./F Size ocument Number Rev GM ate: Monday, March, Sheet of

+V_OR U +V_OR U +V_OR +V_OR +V_OR inside cavity, north side, primary layer. +V_OR +.V_VP ll use U V(+-%,XS,)Pb-Free. inside cavity, north side, secondary layer. U U inside cavity, south side, secondary layer. U U U U U U U U U U U inside cavity, south side, primary layer..u U U.U U U U U.U U U U.U U U.U U U U U U U.U Layout out: Place these inside socket cavity on North side secondary. +V_OR +PWR_SR + U +V_OR U V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] F V[] V[] F V[] V[] F V[] V[] F V[] V[] F V[] V[] F V[] V[] F +.V_VP V[] V[] F V[] V[] VP[] G V[] VP[] V V[] VP[] J + V[] VP[] K U V[] VP[] M V[] VP[] J V[] VP[] K F V[] VP[] M F V[] VP[] N F V[] VP[] N F V[] VP[] R F V[] VP[] R F V[] VP[] T F V[] VP[] T F V[] VP[] V F V[] VP[] W V[] V[] V[] V[] V[] V[] V[] VI[] VI V[] VI[] F VI V[] VI[] VI V[] VI[] F VI V[] VI[] VI V[] VI[] F VI V[] VI[] VI V[] V[] +VSNS V[] VSNS F +VSNS V[] V[] +VSSSNS V[] VSSSNS +VSSSNS MLX_- + U + U_N Layout Note: Need to add uf cap on PWR_SR for cap singing. Place on PWR_SR near +V_OR.. + U_N.U +VSNS +VSSSNS +.V_RUN Layout Note: Place near PIN. +V_OR U R /F R /F Route VSNS and VSSSNS traces at.ohms and length matched to within mil. Place PU and P within inch of PU. U VSS[] VSS[] P VSS[] VSS[] P VSS[] VSS[] P VSS[] VSS[] R VSS[] VSS[] R VSS[] VSS[] R VSS[] VSS[] R F VSS[] VSS[] T VSS[] VSS[] T VSS[] VSS[] T VSS[] VSS[] T VSS[] VSS[] U VSS[] VSS[] U VSS[] VSS[] U VSS[] VSS[] U VSS[] VSS[] V VSS[] VSS[] V VSS[] VSS[] V VSS[] VSS[] V VSS[] VSS[] W VSS[] VSS[] W VSS[] VSS[] W VSS[] VSS[] W VSS[] VSS[] Y VSS[] VSS[] Y VSS[] VSS[] Y VSS[] VSS[] Y VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] G VSS[] VSS[] G VSS[] VSS[] G VSS[] VSS[] G VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] J VSS[] VSS[] J VSS[] VSS[] J VSS[] VSS[] J VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] L VSS[] VSS[] L VSS[] VSS[] L VSS[] VSS[] L VSS[] VSS[] M VSS[] VSS[] M VSS[] VSS[] F M VSS[] VSS[] F M VSS[] VSS[] F N VSS[] VSS[] F N VSS[] VSS[] F N VSS[] VSS[] F N VSS[] VSS[] F P VSS[] VSS[] VSS[] F MLX_-. QUNT OMPUTR Merom Processor (POWR) Size ocument Number Rev GM ate: Monday, March, Sheet of

T T H_# T H_# +.V_VP +.V_VP R /F R /F R./F R./F H_SWING R./F H_SOMP H_SOMP# H_ROMP H_# H_#[..] H_#.U/V Layout Note: H_ROMP trace should be -mil wide with -mil spacing. +.V_VP R K/F R K/F H_RST# H_PUSLP# H_#[..].U/V H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_SWING H_ROMP H_SOMP H_SOMP# R H_RF U H_#_ G H_#_ G H_#_ M H_#_ H H_#_ H H_#_ G H_#_ F H_#_ N H_#_ H H_#_ M H_#_ N H_#_ N H_#_ H H_#_ P H_#_ K H_#_ M H_#_ W H_#_ Y H_#_ V H_#_ M H_#_ J H_#_ N H_#_ N H_#_ W H_#_ W H_#_ N H_#_ Y H_#_ Y H_#_ P H_#_ W H_#_ N H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ Y H_#_ H_#_ H_#_ H_#_ G H_#_ J H_#_ H H_#_ J H_#_ H_#_ H_#_ H H_#_ J H_#_ H H_#_ J H_#_ H_#_ J H_#_ J H_#_ H_#_ J H_#_ H H_#_ H H_#_ H_SWING H_ROMP W H_SOMP W H_SOMP# H_PURST# H_PUSLP# H_VRF H_VRF RSTLIN_p_U HOST H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_S# H_ST#_ H_ST#_ H_NR# H_PRI# H_RQ# H_FR# H_SY# HPLL_LK HPLL_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_INV#_ H_INV#_ H_INV#_ H_INV#_ H_STN#_ H_STN#_ H_STN#_ H_STN#_ H_STP#_ H_STP#_ H_STP#_ H_STP#_ H_RQ#_ H_RQ#_ H_RQ#_ H_RQ#_ H_RQ#_ H_RS#_ H_RS#_ H_RS#_ J M F L G K L J K P R H L M N J N G H G F M M H K G K L M K H L K J M H H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#[..] H_#[..] H_S# H_ST# H_ST# H_NR# H_PRI# H_R# H_FR# H_SY# LK_MH_LK LK_MH_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# T T H_INV# H_INV# H_INV# H_INV# H_RQ# H_RQ# H_RQ# H_RQ# H_RQ# H_RS# H_RS# H_RS# T T H_STN# H_STN# H_STN# H_STN# H_STP# H_STP# H_STP# H_STP# U QI PN Layout Note: Place the. uf decoupling capacitor within mils from GMH pins. IS JSLUT UM JSLTT restline (HOST) QUNT OMPUTR Size ocument Number Rev GM ate: Monday, March, Sheet of

SM_ROMP_VOH.U SM_ROMP_VOL.U,, +.V_RUN +.V_VP R M R M +.V_SUS Santa Rosa Platform MOW WW For Gb RM support, change Pin-J to R M, change Pin- to R M. R R.U.U K K R R K/F R.K R K/F UM_L_- UM_L_- UM_L_- UM_L_- UM_L_+ UM_L_- UM_L_+ PM_XTTS# PM_XTTS# THRMTRIP_MH# PM_MUSY#,, H_PRSTP# PM_XTTS# PM_XTTS#, IH_PWRG, R R R R PRSLPVR _UM _UM _UM _UM S_N_PI_RST# UM_L_-_R UM_L_+_R UM_L_-_R UM_L_+_R Layout Note: Location of all MH_FG strap resistors needs to be close to minmize stub., PU_MH_SL, PU_MH_SL, PU_MH_SL T T R.K_N T T T R.K_N T T T T T T R.K_N +.V_RUN T T R.K_N R.K_N T T T T T T T T T T T T T T T T PM_XTTS# PM_XTTS# FG FG FG FG FG FG FG FG FG FG FG FG FG FG FG FG FG FG PLTRST#_R THRMTRIP_MH# R R _N P P R N R R M N J R M L M H J K F H K J F G J H W K P N N F N G J R L J K M M L N L G L L J W V N G J K K L L L L K J K U RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ PM_M_USY# PM_PRSTP# PM_XT_TS#_ PM_XT_TS#_ PWROK RSTIN# THRMTRIP# PRSLPVR N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ RSTLIN_p_U R MUXING RSV LK MI FG GRPHIS VI PM M N MIS SM_K_ SM_K_ SM_K_ SM_K_ SM_K#_ SM_K#_ SM_K#_ SM_K#_ SM_K_ SM_K_ SM_K_ SM_K_ SM_S#_ SM_S#_ SM_S#_ SM_S#_ SM_OT_ SM_OT_ SM_OT_ SM_OT_ SM_ROMP SM_ROMP# SM_ROMP_VOH SM_ROMP_VOL SM_VRF_ SM_VRF_ PLL_RF_LK PLL_RF_LK# PLL_RF_SSLK PLL_RF_SSLK# PG_LK PG_LK# MI_RXN_ MI_RXN_ MI_RXN_ MI_RXN_ MI_RXP_ MI_RXP_ MI_RXP_ MI_RXP_ MI_TXN_ MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_ MI_TXP_ MI_TXP_ MI_TXP_ GFX_VI_ GFX_VI_ GFX_VI_ GFX_VI_ GFX_VR_N L_LK L_T L_PWROK L_RST# L_VRF SVO_TRL_LK SVO_TRL_T LK_RQ# IH_SYN# TST_ TST_ V V W W W Y G G K G H J J L K K L R W H H K K N J N N M J N N J J M M J J M M M K T N M H K G G R SMROMPP SMROMPN SM_ROMP_VOH SM_ROMP_VOL MH_LVRF M_LK_R M_LK_R M_LK_R M_LK_R M_LK_R# M_LK_R# M_LK_R# M_LK_R# SVO_TRLLK_L R SVO_TRLT_L R R K R_K_IMM, R_K_IMM, R_K_IMM, R_K_IMM, R_S_IMM#, R_S_IMM#, R_S_IMM#, R_S_IMM#, M_OT, M_OT, M_OT, M_OT, +V_R_MH_RF MH_RFLK_L MH_RFLK#_L R RF_SSLK_L R RF_SSLK#_L R R LK_MH_GPLL LK_MH_GPLL# MI_MRX_ITX_N MI_MRX_ITX_N MI_MRX_ITX_N MI_MRX_ITX_N MI_MRX_ITX_P MI_MRX_ITX_P MI_MRX_ITX_P MI_MRX_ITX_P MI_MTX_IRX_N MI_MTX_IRX_N MI_MTX_IRX_N MI_MTX_IRX_N MI_MTX_IRX_P MI_MTX_IRX_P MI_MTX_IRX_P MI_MTX_IRX_P T T T T T, L_LK L_T IH_L_PWROK, IH_L_RST# LK_GPLLRQ# MH_IH_SYN# R +.V_RUN POP FOR UM H_THRMTRIP# _IS _IS R R _UM _UM _UM _UM R R R POP FOR UM.K_UM.K_UM R R SMROMPP SMROMPN R _N _U _U _U L_LK_R L_T_R +.V_SUS LTL_LK LTL_T UM_VG_LU UM_RT_LK_ UM_RT_T_ UM_VGHSYN R /F R /F MH_RFLK MH_RFLK# RF_SSLK RF_SSLK# UM_VG_GRN UM_VG_R UM_VGVSYN THRMTRIP_MH# UM_VG_LU_R UM_VG_GRN_R UM_VG_R_R UM US RSISTOR /F PN:SF IS US OHM PN:SJ Layout Note: Place ohm termination resistors close to GMH. UM_L_LK UM_L_T UM_NV UM_L_LK-_ UM_L_LK+_ UM_L_LK-_ UM_L_LK+_ UM_I_PWM UM_PNL_KN UM_L_+ UM_L_+ UM_L_+ _UM UM_L_LK- _UM UM_L_LK+ _UM UM_L_LK- _UM UM_L_LK+ UM_L_- UM_L_- UM_L_- UM_L_+ UM_L_+ UM_L_+ Non-iMT MH_LVRF.U +.V_RUN R R R R K/F R /F _UM POP FOR UM R R R R R R R R R R UM_VG_LU_R UM_VG_GRN_R UM_VG_R_R _UM UM_I_PWM_RJ _UM PNL_KN_R H LTL_LK LTL_T _UM L_LK_R _UM L_T_R _UM NV_R K _UM UM_L_-_R _UM UM_L_-_R _UM UM_L_-_R _UM UM_L_+_R _UM UM_L_+_R _UM UM_L_+_R _UM UM_L_-_R _UM UM_L_-_R _UM UM_L_-_R _UM UM_L_+_R _UM UM_L_+_R _UM UM_L_+_R R _UM UM_RT_LK R R _UM UM_RT_T R R /F_UMUM_VGHSYN_R R.K_UM RT_TVO_IRF R /F_UMUM_VGVSYN_R POP FOR UM R R R R R R R R R R R _UM _UM R R R T R R R R R R R R R R _IS _IS _IS _IS _IS _IS _IS _IS _IS _IS _IS.K/F_UM _UM R R R L_IG M P R, R and R IS: -->SJ UM: -->SF L_LK_R L_T_R UM_RT_LK R UM_RT_T R UM_VGHSYN_R RT_TVO_IRF UM_VGVSYN_R MH_RFLK_L MH_RFLK#_L RF_SSLK_L RF_SSLK#_L POP FOR IS _U _U _U L L N N G F G F G G K F J L H G K J F K G F U L_KLT_TRL L_KLT_N L_TRL_LK L_TRL_T L LK L T L_V_N LVS_IG LVS_VG LVS_VRFH LVS_VRFL LVS_LK# LVS_LK LVS_LK# LVS_LK LVS_T#_ LVS_T#_ LVS_T#_ LVS_T_ LVS_T_ LVS_T_ LVS_T#_ LVS_T#_ LVS_T#_ LVS_T_ LVS_T_ LVS_T_ TV_ TV_ TV_ TV_RTN TV_RTN TV_RTN TV_ONSL_ TV_ONSL_ RT_LU RT_LU# RT_GRN RT_GRN# RT_R RT_R# RT LK RT T RT_HSYN RT_TVO_IRF RT_VSYN RSTLIN_p_U LVS TV VG PI-XPRSS GRPHIS PG_OMPI PG_OMPO PG_RX#_ PG_RX#_ PG_RX#_ PG_RX#_ PG_RX#_ PG_RX#_ PG_RX#_ PG_RX#_ PG_RX#_ PG_RX#_ PG_RX#_ PG_RX#_ PG_RX#_ PG_RX#_ PG_RX#_ PG_RX#_ PG_RX_ PG_RX_ PG_RX_ PG_RX_ PG_RX_ PG_RX_ PG_RX_ PG_RX_ PG_RX_ PG_RX_ PG_RX_ PG_RX_ PG_RX_ PG_RX_ PG_RX_ PG_RX_ PG_TX#_ PG_TX#_ PG_TX#_ PG_TX#_ PG_TX#_ PG_TX#_ PG_TX#_ PG_TX#_ PG_TX#_ PG_TX#_ PG_TX#_ PG_TX#_ PG_TX#_ PG_TX#_ PG_TX#_ PG_TX#_ PG_TX_ PG_TX_ PG_TX_ PG_TX_ PG_TX_ PG_TX_ PG_TX_ PG_TX_ PG_TX_ PG_TX_ PG_TX_ PG_TX_ PG_TX_ PG_TX_ PG_TX_ PG_TX_ N M J L N T T U Y Y W G H G G J L M U T T W W Y H G H G N U U N R T Y W W H H M T T N R U W Y Y G H +VG_PI_R PI_MRX_GTX_N PI_MRX_GTX_N_L R PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_P PI_MRX_GTX_P_L R PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX P PI_MTX_GRX P PI_MTX_GRX P PI_MTX_GRX P PI_MTX_GRX P PI_MTX_GRX P PI_MTX_GRX P PI_MTX_GRX P PI_MTX_GRX P PI_MTX_GRX P PI_MTX_GRX P PI_MTX_GRX P PI_MTX_GRX P PI_MTX_GRX P PI_MTX_GRX P PI_MTX_GRX P SVO_TRLLK_L SVO_TRLT_L PI_MRX_GTX_N_L PI_MRX_GTX_P_L PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX N PI_MTX_GRX P PI_MTX_GRX P PI_MTX_GRX P PI_MTX_GRX P R./F +V_PG PI_MRX_GTX_N _IS PI_MRX_GTX_P _IS R R R R POP FOR IS _UM _UM _UM _UM.U_UM.U_UM.U_UM.U_UM.U_UM.U_UM.U_UM.U_UM PI_MTX_GRX_N[..] PI_MTX_GRX_P[..].U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS locked ap. N POP FOR UM PI_MRX_GTX_N[..] PI_MRX_GTX_P[..] PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P SVO_TRLLK SVO_TRLT SVO_INT- SVO_INT+ SVO_R- SVO_GRN- SVO_LU- SVO_LK- SVO_R+ SVO_GRN+ SVO_LU+ SVO_LK+,,,,, PLTRST# R PLTRST#_R R FG FG FG FG FG Low=MIx MI X Select High=MIx(efault) PI xpress Graphic Lane FS ynamic OT MI Lane Reversal SVO/PI oncurrent Operation Low= Reveise Lane High=Normal operation Low=ynamic OT isable High=ynamic OT nable(default). Low=Normal(default). High=Lane Reversed Low=Only SVO or PIx is operational (defaults) High=SVO and PIx are operating simultaneously via PG port Low=No SVO evice Present (default) SVO_RTL_T SVO Present. High=SVO evice Present QUNT OMPUTR restline (VG,MI) Size ocument Number Rev GM Monday, March, ate: Sheet of

R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R M R M R M R M R M R M R M R M R QS R QS R QS R QS R QS R QS R QS R QS R M R M R M R M R M R M R M R M R S R W# R RS# R S# R S R S R M R M R M R M R M R M R QS# R QS# R QS# R QS# R QS# R QS# R QS# R QS# R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R S R S R S R S# R W# R RS# R M R QS# R QS# R QS# R QS# R QS# R QS# R QS# R QS# R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R QS R QS R QS R QS R QS R QS R QS R QS R M R M R M R M R M R M R S# R RS# R W# R M R M R QS R QS# R R R R [..] R S, R W#, R RS#, R S, R S, R S#, R QS#[..] R M[..], R QS[..] R M[..] R [..] R S#, R S, R S, R S, R QS#[..] R M[..], R QS[..] R M[..] R W#, R RS#, Size ocument Number Rev ate: Sheet of QUNT OMPUTR GM restline (R) Monday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTR GM restline (R) Monday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTR GM restline (R) Monday, March, T T T T T T T T T T R SYSTM MMORY U RSTLIN_p_U R SYSTM MMORY U RSTLIN_p_U S_Q_ R S_Q_ W S_Q_ G S_Q_ J S_Q_ S_Q_ G S_Q_ H S_Q_ S_Q_ W S_Q_ S_Q_ G S_Q_ S_Q_ S_Q_ F S_Q_ H S_Q_ G S_Q_ F S_Q_ R S_Q_ W S_Q_ T S_Q_ W S_Q_ W S_Q_ Y S_Q_ Y S_Q_ V S_Q_ T S_Q_ V S_Q_ T S_Q_ W S_Q_ V S_Q_ U S_Q_ T S_Q_ S_Q_ S_Q_ R S_Q_ S_Q_ S_Q_ S_Q_ Y S_Q_ G S_Q_ W S_Q_ S_Q_ S_Q_ S_Q_ Y S_Q_ R S_Q_ T S_Q_ T S_Q_ Y S_Q_ S_Q_ R S_Q_ R S_Q_ R S_Q_ N S_Q_ M S_Q_ N S_Q_ T S_Q_ T S_Q_ N S_Q_ M S_Q_ N S_Q_ W S_Q_ S_Q_ F S_S_ S_S_ K S_S_ F S_S# L S_M_ T S_M_ S_M_ S_M_ W S_M_ W S_M_ G S_M_ Y S_QS_ T S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ H S_QS_ S_QS_ P S_M_ N S_QS#_ T S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ H S_QS#_ S_QS#_ P S_M_ J S_M_ S_M_ S_M_ S_M_ G S_M_ J S_M_ K S_M_ H S_M_ L S_M_ K S_M_ J S_M_ J S_M_ L S_M_ S_RS# S_RVN# Y S_W# T T T T T T R SYSTM MMORY U RSTLIN_p_U R SYSTM MMORY U RSTLIN_p_U S_Q_ P S_Q_ R S_Q_ S_Q_ S_Q_ S_Q_ Y S_Q_ F S_Q_ F S_Q_ J S_Q_ J S_Q_ J S_Q_ L S_Q_ W S_Q_ K S_Q_ K S_Q_ K S_Q_ K S_Q_ J S_Q_ L S_Q_ J S_Q_ J S_Q_ K S_Q_ J S_Q_ W S_Q_ L S_Q_ K S_Q_ K S_Q_ S_Q_ K S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ G S_Q_ N S_Q_ J S_Q_ L S_Q_ K S_Q_ L S_Q_ K S_Q_ K S_Q_ J S_Q_ J S_Q_ F S_Q_ H S_Q_ N S_Q_ G S_Q_ S_Q_ K S_Q_ S_Q_ S_Q_ J S_Q_ S_Q_ S_Q_ R S_Q_ T S_Q_ V S_Q_ Y S_Q_ Y S_Q_ U S_Q_ T S_Q_ V S_Q_ S_Q_ S_S_ Y S_S_ G S_S_ G S_S# S_M_ R S_M_ S_M_ K S_M_ L S_M_ H S_M_ J S_M_ F S_M_ W S_QS_ T S_QS_ S_QS_ K S_QS_ K S_QS_ J S_QS_ L S_QS_ S_QS_ V S_QS#_ U S_QS#_ S_QS#_ L S_QS#_ K S_QS#_ K S_QS#_ K S_QS#_ F S_QS#_ V S_M_ S_M_ G S_M_ G S_M_ S_M_ S_M_ G S_M_ G S_M_ W S_M_ F S_M_ S_M_ S_M_ S_M_ Y S_M_ S_RS# V S_RVN# Y S_W# T T T T T T T T T T

+.V_VP UG T V_ T V_ H V_ V_ V_ K V_ J V_ J V_ H V_ H V_ H V_ F V_ R V_ +.V_SUS U V_SM_ U V_SM_ U V_SM_ V V_SM_ W V_SM_ W V_SM_ Y V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ F V_SM_ F V_SM_ G V_SM_ G V_SM_ G V_SM_ H V_SM_ H V_SM_ H V_SM_ J V_SM_ J V_SM_ J V_SM_ K V_SM_ K V_SM_ K V_SM_ K V_SM_ L V_SM_ U V_SM_ R V_XG_ T V_XG_ W V_XG_ W V_XG_ Y V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ +.V_VP V_XG_ V_XG_ F V_XG_ F V_XG_ V_XG_ H V_XG_ H R V_XG_ H V_XG UM H V_XG_ H V_XG_ V_XG_ J V_XG_ N V_XG_ () V OR POWR V SM V GFX R IS RSTLIN_p_U V GFX NTF V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V SM LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF T T T T T T T U U U U U U U U V V V V V V V Y Y Y Y Y Y Y Y Y Y Y F F H H H H J J J K K L L L L L L M M M M M M P P P P P P P P R R R R R V V V Y W W T VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF UM POP POWR JUMP N & UM POP POWR JUMP N LL P.U/V +.V_VP Layout Note: mils from edge. () R UM R IS R IS ().U/V + U_UM. + U Layout Note: mils from edge. R UM + U_UM. U/V +.V_VP Non-iMT +.V_RUN Layout Note: Inside GMH cavity for V_XM..U_UM.U/V.U_UM.U/V.U/V +V_GMH_L Layout Note: Inside GMH cavity. + U_N..U_UM U_UM U/V R.U/V.U/V U/V U_UM..U/V +.V_VP +.V_VP U_UM Layout Note: Inside GMH cavity..u/v Layout Note: Place close to GMH edge. + U_N. U/V.U/V SMKL--F.U/V.U/V.U/V +.V_SUS.U/V Layout Note: Place where LVS and R taps. UF V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ F V_NTF_ F V_NTF_ H V_NTF_ H V_NTF_ H V_NTF_ H V_NTF_ J V_NTF_ J V_NTF_ K V_NTF_ K V_NTF_ K V_NTF_ K V_NTF_ V_NTF_ J V_NTF_ M V_NTF_ L V_NTF_ L V_NTF_ V_NTF_ V_NTF_ V_NTF_ P V_NTF_ P V_NTF_ R V_NTF_ R V_NTF_ Y V_NTF_ Y V_NTF_ Y V_NTF_ Y V_NTF_ Y V_NTF_ T V_NTF_ T V_NTF_ T V_NTF_ U V_NTF_ U V_NTF_ U V_NTF_ U V_NTF_ U V_NTF_ U V_NTF_ V V_NTF_ V V_NTF_ V V_NTF_ V V_NTF_ RSTLIN_p_U + U/.V V NTF L V_XM_NTF_ L V_XM_NTF_ L V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ P V_XM_NTF_ P V_XM_NTF_ P V_XM_NTF_ P V_XM_NTF_ L V_XM_NTF_ L V_XM_NTF_ L V_XM_NTF_ R V_XM_NTF_ R V_XM_NTF_ R V_XM_NTF_ POWR V XM NTF U/V Layout Note: Place on the edge. QUNT OMPUTR restline (V,NTF) VSS NTF VSS S V XM VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_S VSS_S VSS_S VSS_S VSS_S VSS_S V_XM_ V_XM_ V_XM_ V_XM_ V_XM_ V_XM_ V_XM_ V_SM U/V T T U U V V F F K M M P P R R R L L T T K K K J J +.V_VP Size ocument Number Rev GM ate: Monday, March, Sheet of

F_ohm+-%_mHz_m_.ohm +.V_RUN R./F +V_MPLL_L +.V_RUN +V_RT LMPGSN_UM UM POP LL SIS Non-iMT m Mx. F_ohm+-%_mHz +.V_RUN _m_.ohm U V R R R R R R R R R R R R L L +V_HPLL LMGSN U/V.U/V L LMGSN +V_MPLL V V _IS _IS _IS _IS _IS _IS _IS _IS _IS _IS _IS _IS +V_LVS_R +VQ_TV_RR +V_RT_R +V_TV_RR +V_TV_RR +V_TV_RR +V_TX_LVS_L +V_PLL +V_PLL +V G +V_RT_ +VSYN IS POP LL L LMPGSN F_ohm+-%_MHz.ohm.U V +V_PG_PLL R /F U. +.V_RUN +.V_RUN R.U_UM Non-iMT m Mx. +V_RT UM nf/p_n uh+-%_m L +V_PLL uh/m_um +.U_UM U/SR_UM.V L +V_PLL uh/m_um.aps should be placed mils with in its pins..u V + U V +.V_SUS +V_RT_R +.V_RUN UM POP LL +.U_UM U/SR_UM.V.U. U () +.V_RUN Non-iMT +V_RT_.U_UM V +.V_RUN +V_LVS UM POP LL _UM R U R _UM.U V +VSYN +V G +V_PLL +V_PLL +V_HPLL +V_MPLL +V_TX_LVS_L +V_PG_PLL U +.V_RUN +V_TV_RR +V_TV_RR +V_TV_RR +V_RT_R +V_TV_RR +VQ_TV_RR UM POP & RSISTOR R _UM.U V +V_PG_PLL.U V _UM R +V_LVS_R J H L M K K U W V U U U T T T T T R R M L N N U J H UH VSYN V_RT V_RT V G VSS G V_PLL V_PLL V_HPLL V_MPLL V_LVS VSS_LVS V_PG_G VSS_PG_G V_PG_PLL V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_NTF_ V_SM_NTF_ V_SM_K_ V_SM_K_ V_TV V_TV V_TV V_TV V_TV V_TV V_RT V_TV V_Q V_HPLL V_PG_PLL V_LVS_ V_LVS_ +VTTLF +VTTLF +VTTLF RT PLL K SM PG LVS POWR TV TV/RT LVS X XF SM K HV MI PG VTT VTTLF VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_NTF V_XF_ V_XF_ V_XF_ V_MI V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_TX_LVS V_HV_ V_HV_ V_PG_ V_PG_ V_PG_ V_PG_ V_PG_ V_RXR_MI_ V_RXR_MI_ VTTLF VTTLF VTTLF U U U U U U U U U U T T T T T T T T T R R R F H RSTLIN_p_U T U U T T T R J K K J J W W V V H H +V_SM_K +V_RXR_MI +VTTLF +VTTLF +VTTLF +.V_VP Place on the edge. +.V_RUN.U/.V.U/.V +.V_VP Place on the edge. +V_X_L L Reserved L pad for inductor. U/V U/V Place caps close +.V_RUN to V_X. +V_TX_LVS_L.U/V V V.U/.V.U..U V + U/V + U/V +V_PG. +.V_RUN _UM R U/.V U/.V + U/V NoniMT +.V_RUN uh+-%_. V_HV SMKL--F_N U/V +.V_VP +.V_RUN +.V_RUN +V_HV_L R _N U/.V Place caps close to,, uh+-%_m +V_TX_LVS L +V_TX_LVS_R uh/m_um + U_UM P_UM. L uh+-%_. +.V_VP nh/. L nh/. Place ohm close to +.V_SUS +.V_VP R _UM UM POP LL +.V_SUS layout note: close to pin +V_TX_LVS_L P_UM U_N U_UM. +.V_RUN Non-iMT U U.U/V U.U/V.U V.U/V L uh/m +V_SM_K U/V.U/V uh+-%_m R /F/ +V_SM_K_L U/.V +.V_SUS layout shound close to & F_ohm+-%_mHz_m_.ohm UM POP LL SIS,,,, R & +.V_RUN L +V_TV +V_TV_RR LMPGSN_UM R UM nf &.uf for V_TV:_R should U_UM.U_UM nf/p_n be placed with in mils from restline.. +.V_RUN U_IS..U_IS V _IS R +V_TV_RR.U_IS IS POP LL +V G +V_TVG R _UM R./F_UM nf/p_n.u_um +.V_RUN +.V_RUN +V_TV_L R _N SMKL--F_N TV Voltage Follower ircuit - mv..u_um R.U_UM +V_TV_RR R _UM nf/p_n +V_TV_RR _UM nf/p_n +.V_RUN UM POP LL SIS & R.U_UM L +VQ_TV LMPGSN_UM R F_ohm+-%_ <Size>.U/V/_UM mhz_m_.ohm <Voltage> +V_RT_R UM +VQ_TV_RR nf/p_n UM nf/p_n QUNT OMPUTR restline (POWR) Size ocument Number Rev GM Monday, March, ate: Sheet of

Size ocument Number Rev ate: Sheet of QUNT OMPUTR GM restline (VSS) Monday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTR GM restline (VSS) Monday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTR GM restline (VSS) Monday, March, VSS UI RSTLIN_p_U VSS UI RSTLIN_p_U VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ F VSS_ F VSS_ F VSS_ F VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ K VSS_ K VSS_ K VSS_ K VSS_ L VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ P VSS_ P VSS_ P VSS_ R VSS_ R VSS_ R VSS_ R VSS_ R VSS_ R VSS_ T VSS_ T VSS_ T VSS_ T VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ F VSS_ F VSS_ F VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ K VSS_ K VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ V VSS_ V VSS_ W VSS_ W VSS_ K VSS_ K VSS_ K VSS_ L VSS_ L VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ K VSS_ K VSS_ L VSS_ L VSS_ L VSS_ L VSS_ VSS_ VSS_ VSS UJ RSTLIN_p_U VSS UJ RSTLIN_p_U VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ H VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ K VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ P VSS_ P VSS_ P VSS_ P VSS_ P VSS_ R VSS_ T VSS_ T VSS_ T VSS_ U VSS_ U VSS_ U VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ W VSS_ Y VSS_ Y VSS_ Y VSS_ V VSS_ V VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ P VSS_ T VSS_ T VSS_ T VSS_ R VSS_ VSS_ VSS_ VSS_ F VSS_ F VSS_ T VSS_ V VSS_ H

.KHZ R M +RT_LL +RT_LL IH_RTX IH_RTX IH_INTVRMN IH_LN_SLP W R R K/F R K/F P/V.KHZ P/V R _N R _N IH_Z_HMI_ITLK IH_Z_O_ITLK IH_Z_HMI_SYN IH_Z_O_SYN IH_Z_HMI_RST#, IH_Z_O_RST# IH_Z_HMI_SOUT IH_Z_O_SOUT +RT_LL ST_TX-_ ST_TX+_ ST_TX-_ ST_TX+_ ST_TX-_ ST_TX+_ IH_RTRST# IH_INTRUR# Z_IT_LK Z_SYN Z_RST# Z_SOUT Place all series terms close to IH except for SIN input lines,which should be close to source.placement of R, R, R & R should equal distance to the T split trace point as R, R, R & R respective. asically,keep the same distance from T for all series termination resistors. P/V_UM P P P P P P R _UM R R _UM R R _UM R istance between the IH- M and cap on the "P" signal should be identical distance between the IH- M and cap on the "N" signal for same pair. R M P/V_N R K U/V R _UM R Master H ST O Second H Reserved for Intel Nineveh T design. T T T T T +.V_SUS +.V_PI_IH IH_Z_O_SIN IH_Z_HMI_SIN T T +.V_SUS ST_T# ST_TX- ST_TX+ ST_TX- ST_TX+ ST_TX- ST_TX+ ST_RX- ST_RX+ ST_RX- ST_RX+ ST_RX- ST_RX+ LK_PI_ST# LK_PI_ST Place within mils of IH ball T R K_N IHM Internal VR nable Strap (Internal VR for VccSus., VccSus., VccL.) Low = Internal VR isabled IH_INTVRMN High = Internal VR nabled(efault) IH_RTX IH_RTX IH_RTRST# GLN_LK LN_RX LN_RX LN_RX LN_TX LN_TX LN_TX R./F GLN_OMP R R Z_IT_LK Z_SYN Z_RST# Z_SOUT ST_TX-_ ST_TX+_ ST_TX-_ ST_TX+_ ST_TX-_ ST_TX+_ R./F STIS U G RTX F RTX F IH_INTRUR# INTRUR# IH_INTVRMN F IH_LN_SLP INTVRMN LN_SLP GLN_LK LN_RSTSYN LN_RX LN_RX LN_RX LN_TX LN_TX LN_TX H J H_IT_LK J H_SYN H_RST# J H_SIN H H_SIN H H_SIN H_SIN F RTRST# GLN_OK#/GPIO GLN_OMPI GLN_OMPO H_SOUT STL# F STRXN F STRXP H STTXN H STTXP G STRXN G STRXP J STTXN J STTXP ST_LKN ST_LKP G STRIS# G STRIS RT LP LN / GLN IH K_N K_N H_OK_N#/GPIO G H_OK_RST#/GPIO F STRXN F STRXP STTXN STTXP ST I,IHM,G,-,revp_ PU I IHM LN SLP Strap (Internal VR for VccLN. and VccL.) Low = Internal VR isabled IH_LN_SLP High = Internal VR nabled(efault) FWH/L FWH/L F FWH/L G FWH/L F FWH/LFRM# LRQ# G LRQ#/GPIO GT F M# G PRSTP# F PSLP# FRR# PUPWRG/GPIO IGNN# G F INIT# INTR RIN# H NMI SMI# G STPLK# THRMTRIP# TP V U V T V T T T R T V V U V U S# Y S# Y IOR# W IOW# W K# Y IIRQ Y IORY Y RQ W SIO_GT H_PRSTP# H_PSLP# H_FRR# SIO_RIN# THRMTRIP#_IH I_IRQ I_IORY I_ I_ I_ I_ I_ I_ I_ I_ I_ I_ I_ I_ I_ I_ I_ I_ I_ I_ I_ LP_L, LP_L, LP_L, LP_L, LP_LFRM#, SIO_GT H_M# H_PRSTP#,, H_PSLP# H_FRR# H_PWRGOO H_IGNN# H_INIT# H_INTR SIO_RIN# H_NMI H_SMI# H_STPLK# T T T T T T T T T T T T T T T T T T T T T T T T T T T R.K R.K T +.V_RUN H_PRSTP# H_PSLP# H_FRR# SIO_GT SIO_RIN# THRMTRIP#_IH R _N +.V_VP R _N R K +.V_RUN +.V_VP R R K R +.V_RUN XOR hain ntrance Strap IH RSV H SOUT escription RSV nter XOR hain Normal Operation (efault) Set PI port config bit R K_N Z_SOUT R K_N IH_RSV QUNT OMPUTR IH-M (PU,I,ST,LP,,LN) Size ocument Number Rev GM ate: Monday, March, Sheet of

Place TX blocking caps close IH. PI_TXN_ PI_TX-.U PI_TXP_ PI_TX+.U PI_TXN_ PI_TX-.U PI_TXP_ PI_TX+.U.U PI_TXN_ PI_TX- PI_TXP_ PI_TX+.U.U PI_TXN_ PI_TX- PI_TXP_ PI_TX+.U GLN_TXN_ PI_TX-/GLN_TX-.U.U GLN_TXP_ PI_TX+/GLN_TX+ IH_SPI_S#_R PI_GNT# R K_N R K_N LP PI SPI oot IOS Strap GNT# No stuff No stuff Stuff SPI_S# No stuff Stuff No stuff T T PI_RX-/GLN_RX- PI_RX+/GLN_RX+ Giga it LOM MiniWLN T PI_RX- PI_RX+ PI_RX- PI_RX+ MiniWWN T PI_RX- PI_RX+ MiniWPN T PI_RX- PI_RX+ US_O_# US_O_# US_O# T T xpress ard T T T T U P PRN P PI_TXN_ PRP N PI_TXP_ PTN N PTP T M PRN M PI_TXN_ PRP L PI_TXP_ PTN T L PTP K PRN K PI_TXN_ PRP J PI_TXP_ PTN J PTP T H PRN H PI_TXN_ PRP G PI_TXP_ PTN G PTP GLN_TXN_ GLN_TXP_ IH_SPI_S#_R US_O_# US_O_# O# O# O# O# US_O# O# F PRN F PRP PTN T PTP T PRN/GLN_RXN PRP/GLN_RXP PTN/GLN_TXN PTP/GLN_TXP SPI_LK SPI_S# SPI_S# SPI_MOSI F SPI_MISO J O# G O#/GPIO G O#/GPIO O#/GPIO F O#/GPIO G O#/GPIO O#/GPIO J O#/GPIO O# H O# PI-xpress irect Media Interface SPI US MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MI_LKN MI_LKP MI_ZOMP MI_IROMP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USRIS# USRIS V V U U Y Y W W T T Y Y G G H H H H J J K K K K L L M M M M N N F F MI_MTX_IRX_N MI_MTX_IRX_P MI_MRX_ITX_N MI_MRX_ITX_P MI_MTX_IRX_N MI_MTX_IRX_P MI_MRX_ITX_N MI_MRX_ITX_P MI_MTX_IRX_N MI_MTX_IRX_P MI_MRX_ITX_N MI_MRX_ITX_P MI_MTX_IRX_N MI_MTX_IRX_P MI_MRX_ITX_N MI_MRX_ITX_P LK_PI_IH# LK_PI_IH MI_OMP R./F +.V_PI_IH Place within mils of IH IH_USP- IH_USP+ Side pair Top / left IH_USP- IH_USP+ Side pair bottom / left IH_USP- IH_USP+ Side pair top/right() IH_USP- IH_USP+ Side pair ot right() PI Pullups IH_USP- IH_USP+ amera IH_USP- IH_USP+ Mini ard (WWN) IH_USP- IH_USP+ Mini ard (WPN) IH_USP- IH_USP+ xpress ard IH_USP- IH_USP+ left side signal US port RP IH_USP- PI_FRM# iometric IH_USP+ PI_STOP# PI_VSL# PI_RQ# USRIS +.V_RUN +.V_RUN PI_TRY# PI_PIRQ# PI_PIRQ# PI_SRR# WWN Noise - IH improvements O# O#.U_N.U_N O# O# US_O# US_O_# US_O_#.U_N.U_N.U_N.U_N.U_N O#.U_N Non-iMT +.V_SUS O# O# O# O# RP KX +.V_SUS US_O# US_O_# US_O_# O# Short F and F at the package and keep length to less than mils. Trace Impedance should be ohms +/- %. R./F PI_IRY# PI_PRR# PI_PLOK# PI_PIRQ# +.V_RUN RP +.V_RUN PI_PIRQ# IH_IRQH_GPIO PI_PIRQ# PI_RQ# PI_[..] T PI_PIRQ# PI_PIRQ# T PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# U G F PI RQ# GNT# RQ#/GPIO GNT#/GPIO RQ#/GPIO GNT#/GPIO RQ#/GPIO GNT#/GPIO /# /# /# /# IRY# PR PIRST# VSL# PRR# PLOK# SRR# STOP# TRY# FRM# PLTRST# PILK PM# Interrupt I/F F PIRQ# PIRQ# PIRQ# PIRQ# PIRQ#/GPIO PIRQF#/GPIO PIRQG#/GPIO PIRQH#/GPIO PI_RQ# PI_GNT# PI_RQ# PI_GNT# S_WWN_PI_RST# F PI_GNT# S_LOM_PI_RST# PI_GNT# F PI_IRY# G PI_RST#_G PI_VSL# PI_PRR# PI_PLOK# F PI_SRR# PI_STOP# PI_TRY# PI_FRM# G PI_PLTRST# LK_PI_IH G F S_WPN_PI_RST# G S_WLN_PI_RST# F S_N_PI_RST# IH_IRQH_GPIO PI_RQ# PI_GNT# T T S_WWN_PI_RST# T S_LOM_PI_RST# T PI # PI # PI # PI # PI_IRY# PI_PR PI_VSL# PI_PRR# PI_PLOK# PI_SRR# PI_STOP# PI_TRY# PI_FRM# LK_PI_IH T IH_PM#, T T T T T T S_WPN_PI_RST# S_WLN_PI_RST# S_N_PI_RST# T T T T T T T T PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_IRY# PI_TRY# PI_FRM# PI_STOP# PI_VSL# PI_GNT# PI_RQ# PI_GNT# away override strap. Low = swap override enabled. S_N_PI_RST# High = efault. T T T T T T T T T T T T T T R K_N LK_PI_IH.P_N Reserved for MI.Place resister and cap close to IH. R _N Non-iMT PI_RST#_G PI_PLTRST# S_WPN_PI_RST# S_WWN_PI_RST# S_WLN_PI_RST# S_LOM_PI_RST# S_N_PI_RST# IOS should not enable the internal GPIO pull up resistor..u.u +.V_SUS U +.V_SUS QUNT OMPUTR IH-M (US,MI,PI,PI) dd uffers as needed for Loading and fanout concerns. TSZFU(TL,F,T) U TSZFU(TL,F,T) R R R R R PI_RST# K K K K K PLTRST#,,,,, Size ocument Number Rev GM ate: Monday, March, Sheet of

+.V_SUS RP Non-iMT IH_SMT IH_SMLK Place these close to IH. Non-iMT +.V_SUS IH_SMLK R IH_SMLINK IH_SMT R IH_SMLINK R _N +.V_RUN LKRUN# K_L_T# PI_MR_T# +.V_RUN +.V_RUN +.V_SUS.KX IH_SMLINK IH_SMLINK Option to " isable " clkrun. Pulling it down will keep the clks running. R RP R R R R KX_N R.K K R K R K R K R K R K R K R K R K US_MR_T# US_MR_T# SIO_XT_WK# SIO_XT_SMI# SIO_XT_SI# R _N PI_MR_T# R.K PI_MR_T# PI_MR_T# WLN_RIO_IS# MR_L_T# ST_LKRQ# PLTRST_LY# PLTRST_LY# WPN_RIO_IS_MINI# WWN_RIO_IS#.K_N IMVP_PWRG SF. US_MR_T# US_MR_T# PI_MR_T# PI_MR_T# PI_MR_T# K_N MH_IH_SYN#_R K IRQ_SRIRQ K THRM_LRT# RSV_WOL_N SIO_XT_SMI# US_MR_T# +.V_SUS,, IH_SMLK,, IH_SMT T T T PM_MUSY# H_STP_PI# H_STP_PU#, LKRUN#,,, PI_WK#, IRQ_SRIRQ THRM_LRT#,, IMVP_PWRG MH_IH_SYN# R R R R T ITP_RST# US_MR_T# SPKR IH_RSV T +.V_RUN K_N K K K R R K_N RSV_IH_L_RST# IH_RI# SIO_XT_SI# PI_WK# IH_SMLK IH_SMT RSV_IH_L_RST# IH_SMLINK IH_SMLINK IH_RI# RSV_LPP# US_MR_T# LKRUN# PI_WK# IRQ_SRIRQ THRM_LRT# IMVP_PWRG US_MR_T# US_MR_T# SIO_XT_SMI# SIO_XT_SI# PI_MR_T# PI_MR_T# PLTRST_LY# SPKR SPKR No Reboot strap. Low = efault. SPKR High = No Reboot. Non-iMT U J SMLK SMT G LINKLRT# SMLINK SMLINK F F SUS_STT#/LPP# SYS_RST# G G MUSY#/GPIO SMLRT#/GPIO STP_PI#/GPIO G STP_PU#/GPIO H LKRUN#/GPIO WK# F SRIRQ THRM# J J RI# VRMPWRG TP J TH/GPIO J TH/GPIO H TH/GPIO GPIO GPIO G TH/GPIO H GPIO GPIO G SLOK/GPIO H QRT_STT/GPIO QRT_STT/GPIO G STLKRQ#/GPIO F SLO/GPIO J STOUT/GPIO STOUT/GPIO SPKR MH_IH_SYN#_R J MH_SYN# J TP SMbus address These are for backdrive issue. SM ST GPIO locks SYS GPIO Power MGT MIS GPIO ontroller Link STGP/GPIO J STGP/GPIO J STGP/GPIO F STGP/GPIO G +.V_RUN +.V_RUN LK_IH_M LK_IH_M IH_SUSLK IH_TLOW# RSV_IH_LN_RST# IH_RSMRST# IH_L_PWROK RSV_IH_L_LK RSV_IH_L_T L_VRF L_VRF RSV_GPIO RSV_GPIO RSV_WOL_N Q,, IH_SMT MM_ST +.V_RUN LK G LK G SUSLK SLP_S# G SLP_S# F SLP_S# S_STT#/GPIO R.K PWROK IH_PWRG PRSLPVR PRSLPVR/GPIO J TLOW# PWRTN# LN_RST# RSMRST# K_PWRG LPWROK SLP_M# H H G J L_LK F L_LK L_T F L_T F L_VRF L_VRF H L_RST# J MM_L/GPIO J M LRT/GPIO J _M_LRT/GPIO F WOL_N/GPIO G NW--F RP.KX Non-iMT LK_IH_M LK_IH_M T SIO_SLP_S# T SIO_SLP_S# IH_PWRG, PRSLPVR, R.K +.V_SUS SIO_PWRTN# IH_RSMRST# LK_PWRG IH_L_PWROK, L_LK T L_T T R.K T T T IH_L_RST# T T T +.V_SUS Non-iMT IH_PWRG PRSLPVR IH_RSMRST# RSV_IH_LN_RST# IH_L_PWROK RSV_GPIO Non-iMT L_VRF.U +.V_RUN LK_IH_M LK_IH_M R R K R R R R /F R _N R _N R R.K/F IS:LW UM:SUS L_VRF +.V_SUS +.V_LW +.V_SUS.U_N.P_N.P_N K K K M K R R.K/F_N.K/F_N R /F_N,, IH_SMLK Q NW--F MM_SLK QUNT OMPUTR IH-M (PM,GPIO,SM,L) Size ocument Number Rev GM ate: Monday, March, Sheet of

+IH_VRF_SUS +IH_VRF_RUN +.V_MIPLL TP_VSUS._ TP_VSUS._ TP_VSUS._ TP_VSUS._ TP_VL. +VL_ +VSTPLL +VSTPLL_L +VSTPLL TP_VSUSLN TP_VSUSLN +.V_MIPLL_R +.V_VP +.V_RUN +.V_SUS +.V_RUN +V_RUN +V_SUS +.V_SUS +RT_LL +.V_RUN +.V_VP +.V_SUS +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_PI_IH +.V_RUN +.V_RUN +.V_PI_IH +.V_VP +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_VP Size ocument Number Rev ate: Sheet of QUNT OMPUTR GM IH-M (POWR,GN) Monday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTR GM IH-M (POWR,GN) Monday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTR GM IH-M (POWR,GN) Monday, March, uh+-%_m F_ohm+-%_mHz_._. ohm uh+-%_m Non-iMT Non-iMT Place close to. Non-iMT Non-iMT Non-iMT Non-iMT WWN Noise - IH improvements WWN Noise - IH improvements close to &.U.U.U.U U. U. L uh L uh.u.u T T.U.U + U + U.U.U R R T T U U.U.U.U_N.U_N.U_N.U_N.U_N.U_N U U T T/R T T/R.U_N.U_N.U_N.U_N U U.U.U.U.U U U.U..U..U.U L uh L uh.u.u R R.U.U R R.U_N.U_N.U.U.U_N.U_N T T U U.U.U U U.U.U T T U U VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] F VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] J VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] F VSS[] VSS[] F VSS[] F VSS[] F VSS[] G VSS[] VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] H VSS_NTF[] H VSS_NTF[] J VSS_NTF[] J VSS_NTF[] J VSS_NTF[] J VSS_NTF[] VSS_NTF[] VSS[] VSS[] VSS[] VSS[] VSS[] U VSS[] K VSS[] W.U.U.U.U.U.U.U.U T T.U.U OR VGP TX RX I US OR PI GLN POWR VP_OR VPSUS VPUS UF OR VGP TX RX I US OR PI GLN POWR VP_OR VPSUS VPUS UF VRF[] VRF[] T VRF_SUS G V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] F V [] F V [] G V [] H V [] H V [] J V [] J V [] K V [] K V [] L V [] L V [] L V [] M V [] M V [] N V [] N V [] N V [] P V [] P V [] R V [] R V [] R V [] R V [] T V [] T V [] T V [] T V [] T V [] U V_[] F VMIPLL R V [] V [] F V [] G V [] H V [] J VSTPLL J V_[] V [] V [] V [] V [] V [] VUSPLL VLN_[] F VLN_[] G V_[] V_[] V_[] V_[] V_[] V_[] V_[] F V_[] G V_[] L V_[] L V_[] L V_[] L V_[] L V_[] L V_[] M V_[] M V_[] P V_[] P V_[] T V_[] T VLN_[] F VLN_[] G VH VSUSH V_PU_IO[] V_PU_IO[] V_[] V_[] U V_[] V V_[] W V_[] W V_[] W V_[] Y V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] F VRT VSUS_[] VSUS_[] VSUS_[] VSUS_[] G VSUS_[] H VSUS_[] P VSUS_[] P VSUS_[] VSUS_[] N VSUS_[] P VSUS_[] P VSUS_[] P VSUS_[] P VSUS_[] P VSUS_[] R VSUS_[] R VSUS_[] R V [] V [] V [] V [] V [] G V [] G VSUS_[] J VSUS_[] F V [] F V [] L V [] L V [] M V [] M VSUS_[] V_[] V [] W V_[] U V_[] V V_[] V V_[] V V_[] U V_[] V V_[] V V_[] V VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_ VGLNPLL V_[] F V_[] V_[] V_[] VSUS_[] R V [] H VSUS_[] V [] V [] VSUS_[] J V_MI[] V_MI[] VL_ G VL_[] G VL_[] F VL_ V [] W V [] V V [] U V [] Y V [] V V [] V R R.U.U.U.U SMKL--F SMKL--F P U_N P U_N U. U. U U.U.U T T.U_N.U_N L LMPGSN L LMPGSN.U.U T T.U.U SMKL--F SMKL--F U U U U.U_N.U_N R R.U.U

R M R M R QS R QS# R M R M R M R R QS R R M R R M R M R M R QS# R M R QS R S R W# R R M R M R M R R S# R QS# R M R M R QS# R M R R M R R R R R QS R R R QS R R R R R R R R R R R R QS# R QS R R R R R R QS# M_OT M_OT R R S R QS# R QS R QS# R RS# R R R R M R QS R R R M R R R R R M R M R M R S R QS R M R M R M R R R R R R QS R R R QS R R M R R R QS# M_OT R M R QS# R R M R R M M_OT R QS# R QS# R R R R R R M R S R QS# R R M R R R QS R W# R M R R M R M R R M R R R QS R R RS# R M R R R R QS# R R M R S R M R S R R QS R R R QS# R R R QS R QS R M R R S# R M R R QS# R M R R R M R R R R M R R M R R MM_SLK MM_ST MM_ST MM_SLK PM_XTTS# PM_XTTS# R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R QS#[..] R [..] R M[..], R M[..] R QS[..] R_S_IMM#, R_S_IMM#, R QS#[..] R [..] R M[..], R S, R M[..] M_OT, M_LK_R R RS#, R QS[..] R_S_IMM#, R_S_IMM#, R S, R RS#, R_K_IMM, R S, R_K_IMM, R S, M_LK_R# M_LK_R PM_XTTS# M_LK_R M_LK_R# M_LK_R R S#, R S, R W#, R_K_IMM, M_OT, R S#, R W#, R S, R_K_IMM, M_OT, M_LK_R# M_LK_R# M_OT, R M, R M, PM_XTTS# MM_ST MM_SLK +.V_RUN +.V_SUS +V_R_MH_RF +.V_RUN +.V_SUS +.V_SUS +V_R_MH_RF +.V_SUS +.V_RUN +.V_RUN +V_R_MH_RF +V_R_MH_RF +.V_RUN +.V_SUS +.V_SUS +.V_SUS +.V_SUS Size ocument Number Rev ate: Sheet of QUNT OMPUTR GM R_SO-IMM (P) X Monday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTR GM R_SO-IMM (P) X Monday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTR GM R_SO-IMM (P) X Monday, March, LOK, LOK, SMbus address SMbus address K, K, Place these aps near So-imm. Place these aps near So-imm. Place these aps near So-imm. Place these aps near So-imm. H. H. MSTR SLV.U_.V.U_.V R K R K.U_V.U_V.U_.V.U_.V R K R K.U_V.U_V.U_V.U_V.U_.V.U_.V.U_V.U_V.U_.V.U_.V.U_.V.U_.V.U_V.U_V.U_V.U_V.U_.V.U_.V.U_V.U_V.U_.V.U_.V.U_.V.U_.V.U_.V.U_.V.U_V.U_V R K R K P R SRM SO-IMM (P) JIM TY_-- P R SRM SO-IMM (P) JIM TY_-- VRF VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS K V N _ V V V /P W# V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS Q Q VSS M VSS Q Q VSS Q Q VSS M VSS K K# VSS Q Q VSS VSS Q Q VSS N M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS K V V V V RS# S# V OT V N VSS Q Q VSS M VSS Q Q VSS Q Q VSS VSS M VSS Q Q VSS Q Q VSS NTST VSS QS# QS VSS Q Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS Q Q VSS Q Q VSS K K# VSS M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS S S VSS.U_V.U_V.U_.V.U_.V.U_.V.U_.V.U_V.U_V P R SRM SO-IMM (P) JIM TY_-- P R SRM SO-IMM (P) JIM TY_-- VRF VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS K V N _ V V V /P W# V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS Q Q VSS M VSS Q Q VSS Q Q VSS M VSS K K# VSS Q Q VSS VSS Q Q VSS N M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS K V V V V RS# S# V OT V N VSS Q Q VSS M VSS Q Q VSS Q Q VSS VSS M VSS Q Q VSS Q Q VSS NTST VSS QS# QS VSS Q Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS Q Q VSS Q Q VSS K K# VSS M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS S S VSS.U_.V.U_.V.U_V.U_V.U_.V.U_.V R K R K.U_V.U_V.U_.V.U_.V

+.V_R_VTT Layout note: Place cap close to every R-pack terminated to SMR_VTRM..U_V.U_V.U_V.U_V.U_V.U_V.U_V.U_V.U_V.U_V.U_V.U_V.U_V +.V_R_VTT.U_V.U_V.U_V.U_V.U_V.U_V.U_V.U_V.U_V.U_V.U_V.U_V.U_V +.V_R_VTT, R M[..] R M[..], R M R M RP RP R M R M R M R M PR-S- RP PR-S- RP R M R M, R S, R RS#, M_OT, R S R S R RS# R M M_OT R S R M PR-S- RP PR-S- RP PR-S- RP PR-S- RP PR-S- RP PR-S- RP R S R RS# M_OT R M R M R M R S, R RS#, M_OT, Please these resistor closely IMM,all trace length< mil. R M R M R M R M PR-S- RP PR-S- RP PR-S- RP PR-S- RP R M R M R M R M Please these resistor closely IMM,all trace length< mil., R S R S R M PR-S- RP PR-S- RP R S R M R S, T, R S#, R W# R S# R W# R M R M PR-S- RP PR-S- RP PR-S- RP PR-S- RP R S# R W# R M R M R S#, R W#,, R_S_IMM# PR-S- PR-S- R, M_OT R M_OT, R M R R R S, R R R_S_IMM#, R R, R_S_IMM# R_S_IMM#, R, R_K_IMM R R_K_IMM, R, R_K_IMM R R_K_IMM, R, R M R R M, QUNT OMPUTR R RS. RRY Size ocument Number Rev GM ate: Monday, March, Sheet of

dd capacitor pads for improving WWN. LK_XTL_IN P ST_LKRQ# LK_GPLLRQ# LK_LP_UG LK_PI_PR LK_PI_ LK_PI_IH LK_IH_M, PU_MH_SL, PU_MH_SL, PU_MH_SL +.V_RUN P P_N P_N P_N P_N LK_IH_M LK_PWRG L.MHz ohms@mhz ohms@mhz.mhz LK_IH_M LK_IH_M LK_PI_ LK_PI_PR LK_PI_IH Y LK_XTL_OUT ST_LKRQ# LK_GPLLRQ# LK_IH_M R R.K L LMSG R.K R.K LK_IH_M LK_LP_UG FOR UG N POP RSISTOR LMPGSN L LMPGSN.U R. R. R. R R /F LK_LP_UG R _N LK_PI_PR R LK_PI_ R LK_PI_IH R.U R. P +K_V_MIN +K_V_PI +K_V_PLL +K_V_ R.U.U +K_V_SR.U. +K_V_PI +K_V_PLL +K_V_ +K_V_SR +K_V_MIN ST_LKRQ#_ LK_GPLLRQ#_ PI_PR PI_SIO M_SL PI_IH FS FS FS LK_XTL_OUT LK_XTL_IN LK_ST LK_SLK UM without imt.u.u.u.u.u.u. U_N U V_PI V_RF V_PLL V_ V_SR V_PU V_IO V_IO V_IO V_IO V_IO V_IO GN GN GN GN GN GN GN GN GN R#_/PI- R_/PI- TM/PI- SR_N/PI- M_SL/PI- ITP_N/PIF-# FS/US FS/TST_MO FS/TST_SL/RF RST# K_PWRG/P# XOUT XIN ST SLK SLGSPV OT_SS OT_SS# M_SS M_NSS,, SMT,, SMLK PU_ITP PU_ITP# SMbus address These are for backdrive issue. K QFN +.V_RUN +.V_RUN OT_SS OT_SS# M_NSS M_SS POP RSISTOR FOR UM Q NW--F PU- PU-# PU- PU-# SR-/PU_ITP SR-#/PU_ITP# SR-/OT SR-#/OT# SR-/S SR-#/S SR-/ST SR-#/ST# R#_/SR- R#_/SR-# SR- SR-# PI_STOP#/SR- PU_STOP#/SR-# SR- SR-# R#_F/SR- R#_/SR-# SR- SR-# SR- SR-# R#_H/SR- R#_G/SR-# Q NW--F GN RP RP RP RP.KX MINILK_RQ#_ R_LK_RQ#_ LK_ST LK_SLK PU_LK PU_LK# MH_LK MH_LK# PI_ST PI_ST# PI_MINI PI_MINI# MH_GPLL MH_GPLL# PI_XPR PI_XPR# PI_MINI PI_MINI# PI_IH PI_IH# PI_LOM PI_LOM# _UM _UM _N Non-iMT PU_ITP PU_ITP# to MH PLL_RF_LK MH_RFLK MH_RFLK# to MH PLL_RF_SSLK RF_SSLK# RF_SSLK LK_PU_ITP LK_PU_ITP# POP for ITP use M_SL RP RP RP R R /F /F MINILK_RQ# R_LK_RQ# RP RP RP RP RP RP RP +.V_RUN _IS _IS RP RP PI_IH R K_IS R K_UM +.V_RUN M_SL M_SL (PIN) =UM = isc. GRFX down LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# LK_PI_MINI LK_PI_MINI# LK_PI_VG LK_PI_VG# LK_VG_M_NSS LK_VG_M_SS LK_PI_ST LK_PI_ST# LK_PI_MINI LK_PI_MINI# LK_MH_GPLL LK_MH_GPLL# H_STP_PI# H_STP_PU# LK_PI_XPR LK_PI_XPR# MINILK_RQ# R_LK_RQ# LK_PI_MINI LK_PI_MINI# LK_PI_IH LK_PI_IH# LK_PI_LOM LK_PI_LOM# R K_N R K_N OTT SRT LK_GPLLRQ# ST_LKRQ# R_LK_RQ# MINILK_RQ# PI_PR PI_SIO PI_IH OT SR H_STP_PI# H_STP_PU# FS FS FS PU SR PI PIN PIN PIN PIN QUNT OMPUTR LOK GNRTOR to TI VG Silego need pull up but other? R K R K R K R K R K_N R K_N R K_N RSV / M_T Mout R R / M_ MSSout +.V_RUN +.V_RUN Size ocument Number Rev GM K K ate: Monday, March, Sheet of

PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_P PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MTX_GRX_N PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX_P PI_MRX_GTX P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX_P PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_N PI_MRX_GTX_P[..] PI_MTX_GRX_P[..] PI_MTX_GRX_N[..] PI_MRX_GTX_N[..] LK_PI_VG LK_PI_VG# PLTRST_LY# +PI_V Size ocument Number Rev ate: Sheet of QUNT OMPUTR GM VG-M-S (PIe) Monday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTR GM VG-M-S (PIe) Monday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTR GM VG-M-S (PIe) Monday, March,.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS R K/F_IS R K/F_IS R _IS R _IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS PRT OF alibration P I - X P R S S I N T R F lock SM us U M-LP_IS PRT OF alibration P I - X P R S S I N T R F lock SM us U M-LP_IS PI_TXP G PI_TXN G PI_TXP F PI_TXN F PI_TXP F PI_TXN F PI_TXP PI_TXN PI_RXP K PI_RXN J PI_RXP J PI_RXN J PI_RXP H PI_RXN H PI_RXP G PI_RXN G PI_TXP PI_TXN PI_TXP PI_TXN PI_TXP PI_TXN PI_TXP PI_TXN PI_RXP F PI_RXN PI_RXP PI_RXN PI_RXP PI_RXN PI_RXP PI_RXN PI_RFLKP J PI_RFLKN J PRST M PI_TXP PI_TXN PI_TXP W PI_TXN W PI_TXP W PI_TXN W PI_TXP V PI_TXN V PI_RXP PI_RXN PI_RXP PI_RXN PI_RXP Y PI_RXN Y PI_RXP W PI_RXN W PI_TXP V PI_TXN V PI_TXP U PI_TXN U PI_TXP U PI_TXN U PI_TXP R PI_TXN R PI_RXP V PI_RXN U PI_RXP U PI_RXN U PI_RXP T PI_RXN T PI_RXP R PI_RXN R PI_LRN G PI_LRP J N_SMLK K N_SM_T K N_FN_TH K N_RM_ F N_RM_ G N TT K.U_IS.U_IS.U_IS.U_IS R.K_IS R.K_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS.U_IS