Logic Deign CS 270: Mathematical Foundation of Computer Science Jeremy Johnon
Logic Deign Objective: To provide an important application of propoitional logic to the deign and implification of logic circuit. 2
Topic Logic gate and, or, inverter nand Logic circuit Encoder, decoder, multiplexor Simplification of logic circuit Full adder Implementation of a imple proceor 3
Logic Circuit A ingle line labeled x i a logic circuit. One end i the input and the other i the output. If A and B are logic circuit o are: and gate A B or gate A B inverter (not) A 4
Cacaded and gate Multi-Input Gate A B C D ((A B) C) D (A B) (C D) A (B (C D)) A B A B C D C D A B C D 5
Logic Circuit Given a boolean expreion it i eay to write down the correponding logic circuit Here i the circuit for the original multiplexor expreion x 0 x 1 6
Logic Circuit Here i the circuit for the implified multiplexor expreion x 0 x 1 7
Nand Nand negation of the conjunction operation: x y x y 0 0 1 0 1 1 1 0 1 1 1 0 A nand gate i an inverted and gate: 8
Implementing Logic Gate with Tranitor +V +V gate output A B A NAND B ground ground A Tranitor NOT Gate A Tranitor NAND Gate 9
Decoder A decoder i a logic circuit that ha n input (think of thi a a binary number) and 2 n output. The output correponding to the binary input i et to 1 and all other output are et to 0. d 0 b 0 d 1 b 1 d 2 d 3 10
Encoder An encoder i the oppoite of a decoder. It i a logic circuit that ha 2 n input and n output. The output equal to the input line (in binary) that i et to 1 i et to 1. d 0 d 1 b 0 d 2 d 3 b 1 11
Multiplexor A multiplexor i a witch which route n input to one output. The input i elected uing a decoder. d 0 d 1 d 2 d 3 1 0 12
XOR One or the other, but not both Notation for circuit: x y x y 0 0 0 0 1 1 1 0 1 1 1 0 x y x y
Full Adder Ued to add to binary number tored a an array of bit uing carry ripple addition CarryIn Three binary input a, b and CarryIn Two binary output Sum and CarryOut uch that a + b + CarryIn = 2*CarryOut + Sum Carry 110 A 101 B 111 A+B = 1100 a b CarryOut Sum 14
Exercie Derive a truth table for the output bit (Sum and CarryOut) of a full adder. Uing the truth table derive a um of product expreion for Sum and CarryOut. Draw a circuit for thee expreion. Uing propertie of Boolean algebra implify your expreion. Draw the implified circuit. CarryIn a b Sum CarryOut 15
Building a Computer from Logic Gate Objective: To develop a imple model of a computer and it execution that i capable of executing RAM program. To introduce the concept of abtraction in computer deign. The model will be given chematically with timing equence. RAL intruction will be implemented uing microintruction decribed in a notation called Regiter Tranfer Language (RTL). The control logic for implementing microintruction will be decribed at the gate level. Reference: Dewdney, The New Turing Omnibu (Chapter 48). Lec 2 Sytem Architecture 16
SCRAM A Simple but Complete Random Acce Machine. Thi computer can execute RAL intruction. 8-bit word 16 word memory (4 addre bit) Intruction (4 bit opcode, 4 bit operand) 7 regiter PC (program counter) IR (intruction regiter - IR(C) = intruction code, IR(O) = operand MAR (memory addre regiter) MBR (memory buffer regiter) AC (accumulator) AD (regiter for addition internal to the ALU - arithmetic logic unit) Driven by the CLU (control logic unit) A timer T generate pule that are decoded into eparate input line to the CLU Lec 2 Sytem Architecture 17
Fetch and Execute A cycle of operation conit of two tage The fetch cycle get the next executable intruction and load it into the IR The execute cycle perform the intruction in the IR The fetch and execute cycle are written a a equence of micro-intruction decribed in a notation called Regiter Tranfer Language (RTL) Important: thi machine ue a timer T that tick everal time per each of the two cycle; therefore, the fetch and execute cycle conit of everal clock cycle. Lec 2 Sytem Architecture 18
PC INC MAR MUX 0 1 2 3 Memory READ/ WRITE IR(C) Decoder IR(O) MBR MUX 0 1 q 9 q 8 q 7 q 6 q 5 q 4 q 3 q 2 q 1 x 1 x 2 x 3 x 4 x 5 CLU t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 INC 0 1 2 3 MUX CLEAR AC ALU AD MUX 0 1 Decoder T Lec 2 Sytem Architecture 19
Intruction Opcode LDA 0001 X; Load content of memory addre X into the AC LDI 0010 X; Indirectly load content of addre X into the AC STA 0011 X; Store content of AC at memory addre X STI 0100 X; Indirectly tore content of AC at addre X ADD 0101 X; Add content of addre X to the AC SUB 0110 X; Subtract content of addre X from the AC JMP 0111 X; Jump to the intruction labeled X JMZ 1000 X; Jump to intruction X if the AC contain 0 Lec 2 Sytem Architecture 20
Microprogram Fetch cycle t 0 : MAR PC t 1 : MBR M; PC PC + 1 t 2 : IR MBR Execute cycle (LDA) q 1 t 3 : MAR IR(O) q 1 t 4 : MBR M q 1 t 5 : AC MBR Lec 2 Sytem Architecture 21
Microprogram Execute cycle (LDI) q 2 t 3 : MAR IR(O) q 2 t 4 : MBR M q 2 t 5 : MAR MBR q 2 t 6 : MBR M q 2 t 7 : AC MBR Execute cycle (ADD) q 5 t 3 : MAR IR(O) q 5 t 4 : MBR M q 5 t 5 : AD MBR q 5 t 6 : AD AD + AC q 5 t 7 : AC AD Lec 2 Sytem Architecture 22
Microprogram Execute cycle (JMP) PC relative addreing q 7 t 3 : AC PC q 7 t 4 : AD AC q 7 t 5 : AC IR(0) q 7 t 6 : AD AD + AC q 7 t 7 : AC AD q 7 t 8 : PC AC Execute cycle (JMP) abolute addreing q 7 t 3 : AC IR(0) q 7 t 4 : PC AC Lec 2 Sytem Architecture 23
Control Logic for the Fetch Cycle t 0 : MAR PC t 1 : MBR M; PC PC + 1 t 2 : IR MBR t 0 x 10 x 10 x 4 t 1 x 7 x 2 x 5 x 13 t 2 x 1 Lec 2 Sytem Architecture 24
PC INC MAR MUX 0 1 2 3 Memory READ/ WRITE IR(C) Decoder IR(O) MBR MUX 0 1 q 9 q 8 q 7 q 6 q 5 q 4 q 3 q 2 q 1 x 1 x 2 x 3 x 4 x 5 CLU t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 Decoder x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 INC T 0 1 2 3 MUX CLEAR AC ALU AD MAR PC MUX 0 1 Lec 2 Sytem Architecture 25
PC INC MAR MUX 0 1 2 3 Memory READ/ WRITE IR(C) Decoder IR(O) MBR MUX 0 1 q 9 q 8 q 7 q 6 q 5 q 4 q 3 q 2 q 1 x 1 x 2 x 3 x 4 x 5 CLU t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 Decoder x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 INC T 0 1 2 3 MUX CLEAR AC ALU AD MUX 0 1 MBR M; PC PC + 1 Lec 2 Sytem Architecture 26
PC INC MAR MUX 0 1 2 3 Memory READ/ WRITE IR(C) Decoder IR(O) MBR MUX 0 1 q 9 q 8 q 7 q 6 q 5 q 4 q 3 q 2 q 1 x 1 x 2 x 3 x 4 x 5 CLU t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 Decoder x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 INC T 0 1 2 3 MUX CLEAR AC ALU AD MUX 0 1 IR MBR Lec 2 Sytem Architecture 27
Logic for Loading the Accumulator q 1 t 3 x 10 x 10 MAR IR(0) x 4 x 2 t 4 x 7 MBR M x 5 t 5 x 11 x 11 x 12 AC MBR Lec 2 Sytem Architecture 28
PC INC MAR MUX 0 1 2 3 Memory READ/ WRITE IR(C) Decoder IR(O) MBR MUX 0 1 q 9 q 8 q 7 q 6 q 5 q 4 q 3 q 2 q 1 x 1 x 2 x 3 x 4 x 5 CLU t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 Decoder x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 INC T 0 1 2 3 MUX CLEAR AC ALU AD MUX 0 1 MAR IR(0) Lec 2 Sytem Architecture 29
PC INC MAR MUX 0 1 2 3 Memory READ/ WRITE IR(C) Decoder IR(O) MBR MUX 0 1 q 9 q 8 q 7 q 6 q 5 q 4 q 3 q 2 q 1 x 1 x 2 x 3 x 4 x 5 CLU t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 Decoder x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 INC T 0 1 2 3 MUX CLEAR AC ALU AD MBR M MUX 0 1 Lec 2 Sytem Architecture 30
PC INC MAR MUX 0 1 2 3 Memory READ/ WRITE IR(C) Decoder IR(O) MBR MUX 0 1 q 9 q 8 q 7 q 6 q 5 q 4 q 3 q 2 q 1 x 1 x 2 x 3 x 4 x 5 CLU t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 Decoder x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 INC T 0 1 2 3 MUX CLEAR AC ALU AD AC MBR MUX 0 1 Lec 2 Sytem Architecture 31
CLU Logic Some of the output line from the two previou lide appear in both circuit. It i neceary to have ome logic to connect and coordinate the individual output to the wire leaving the CLU. Lec 2 Sytem Architecture 32
Exercie Write microprogram for STA, STI, and JMZ. Implement the microprogram in tandard logic. Deign the portion of the CLU that determine the two output line labeled x 10. Input to thi circuit will be one or both of the line previouly labeled x 10 in the individual circuit for LDA, LDI, and the other circuit. Convert the following program to the equivalent et of binary word, a indicated in thi chapter. Thi i called machine code. Trace the execution of the program by liting the q, t, and x variable. LDA 1 ADD 2 STA 3 Lec 2 Sytem Architecture 33