Chapter 3 ipolar Junction Transistors
Goal. ipolar Junction Transistor Operation in amplifier circuits. 2. Load-line Analysis & Nonlinear Distortion. 3. Large-signal equialent circuits to analyze JT circuits. 4. ias circuits. 5. Small-signal equialent circuits to analyze JT amplifiers. 6. Seeral Important Amplifier Configurations.
st Transistor rattain and ardeen's pnp point-contact germanium transistor operated s a speech amplifier with a power gain of 8 on December 23, 947
Explanation of st Transistor his picture shows the workbench of John ardeen and Walter rattain t ell Laboratories. They were supposed to be doing fundamental esearch about crystal surfaces. The experimental results hadn't been ery good, though, and there's a rumor that their boss, William hockley, came near to canceling the project. ut in 947, working lone, they switched to using tremendously pure materials. It dawned n them that they could build the circuit in the picture. It was a working mplifier! John and Walter submitted a patent for the first working oint contact transistor. Shockley was furious and took their work and nented the junction transistor and submitted a patent for it 9 days ater. The three shared a Nobel Prize. ardeen and rattain continued in esearch (and ardeen later won another Nobel). Shockley quit to start emiconductor company in Palo Alto. It folded, but its staff went on to nent the integrated circuit (the "chip") and to found Intel Corporation y 960, all important computers used transistors for logic, and ferrite
- from ell Laboratories ecord magazine January 975, p.74 Major Milestones in Transistor Electronics 948 - POINT CONTACT TANSISTO 950 - SINGLE-CYSTAL GEMANIUM 95 - GOWN JUNCTION TANSISTO 952 - ALLOY JUNCTION TANSISTO 952 - ZONE MELTING AND EFINING 952 - SINGLE-CYSTAL SILICON 955 - DIFFUSED -ASE TANSISTOS 957 - OXIDE MASKING 960 - PLANA TANSISTO 960 - MOS TANSISTO 960 - EPITAXIAL TANSISTO 96 - INTEGATED CICUITS
Close-Up of 2N23 transistor by Western Electric in 954
Transistor 948 년미국 ell Lab 의 Walter Houser rattain, John ardeen 및 William radford Shockley 는반도체격자구조의시편 ( 試片 ) 에가는도체선을접촉시켜주면전기신호의증폭작용을나타내는것을발견하여이를트랜지스터라고명명하였다. 이것이그동안신호증폭의구실을해오던진공관 ( 眞空管 ) 과대치되는트랜지스터의시초가된것이다. 트랜지스터그자체가소형이어서이를사용하는기기 ( 機器 ) 는진공관을사용할때에비하여소형이되며, 가볍고소비전력이적어편리하다. 초기에는잡음 주파수특성이나쁘고, 증폭도도충분하지못하였으나, 그후많이개량되어아주대전력을다룰수있는등특수한경우를제외하고는진공관에대치되었다. - 두산백과사전 - The Most asic & Important Actie Component - Power Amplification - IC uses more recently : interfacing required - if no proper IC, only transistor can do something.
Transistor Function: Current Amplification Type : PNP, NPN Type Code : PNP High Frequency (2SA ) PNP Low Frequency (2S ) NPN High Frequency (2SC ) NPN Low Frequency (2SD ) 마이너스전압측을접지로, 플러스전압측을전원으로하는회로의경우, NPN 타입쪽이사용하기쉽다.
Lead in Transistor NPN : 2SC85 NPN : 2SD880 품명이인쇄되어있는면을바라보았을때, 오른쪽리드가베이스중앙의리드가컬렉터왼쪽의리드가이미터 품명이인쇄되어있는면을바라보았을때, 오른쪽리드가이미터중앙의리드가컬렉터왼쪽의리드가베이스 지스터의종류에따라리드의내용이다르기때문에매뉴얼등을참조하여확인할필요가있다 같은 npn 인데리드가다름
Transistor Man Transistor Man obseres the base current and adjusts the output rheostat in an attempt to maintain the output current h FE times larger
asic Transistor Model In npn Transistor, for example. Collector must be more positie than Emitter 2. ase-emitter and ase-collector behae like diode 3. Maximum Parameter V CE : Voltage between Collector and Emitter at open ase V E : Voltage between ase and Emitter I C : Collector Current I : ase Current P : Power Dissipation at Collector at C 25o C f T : frequency at I C I 4. Collector Current is proportional to ase Current I C h FE I h FE : Current Gain 00 ~ 300 Note : h FE is not a good parameter {range : 00-300} Circuit based on a particular h FE alue is a bad circuit
Schematic of JT Transistor Small fraction of Emitter Current flows into ase (C- junction : eerse ias, -E Junction : Forward ias) Typical Junction Connection
Equations of Operation t -E Junction Schokley Equation KCL i E E I ES exp VT i i + E C i et α i i C E i C I s E i C αi ES exp VT exp V E T β i i C I α α s αi ES : Scale Current : Typically 00 i β i C
Common-Emitter Characteristics P N N C C < 0 with E < CE E CE -C junction : eerse ias, -E Junction : Forward ias
Input Output < 0 with < C E CE E must be larger than 0.6 ~ 0.7V i βi 00i C
Analysis of Common-Emitter Amplifier AC VL in Circuits Input () t i ( t) ( t) + DC Output + in E V CC C i C + CE
Load-Line Analysis of Input ( t) i ( t) ( t) V + + in E 0 E in 0 : Q point AC swing around Q Point Max i Min i i 0 Min in ( t), ( in t), i / DC AC ias Max in
V i + CC Load-Line Analysis of Output C C CE Max i From Input Analysis i can be Selected i β i C Min i Min CE Max CE Positie Negatie CE : Inerting Amplifier
in ( t) 0.4sin(2000πt) 2kΩ 40kΩ 0V 40µA.6V Q point : only DC component. 6V.6V i.6 3 0 40µ 40 5µ A i 35µ A A
5µ A i 35µ A IN :.2 ~ 2.0V CE : 7 ~ 3 V A 7/.2 5
Nonlinear Distortion in () t 0.4sin(2000πt) Output Signal is not Exactly Sine Cure in () t.2sin(2000πt) Clipping Occur : Cutoff
PNP ipolar Junction Transistors Except for reersal of current directions and oltage polarities, pnp JT is almost identical to the npn JT. i i i + i i E E C E I ES exp VT β C i
Very Typical Transistor Connection Common-Emitter Amplifier
Operating egion of Transistors When i C becomes zero, we say that the transistor is cutoff. When CE 0.2 V, we say that the transistor is in saturation.
Large-Signal DC Circuit DC ias CC C Actie egion Saturation Cut-off CC
Large-Signal DC Circuit Model Cutoff-egion Saturation-egion Actie-egion T : Open Circuit T : Constant Voltage Source of -0.2V Collector Voltage T : Dependant Current Sourc with ase Voltage 0.7V
Input Output CC C Cut-off Saturation Actie CC
5V Analysis of Fixed ase ias Circuit 200kΩ C kω V CC 5V 0kΩ kω i CC 0.7 CC 0.2 7.5 A ic 4. 8mA µ C I β 00 : i > 0 & i C > βi Actie egion ic β i 00 7.5µ A 7. 5mA VCE VCC C IC 7. 85V
5V 00kΩ I kω β 300 i CC 0.7 CC 0.2 7.5 A ic 4. 8mA C µ i > 0 & i C < βi Saturation egion ic β i 300 7.5µ A 2. 45mA V CE 0. 2V
2kΩ 5V 5V 2kΩ 0. 7 + I V + V E E ( β + ) E V 0.7 I E 2. 5mA E i i + i i β i E C C I + + CC β 00 300 C C I (µa) 2.3 7.4 CE I C (ma) 2.3 2.4 I E E V CE (V) 6.44 6.42
Analysis of Four-esistor ias Circuit Théenin Equialent : + 2 2 V VCC + Two esistor connected to ase Set,,i 2 2
KVL around -E Loop V I + V + E KCL around C--E Node I ( β +) E I E I E E 0.7V I V + KVL around C-E Loop V E ( β + ) E I βi C V CE V CC C I C E I E
Example of Four-esistor ias Circuit I C E 0.7V β 00 I CC 5V 3. Ω + 33k I 2 2 V VCC 5V + V VE 4.2 A IC βi 4. 2mA + µ ( ) β + E VCE VCC C IC EI E 6. 72V 2
Typical JT Circuit (AC Coupled) Q point is set by ias Circuit with, o Describe JT with Characteristic Model. Variation around Q point is smaller than that of Q point itself Small Signal Circuit Model is equired. i C is dependant on i or E as Described in aboe Figure Dependant Current Source Model can be used i swings around Q point E swings around Q poin
Small Signal Model for JT No Passie Element along Emitter Hybrid-π Model ase : esistor r π ollector : Voltage Controlled Current Source ase : esistor r π Collector : Current Controlled Current Source
No Element along ase T Model ase : esistor r e ollector : Voltage Controlled Current Source ase : esistor r e Collector : Current Controlled Current Source
Small-Signal Equialent Circuit i ( t) i i ( t) + Q i b (t) : Signal current flowing into ase I Q : DC current that flows with Zero Signa i (t) : Total ase current. ( t) V ( t) b + E EQ be I Q b (t) : Signal current flowing into ase EQ : DC current that flows with Zero Si E (t) : Total ase current. EQ
i I I I E ( α) I exp ES VT Q Q Q EQ + be( t) + i () t ( α) I ES exp VT EQ ( α) I ES exp VT + i Define be( t) () + be( t) t I Q exp I Q VT VT V T i π () t I Q r r π βv I T i From Preious Definition of Q point C i be r π () t I i ( t) Q + ( t) ( t) βi ( t) b b
Small-Signal Equialent Circuit for the JT V T i ( t) βi ( t) π I C b CQ r β
Typical JT Amplification Mode C E Output Terminal Choice. Common Emitter 2. Emitter Follower (Common Collector 3. Common ase
Common-Emitter Amplifier C, C 2 : Coupling Capacitor without Affecting DC bias from Input & Output (High Pass Filt AC signal only Pass C E : ypass Capacitor Low Impedance path for AC I E to Ground (Same as C,C 2 ) for Midband Frequency mall Signal Equialent Circuit
C : Coupling Capacitor without Affecting DC bias from Input (High Pass Filter) : AC signal only Pass, 2 : See Four esistor ias Parallel to ase - Emitter 2 + 2 V V CC + 2 2
C 2,C E : Coupling Capacitor without Affecting DC bias from Input (High Pass Filter) : AC only Pass C E : Short Circuit to Ground C, L : See Four esistor ias Parallel to Collector - Emitter ' Total C L + C npn Transistor Hybrid π Model L
Small-Signal ac Equialent Circuit C L C L L + 2 2 + π β r A L o in π β r A C o o in i b r π be in b L i β ' o Open Circuit : L 0
Input Impedance & Gains Z in i in in + r π A i i i / o o in in / Z L in A Z in L G A i A
Output Impedance Using Thenin Equialent Circuit without Load Zeroing Voltage Source Z o C
Common-Emitter Amplifier C, C 2 : Coupling Capacitor C E : ypass Capacitor r π βv I T CQ 2 L L C A A o Lβ r π C β Z A in i A Z + in r π G A i A Z o C
in.0sin( ωt) mv r π A A o βvt 63Ω ICQ Lβ 06 rπ C β 58 r π in in s 0. 55 s 3. 33kΩ Z A in i Ω + 53 A 2 r π Zin 28. L 667Ω G Z L L A A i Z A 54.6 54.6sin( ωt mv o in s ) C kω o C 2980
Source Output
Wae form in Common-Emitter Amp
Emitter Followers C, C 2 : Coupling Capacitor
2 + 2 L L E L + E
Een though the oltage gain of the emitter follower is less than unity, the current gain and power gain can be large. A r ( + β ) L + ( + β ) L π Z i + Z it Z A it i A Z i L in Z it r + β π i b G A i A ( + ) L
Output Impedance s s + + 2 Z o i x x ( + β ) ( s + rπ ) + E
Parallel Connection Darlington Configuration