Quad 2-input NND gate Rev. 5 25 November 200 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin compatible with Low-power Schottky TTL (LSTTL). The provides a quad 2-input NND function. Input levels: For 74HC00: CMOS level For 74HCT00: TTL level ESD protection: HBM JESD22-4F exceeds 2000 V MM JESD22-5- exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +25 C Table. Ordering information Type number Package Temperature range Name Description Version 74HC00N 40 C to +25 C DIP4 plastic dual in-line package; 4 leads (300 mil) SOT27-74HCT00N 74HC00D 40 C to +25 C SO4 plastic small outline package; 4 leads; body width SOT08-74HCT00D 74HC00DB 40 C to +25 C SSOP4 3.9 mm plastic shrink small outline package; 4 leads; body SOT337-74HCT00DB 74HC00PW 40 C to +25 C TSSOP4 width 5.3 mm plastic thin shrink small outline package; 4 leads; SOT402-74HCT00PW 74HC00BQ 40 C to +25 C DHVQFN4 body width 4.4 mm plastic dual in-line compatible thermal enhanced very SOT762-74HCT00BQ thin quad flat package; no leads; 4 terminals; body 2.5 3 0.85 mm
Quad 2-input NND gate 4. Functional diagram 2 4 5 B 2 2B Y 2Y 3 6 2 4 5 & & 3 6 9 0 2 3 3 3B 4 4B 3Y 8 4Y mna22 9 0 2 3 & & mna246 8 B Y mna2 Fig. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5. Pinning 74HC00 74HCT00 terminal index area 74HC00 74HCT00 VCC B Y 2 3 4 3 2 V CC 4B 4 B Y 2 4 2 3 3 2 4 4B 4 4Y 2 2B 2Y 4 5 6 0 9 4Y 3B 3 2B 2Y 5 GND () 0 6 9 7 8 3B 3 GND 7 8 3Y GND 3Y 00aal324 00aal323 Transparent top view () This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration DIP4, SO4 and (T)SSOP4 Fig 5. Pin configuration DHVQFN4 5.2 Pin description Table 2. Pin description Symbol Pin Description to 4, 4, 9, 2 data input B to 4B 2, 5, 0, 3 data input 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V. 200. ll rights reserved. Product data sheet Rev. 5 25 November 200 2 of 6
Quad 2-input NND gate Table 2. Pin description continued Symbol Pin Description Y to 4Y 3, 6, 8, data output GND 7 ground (0 V) V CC 4 supply voltage 6. Functional description Table 3. Function table [] Input Output n nb ny L X H X L H H H L [] H = HIGH voltage level; L = LOW voltage level; X = don t care. 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 6034). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage 0.5 +7 V I IK input clamping current V I < 0.5 V or V I >V CC +0.5 V [] - 20 m I OK output clamping current V O < 0.5 V or V O >V CC +0.5V [] - 20 m I O output current 0.5 V < V O < V CC +0.5V - 25 m I CC supply current - 50 m I GND ground current 50 - m T stg storage temperature 65 +50 C P tot total power dissipation [2] DIP4 package - 750 mw SO4, (T)SSOP4 and DHVQFN4 packages - 500 mw [] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP4 package: P tot derates linearly with 2 mw/k above 70 C. For SO4 package: P tot derates linearly with 8 mw/k above 70 C. For (T)SSOP4 packages: P tot derates linearly with 5.5 mw/k above 60 C. For DHVQFN4 packages: P tot derates linearly with 4.5 mw/k above 60 C. 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V. 200. ll rights reserved. Product data sheet Rev. 5 25 November 200 3 of 6
Quad 2-input NND gate 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC00 74HCT00 Unit Min Typ Max Min Typ Max V CC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V V I input voltage 0 - V CC 0 - V CC V V O output voltage 0 - V CC 0 - V CC V T amb ambient temperature 40 +25 +25 40 +25 +25 C t/ V input transition rise and fall rate V CC = 2.0 V - - 625 - - - ns/v V CC = 4.5 V -.67 39 -.67 39 ns/v V CC = 6.0 V - - 83 - - - ns/v 9. Static characteristics Table 6. Static characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit Min Typ Max Min Max Min Max 74HC00 V IH HIGH-level V CC = 2.0 V -.2 -.5 -.5 - V input voltage V CC = 4.5 V - 2.4-3.5-3.5 - V V CC = 6.0 V - 3.2-4.2-4.2 - V V IL LOW-level V CC = 2.0 V - 0.8 - - 0.5-0.5 V input voltage V CC = 4.5 V - 2. - -.35 -.35 V V CC = 6.0 V - 2.8 - -.8 -.8 V V OH HIGH-level output voltage V I = V IH or V IL I O = 20 ; V CC = 2.0 V - 2.0 -.9 -.9 - V I O = 20 ; V CC = 4.5 V - 4.5-4.4-4.4 - V I O = 20 ; V CC = 6.0 V - 6.0-5.9-5.9 - V I O = 4.0 m; V CC = 4.5 V - 4.32-3.84-3.7 - V I O = 5.2 m; V CC = 6.0 V - 5.8-5.34-5.2 - V V OL LOW-level output voltage V I = V IH or V IL I O = 20 ; V CC = 2.0 V - 0 - - 0. - 0. V I O = 20 ; V CC = 4.5 V - 0 - - 0. - 0. V I O = 20 ; V CC = 6.0 V - 0 - - 0. - 0. V I O = 4.0 m; V CC = 4.5 V - 0.5 - - 0.33-0.4 V I O = 5.2 m; V CC = 6.0 V - 0.6 - - 0.33-0.4 V I I input leakage V I = V CC or GND; - - - - - current V CC =6.0V I CC supply current V I = V CC or GND; I O =0; V CC =6.0V - - - - 20-40 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V. 200. ll rights reserved. Product data sheet Rev. 5 25 November 200 4 of 6
Quad 2-input NND gate Table 6. Static characteristics continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit Min Typ Max Min Max Min Max C I input - 3.5 - - - - - pf capacitance 74HCT00 V IH HIGH-level V CC = 4.5 V to 5.5 V -.6-2.0-2.0 - V input voltage V IL LOW-level V CC = 4.5 V to 5.5 V -.2 - - 0.8-0.8 V input voltage V OH HIGH-level output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 20-4.5-4.4-4.4 - V I O = 4.0 m - 4.32-3.84-3.7 - V V OL LOW-level output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 20 ; V CC = 4.5 V - 0 - - 0. - 0. V I O = 5.2 m; V CC = 6.0 V - 0.5 - - 0.33-0.4 V I I input leakage V I = V CC or GND; - - - - - current V CC =6.0V I CC supply current V I = V CC or GND; I O =0; V CC =6.0V - - - - 20-40 I CC C I additional supply current input capacitance per input pin; V I =V CC 2. V; I O =0; other inputs at V CC or GND; V CC = 4.5 V to 5.5 V 0. Dynamic characteristics - 50 - - 675-735 - 3.5 - - - - - pf Table 7. Dynamic characteristics GND = 0 V; C L = 50 pf; for load circuit see Figure 7. Symbol Parameter Conditions 25 C 40 C to +25 C Unit Min Typ Max Max (85 C) Max (25 C) 74HC00 t pd propagation delay n, nb to ny; see Figure 6 [] V CC = 2.0 V - 25-5 35 ns V CC = 4.5 V - 9-23 27 ns V CC = 5.0 V; C L =5pF - 7 - - - ns V CC = 6.0 V - 7-20 23 ns t t transition time see Figure 6 [2] V CC = 2.0 V - 9-95 0 ns V CC = 4.5 V - 7-9 22 ns V CC = 6.0 V - 6-6 9 ns 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V. 200. ll rights reserved. Product data sheet Rev. 5 25 November 200 5 of 6
Quad 2-input NND gate Table 7. Dynamic characteristics continued GND = 0 V; C L = 50 pf; for load circuit see Figure 7. Symbol Parameter Conditions 25 C 40 C to +25 C Unit C PD power dissipation per package; V I =GNDtoV CC [3] - 22 - - - pf capacitance 74HCT00 t pd propagation delay n, nb to ny; see Figure 6 [] V CC = 4.5 V - 2-24 29 ns V CC = 5.0 V; C L =5pF - 0 - - - ns t t transition time V CC = 4.5 V; see Figure 6 [2] - - - 29 22 ns C PD power dissipation capacitance [] t pd is the same as t PHL and t PLH. [2] t t is the same as t THL and t TLH. [3] C PD is used to determine the dynamic power dissipation (P D in W): P D =C PD V CC 2 f i N+ (C L V CC 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs.. Waveforms per package; V I =GNDtoV CC.5 V Min Typ Max Max (85 C) Max (25 C) [3] - 22 - - - pf V I n, nb input V M GND ny output V OH t PHL V Y V M V X t PLH V OL t THL t TLH 00aai84 Fig 6. Measurement points are given in Table 9. V OL and V OH are typical voltage output levels that occur with the output load. Input to output propagation delays Table 8. Measurement points Type Input Output V M V M V X V Y 74HC00 0.5V CC 0.5V CC 0.V CC 0.9V CC 74HCT00.3 V.3 V 0.V CC 0.9V CC 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V. 200. ll rights reserved. Product data sheet Rev. 5 25 November 200 6 of 6
Quad 2-input NND gate V I 90 % negative pulse GND V M 0 % t f t W V M t r V I positive pulse 0 % GND t r 90 % V M t W t f V M V CC G VI DUT VO RT CL 00aah768 Fig 7. Test data is given in Table 9. Definitions test circuit: R T = termination resistance should be equal to output impedance Z o of the pulse generator. C L = load capacitance including jig and probe capacitance. Load circuitry for measuring switching times Table 9. Test data Type Input Load Test V I t r, t f C L 74HC00 V CC 6.0 ns 5 pf, 50 pf t PLH, t PHL 74HCT00 3.0 V 6.0 ns 5 pf, 50 pf t PLH, t PHL 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V. 200. ll rights reserved. Product data sheet Rev. 5 25 November 200 7 of 6
Quad 2-input NND gate 2. Package outline DIP4: plastic dual in-line package; 4 leads (300 mil) SOT27- D M E seating plane 2 L Z 4 e b b 8 w M c (e ) M H pin index E 7 0 5 0 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 2 () () min. max. b b c D E e e L M E M H 4.2 0.5 3.2 0.7 0.02 0.3.73.3 0.068 0.044 0.53 0.38 0.02 0.05 0.36 0.23 0.04 0.009 9.50 8.55 0.77 0.73 6.48 6.20 0.26 0.24 2.54 7.62 0. 0.3 3.60 3.05 0.4 0.2 8.25 7.80 0.32 0.3 0.0 8.3 0.39 0.33 w 0.254 0.0 () Z max. 2.2 0.087 Note. Plastic or metal protrusions of 0.25 mm (0.0 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT27-050G04 MO-00 SC-50-4 99-2-27 03-02-3 Fig 8. Package outline SOT27- (DIP4) 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V. 200. ll rights reserved. Product data sheet Rev. 5 25 November 200 8 of 6
Quad 2-input NND gate SO4: plastic small outline package; 4 leads; body width 3.9 mm SOT08- D E X c y H E v M Z 4 8 Q pin index 2 ( ) 3 θ L p 7 L e b p w M detail X 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 0.25.75 0.0 0.069 0.00 0.004 2 3 b p c D () E () e H () E L L p Q v w y Z.45.25 0.057 0.049 0.25 0.0 0.49 0.36 0.09 0.04 0.25 0.9 0.000 0.0075 8.75 8.55 0.35 0.34 4.0 3.8 0.6 0.5.27 6.2 5.8 0.244 0.228 Note. Plastic or metal protrusions of 0.5 mm (0.006 inch) maximum per side are not included. 0.05.05 0.04.0 0.4 0.039 0.06 0.7 0.6 0.028 0.024 0.25 0.25 0. 0.0 0.0 0.004 θ 0.7 0.3 o 8 o 0.028 0 0.02 OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT08-076E06 MS-02 99-2-27 03-02-9 Fig 9. Package outline SOT08- (SO4) 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V. 200. ll rights reserved. Product data sheet Rev. 5 25 November 200 9 of 6
Quad 2-input NND gate SSOP4: plastic shrink small outline package; 4 leads; body width 5.3 mm SOT337- D E X c y H E v M Z 4 8 Q 2 ( ) 3 pin index 7 detail X L p L θ e b p w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E () e H E L L p Q v w y Z() max. 0.2.80 0.38 0.20 6.4 5.4 7.9.03 0.9.4 mm 2 0.25 0.65.25 0.2 0.3 0. 0.05.65 0.25 0.09 6.0 5.2 7.6 0.63 0.7 0.9 θ o 8 o 0 Note. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT337- MO-50 99-2-27 03-02-9 Fig 0. Package outline SOT337- (SSOP4) 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V. 200. ll rights reserved. Product data sheet Rev. 5 25 November 200 0 of 6
Quad 2-input NND gate TSSOP4: plastic thin shrink small outline package; 4 leads; body width 4.4 mm SOT402- D E X c y H E v M Z 4 8 pin index 2 Q ( ) 3 θ 7 e b p w M detail X L p L 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E (2) e H () E L L p Q v w y Z max. mm. 0.5 0.05 0.95 0.80 0.25 0.30 0.9 0.2 0. 5. 4.9 4.5 4.3 0.65 6.6 6.2 0.75 0.50 0.4 0.3 0.2 0.3 0. 0.72 0.38 θ o 8 o 0 Notes. Plastic or metal protrusions of 0.5 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT402- MO-53 EUROPEN PROJECTION ISSUE DTE 99-2-27 03-02-8 Fig. Package outline SOT402- (TSSOP4) 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V. 200. ll rights reserved. Product data sheet Rev. 5 25 November 200 of 6
Quad 2-input NND gate DHVQFN4: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 4 terminals; body 2.5 x 3 x 0.85 mm SOT762- D B E c terminal index area detail X terminal index area e e b 2 6 v M w M C C B y C C y L 7 E h e 4 8 3 9 D h X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT () max. b c D () D h E () Eh e e L v w y y mm 0.05 0.00 0.30 0.8 0.2 3. 2.9.65.35 2.6 2.4.5 0.85 0.5 2 0.5 0.3 0. 0.05 0.05 0. Note. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT762- - - - MO-24 - - - EUROPEN PROJECTION ISSUE DTE 02-0-7 03-0-27 Fig 2. Package outline SOT762- (DHVQFN4) 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V. 200. ll rights reserved. Product data sheet Rev. 5 25 November 200 2 of 6
Quad 2-input NND gate 3. bbreviations Table 0. cronym CMOS DUT ESD HBM LSTTL MM TTL bbreviations Description Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model Transistor-Transistor Logic 4. Revision history Table. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT00 v.5 20025 Product data sheet - 74HC_HCT00 v.4 Modifications: Figure note [] of Figure 5: changed. 74HC_HCT00 v.4 2000 Product data sheet - 74HC_HCT00 v.3 74HC_HCT00 v.3 20030630 Product data sheet - 74HC_HCT00_CNV v.2 74HC_HCT00_CNV v.2 9970826 Product specification - - 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V. 200. ll rights reserved. Product data sheet Rev. 5 25 November 200 3 of 6
Quad 2-input NND gate 5. Legal information 5. Data sheet status Document status [][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 5.2 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V. 200. ll rights reserved. Product data sheet Rev. 5 25 November 200 4 of 6
Quad 2-input NND gate Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 5.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 6. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V. 200. ll rights reserved. Product data sheet Rev. 5 25 November 200 5 of 6
Quad 2-input NND gate 7. Contents General description...................... 2 Features and benefits.................... 3 Ordering information..................... 4 Functional diagram...................... 2 5 Pinning information...................... 2 5. Pinning............................... 2 5.2 Pin description......................... 2 6 Functional description................... 3 7 Limiting values.......................... 3 8 Recommended operating conditions........ 4 9 Static characteristics..................... 4 0 Dynamic characteristics.................. 5 Waveforms............................. 6 2 Package outline......................... 8 3 bbreviations.......................... 3 4 Revision history........................ 3 5 Legal information....................... 4 5. Data sheet status...................... 4 5.2 Definitions............................ 4 5.3 Disclaimers........................... 4 5.4 Trademarks........................... 5 6 Contact information..................... 5 7 Contents.............................. 6 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 200. ll rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 November 200 Document identifier: 74HC_HCT00